sputtering materials for vlsi and thin film devices || sputtering targets and sputtered films for...

CHAPTER

1Sputtering Targets and SputteredFilms for the MicroelectronicIndustry

1.1 Materials for microelectronics1.1.1 IntroductionThe microelectronic industry arguably uses a wide variety of materials in the form of solid, liquid, gas

and gas plasma in microelectronic device components and for the processing of devices. Figure 1.1

shows these elements in the periodic table. Choices for material selection are made based on the appli-

cations [1]. With the exception of actinides (the bottom-most row) and a few other unstable and less

common elements, most of the elements are used in microelectronics industry. A large number of such

elements and their alloys are used in microelectronics devices in the form of thin films [2�20].

Sputtering is one of the techniques for depositing such thin films in which atoms are ejected from a

source material by using energetic particles inside a chamber [4,6,14]. In principle, the majority of solid

materials can be sputtered under suitable conditions to form thin films. Chapter 2 reviews various sput-

tering methods for depositing thin films and device technology driven evolution of sputtering equip-

ment (also known as sputtering tools). Sputtering can also be used to remove a thin layer of material

from a substrate and this application of sputtering is out of the scope of this book.

The primary focus of this book is to discuss metallurgy and material science of sputtering mate-

rials that are technologically important. These include both: (a) bulk source materials, known as

sputtering targets, and (b) deposited thin films for microelectronic applications. Sputtering target

can be a conductor, semiconductor or an insulator. Conductivity is one of the key parameters that

contrast these three types of solids. As one would expect, a small section of a chapter of this nature

has limited scope to cover this subject. Hence, the following sections will only summarize the gen-

eral characteristics of conduction in conductors, semiconductors and insulators. Afterwards, discus-

sion has been shaped in such a way that readers eventually arrive at those technologically

important materials that are sputtered to form thin films for making commercial device such as

integrated circuits (ICs), displays, magnetic and optical data storage systems, photovoltaic solar cell

and so forth [2�20]. As discussion progresses, readers will note that sputtering is primarily used to

deposit metal-based conductors and not so much for semiconductor and insulators (with some excep-

tions). It is important for readers to note that, in many cases, by the time thin films are sputter deposited

on a substrate, a significant amount of investment has already been done for substrate preparation. As a

result, any failure at the sputter deposition stage will reduce the overall yield and productivity of the

1J. Sarkar: Sputtering Materials for VLSI and Thin Film Devices. DOI: http://dx.doi.org/10.1016/B978-0-8155-1593-7.00001-1

© 2014 Elsevier Inc. All rights reserved.

http://dx.doi.org/10.1016/B978-0-8155-1593-7.00001-1

process. For example, in a complementary metal oxide semiconductor (CMOS) chip manufacturing

process, by the time a cobalt or nickel film is sputter deposited prior to the silicide formation, active

regions have already been formed on the silicon wafer with significant investment.

1.1.1.1 Electrical conductivityThe most common approach to distinguishing conductors, semiconductors and insulators for micro-

electronic applications is based on their electrical conductivity (reciprocal of resistivity) values.

Electrical conductivity (σ) of a material is given by the equation

σ5 n:q:μ (1.1)

where n is the number of carriers, q is the charge and μ is the mobility of the carriers. While con-

ductors have high electrical conductivity (104�106 ohm21 cm21) insulators have low electrical con-

ductivity (#10215 ohm21 cm21) and semiconductors have intermediate electrical conductivity

(1026�103 ohm21 cm21). These boundaries are not rigid and a certain degree of overlap is possible

between these sets of values. In general, the electrical conductivity of the conductors shows a slight

but gradual drop with increasing temperature. This is because n is large for conductors and essen-

tially remains unchanged with temperature. Similarly, q remains constant but the mobility term μdecreases slightly with increasing temperature. The mobility of the carriers decreases because of

the collision between moving electrons and the phonons (lattice vibrations). Silver, copper and gold

are among the best electrical conductors. Transition metals such as iron and nickel are not as good

conductors as above metals. However, for semiconductors and the insulators, n increases dramati-

cally with temperature unlike conductors which outweighs the slight decrease in the mobility term.

As a result, electrical conductivity of semiconductors increases rapidly with temperature.

H

Li

Na

K

Rb

Cs

Fr

Be

Mg

Ca Sc Ti V Cr Mn Fe Co Ni Cu Zn

Sr Y Zr Nb Mo Tc Ru Rh Pd Ag Cd

Ba La Hf

Ce Pr Nd Pm Sm Eu Gd Tb Dy Ho Er Tm Yb Lu

Pa U Np Pu Am Cm Bk Cf Es Fm Md No LwTh

Ta W Re Os Ir Pt Au Hg

Ga

In

Tl

Ge

Sn

Pb

As

Sb

Bi

Se

O

P

NC

Al

B

Te

Po

Br

Cl

F

I

At

Kr

Ar

Ne

He

Xe

Rn

Ra Ac

Dopant

Lanthanide

Actinide

Data storage Superconductors

Processing

Insulators

Semiconductor

Contact

IA

IIA

IIIB IB IIB

IIIA IVA VA VIA VIIA

VIIIA

IVB VB VIB VIIB VIII VIII VIII SSi

FIGURE 1.1

Periodic table showing elements and their applications in microelectronic industry [1].

2 CHAPTER 1 Sputtering Targets and Sputtered Films for Microelectronics

Table 1.1 lists the electrical conductivity of some of the common materials at room temperature.

Figure 1.2 shows the variation of electrical conductivity in aluminum and germanium with tempera-

ture. In fact, insulators are extreme state semiconductors when n is small at normal temperature. In

the following sections, a cursory review of the principles of conduction in solids (conductors, semi-

conductors and insulators) has been presented prior to the discussion of various devices that inte-

grate such materials. Finally, the discussion leads to those conductors, semiconductors and

insulators that are sputtered to form films for device fabrication.

The electronic behavior of solids can be described in terms of band theory or zone theory. The

band theory of solids is well supported by the spectroscopic data and the two independent theoreti-

cal approaches, namely the chemical approach and physical approach. In the chemical approach to

band theory, molecular orbital theory is applied to small and finite molecules and this treatment is

extended to infinite and three-dimensional structures. The physical approach to band theory consid-

ers the energy and the wavelength of electrons in a solid. From either theory, one obtains a model

with bands of energy levels for the valence band (the outermost energy band of an atom that is

fully or partially filled) electrons and conduction band (the band that is above the valence band and

is empty at 0 K) electrons.

Figure 1.3 shows such bands and forbidden energy regions known as band gap. Metals are good

examples of conductors that have partially filled energy bands. As shown in Figure 1.3(a), in a con-

ductor, conduction and valence bands overlap. A small electric field is adequate to induce conduc-

tion or current flow. Semiconductors typically have small band gap (,3.0 eV). As shown in

Figure 1.3(b), the most popular semiconductor silicon has band gap energy of 1.11 eV at 300�K.

Table 1.1 Electrical Conductivity of Selected Bulk Materials

Materials Conductivity (Ohm21 cm21)

Metals

Silver (Ag) 6.803 105

Copper (Cu) 5.983 105

Gold (Au) 4.263 105

Aluminum (Al) 3.773 105

Nickel (Ni) 1.463 105

Iron (Fe) 1.003 105

Semiconductors

Silicon (Si) 5.003 1026

Germanium (Ge) 2.003 1022

Insulators

Silica glass 10217

Alumina (Al2O3) 10214

Silicon carbide (SiC) 1021 to 1022

Boron nitride (BN) 10213

31.1 Materials for microelectronics

FIGURE 1.3

Characterization of conductor, semiconductor and insulating materials using band gap. Solids with band gap

between 0.5 and 3.0 eV are known as semiconductors. Here Si is shown as a representative semiconductor.

Materials with more than 2 eV band gap are known as insulators.

106

105

100

10.0

1.00

0.10

0.010 100 200 300

Temperature (°C)400

Aluminum

Germanium

Ele

ctric

al c

ondu

ctiv

ity (O

hm–1

.cm

–1)

Increasing chargecarriers

Reducingmobility

FIGURE 1.2

Variation of electrical conductivity in aluminum (Al) and germanium (Ge) with temperature.


This is 1.21 eV at 0�K. Energies of this magnitude cannot usually be achieved from applied electric

field to induce conduction. Table 1.2 lists band gap energy values of various industrially important

semiconductors. Insulators have very wide band gap (. 3.0 eV), as shown in Figure 1.3(c). Energy

of this magnitude cannot be obtained from an external electric field. In-depth discussions of this

subject can be found in books devoted to solid state physics [21,22]. In the following sections,

some important properties of conductors, semiconductors and insulators and methods of thin film

deposition for microelectronic applications are summarized.

Table 1.2 Band Gap Width and the Nature of Semiconductor Materials at 300 K

Semiconductor Band Gap (eV) Type

Element

Silicon (Si) 1.11 Indirect

Germanium (Ge) 0.66

III-V Compounds

Gallium arsenide (GaAs) 1.43 Direct

Gallium phosphide (GaP) 2.26 Indirect

GaSb 0.72 Direct

InAs 0.36 Direct

Indium phosphide (InP) 1.35 Direct

InSb 0.17 Direct

AlAs 2.16 Indirect

AlSb 1.58 Indirect

II-VI Compounds

Cadmium sulfide (CdS) 2.42 Direct

Cadmium selenide 1.7 Direct

Cadmium telluride (CdTe) 1.49 Direct

ZnS 3.68 Direct

ZnSe 2.7 Direct

ZnTe 2.2 Direct

Copper indium diselenide(CuInSe2, CIS)

1.01 Direct

Copper indium gallium diselenide(CuInxGa1-xSe2, x: 0�1, CIGS)

1.0�1.7 Direct

IV-VI Compounds

PbS 0.41 Direct

PbSe 0.27 Direct

PbTe 0.31 Direct

SnTe 0.18 Direct

Amorphous material

Amorphous silicon (a-Si) 1.6 Direct


1.1.2 ConductorsSome of the best conductors are copper, aluminum, gold and silver. Conductor thin films for ICs

and other thin film devices encompass a wide variety of metallic materials. For ICs, conducting

films are used to supply power and transmitting information from one part of the device to the

other. The properties that need to be met by such conducting thin films include ease of deposition,

low resistivity (high conductivity), stability during manufacturing and use, ability to form low resis-

tance contacts, adhesion to the surrounding materials, patternability, resistance to electromigration

and stress migration, and compatibility with lead material.

Table 1.3 lists important conducting materials, their deposition methods and their selective

properties that are used in very large scale integration (VLSI). It is clear that sputtering is used

extensively to form such conducting films. As we move on to the other devices such as thin film

transistor liquid crystals displays (TFT-LCDs), storage devices and photovoltaic cells, we will see

more application methods of conducting thin films.

1.1.3 SemiconductorsBased on the chemical composition, semiconductors are divided into two categories, namely ele-

mental and compound (Figure 1.4). Classic examples of elemental semiconductors are silicon

(Si) and germanium (Ge) that are found in group IV of the periodic table. Both of these ele-

ments have a diamond structure in which each atom is tetrahedrally surrounded by four other

atoms. In 1948, Ge was used as a semiconductor in constructing a transistor by John Bardeen,

Table 1.3 Examples of Popular Metal Based Conducting Materials used in VLSI

Conductor Symbol Melting Point(°C)

DepositionMethod

Resistivity(μΩcm)�

Adhesion toDielectric

Aluminum Al 660 Sputter 2.65 Very high

Copper Cu 1083 Sputter & EP 1.68 High

Al (0.5�4.0 wt% Cu) AlCu B650 Sputter 2.95 Very high

Al (1�2 wt% Si) AlSi B640 Sputter 2.69 Very high

Al-Cu-Si AlCuSi � Sputter 2.93 Very high

Titanium Ti 1688 Sputter & CVD 42 Very high

Tantalum Ta 2996 Sputter 12.45 High

Nickel Ni 1453 Sputter 6.84 High

Cobalt Co 1495 Sputter 5.6 High

Tungsten W 3410 Sputter & CVD 5.65 High

Titanium�Tungsten TiW � Sputter 65 Very high

Gold Au 1063 Sputter & Evap 2.35 Low

�Resistivity can be thickness dependent, EP: Electroplating, Evap: Evaporation, CVD: Chemical vapor deposition.


William Shockley and Walter Brattain at Bell Laboratory, USA. The most common inorganic

compound semiconductors are group III-V compounds and most of them have zinc blende struc-

ture (closely related to the diamond structure). Various other compounds such as oxides, sul-

phides that have different crystal structures are also in use as semiconductors. Table 1.2 lists the

most common semiconductors used in microelectronic industry and their important properties

(band gap and nature).

Based on the conduction mechanism semiconductors can be divided into two categories, namely

intrinsic and extrinsic semiconductors. In intrinsic semiconductors the conduction takes place due

to the intrinsic process characteristics (band gap energy and temperature) and without the influence

of any specific foreign material (dopant). High purity Si and Ge are two intrinsic semiconductors.

Because of the small band gap energy, the electrons that are excited by thermal energy from the

top of the valence band to the bottom of the conduction band are responsible for the conduction.

The excited electrons leave behind vacant electron sites in the valence band, called holes, which

act like positive charge carriers. When an electrical field is applied to the intrinsic semiconductor,

the electrons in the conduction band accelerate towards the positive terminal, while holes in the

valence band move toward the negative terminal. Therefore, a current is generated by the move-

ment of both electrons and holes. The number of charge carriers depend on the temperature in an

exponential way (follows Arrhenius equation) and increases rapidly with increasing temperature.

As a result conductivity of the semiconductor also increases in a similar fashion with increasing

temperature. Note that in this respect the behavior of semiconductors is different than metals. This

difference in behavior is shown in Figure 1.2.

In extrinsic semiconductors conductivity is controlled by intentionally adding a small amount of

a specific element, which is called doping. Such doping action can make the material either

electron-rich (n-type semiconductor) or hole-rich (p-type semiconductor). Table 1.4 lists important

dopants for the elemental and compound semiconductors and their doping characteristics. In terms

of percentage, dopant content varies between 0.000001% and 0.1% to bring a semiconductor to a

useful conductivity range. As we move on to other chapters for discussing various microelectronic

devices, e.g., integrated circuits, flat panel displays and photovoltaic cells, we will see the use of

several compound semiconductors.

Elemental

III-V: GaAs, InP, GaN

II

Zn

Cd

III

III-VI

Semiconductor materials

III-V

B

A1

Ga

In

IV

C

Si

Ge

Sn

V

N

P

As

Sb

VI

O

S

Se

Te

Si, Ge

II-VI: ZnS, ZnSe

Compound

FIGURE 1.4

Examples of elemental and common compound semiconductors used in the microelectronics industry.


1.1.4 InsulatorsFor traditional applications, an insulator should possess high dielectric strength (ability to withstand

high voltage without undergoing degradation and becoming electrically conducting) and should

have low dielectric loss in an alternating electric field. The dielectric constant, k, of an insulator,

which is a measure of electrical polarizability of a material, is given by

Table 1.4 Dopants for Elemental and Compound Semiconductors and their

Doping Characteristics

Semiconductor Dopant Doping Character

Si Phosphorus (P) n-Type

Arsenic (As) n-Type

Antimony (Sb) n-Type

Boron (B) p-type

Aluminum (Al) p-type

GaAs Tellurium (Te) n-Type

Sulphur (S) n-Type

Tin (Sn) n-Type

Silicon (S) n-Type

Germanium (Ge) n-Type

Zinc (Zn) p-type

Chromium (Cr) p-type

Silicon (Si) p-type

Germanium (Ge) p-type

GaP Tellurium (Te) n-Type

Selenium (Se) n-Type

Sulphur (S) n-Type

Zinc (Zn) p-type

Magnesium (Mg) p-type

Tin (Sn) p-type

CdTe Indium (In) n-Type

Aluminum (Al) n-Type

Chlorine (Cl)) n-Type

Phosphorus (P) p-type

Lithium (Li) p-type

Sodium (Na) p-type

CdS Gallium (Ga) n-Type

Iodine (I) n-Type

Fluorine (F) n-Type

Lithium (Li) p-type

Sodium (Na) p-type


K5εε0

5ε0ð11χeÞ

ε0

� �5 11χe (1.2)

Here, ε and ε0 are the permittivity of the material and the free space, respectively. χe is the

electrical susceptibility of the insulating material and the unit-less constant of proportionality. In a

perfect vacuum, χe5 0 because there are no atoms to polarize. As a result, k5 1. The polarization

mechanisms, namely electronic, atomic and dipolar, are identified in solid-state material. Electronic

polarization occurs when an electric field displaces the nucleus with respect to the electrons that

surround it. Atomic polarization results when negative and positive ions stretch under an electric

field. Dipolar polarization occurs when permanent dipoles in asymmetric molecules respond to an

electric field. Each polarization mechanism is linked to response time under applied electric field

as shown in Figure 1.5.

In microelectronic devices and in particular in ICs, insulating layers are used as inter-level

dielectric (ILD) to physically separate and electrically isolate conducting layers from each other. In

the vicinity of active regions in a chip, dielectric deposition and property requirements are different

than the inter-metal dielectric that separates intermediate and global interconnects (see Figure 1.13

for definitions). Earlier ILDs for ICs were usually oxides with k ranging from 4.0 to 4.5. Low

dielectric constant (in order to lower interconnect capacitance), high breakdown field strength and

low leakage are usually the dielectric property requirements for such applications. Table 1.5 lists

common insulators used in ICs and their deposition techniques [3]. Note that sputtering is conven-

tionally not used for depositing insulating thin films for ICs. For data storage applications, in par-

ticular in head fabrication, RF sputtering is selectively used for depositing alumina.

1.2 Scope of sputtering in microelectronicsThe phenomenon of sputtering, then called cathodic disintegration, was first reported in 1852 by

Sir William Robert Grove of England. Cathodic disintegration referred to ejection of small parti-

cles. He used a silver-coated copper cathode and a manual hand-operated pump to create a vacuum

dipolar

Die

lect

ric c

onst

ant

atomic electronic

10181015109 1012

Frequency (Hz)

106103

FIGURE 1.5

Response of dielectric under various frequencies.

91.2 Scope of sputtering in microelectronics

of the order of 10 torr. The working gas was introduced into the glass bell-jar from a gas filler blad-

der through a stopcock. Figure 1.6(a) shows the schematic of the original set-up used by W. R.

Grove [23]. Later in 1921, Sir John Thompson renamed cathodic disintegration to spluttering (note

l). Two years later, John Thompson dropped the letter l from spluttering. Ever since, sputtering has

been used to describe cathodic disintegration of materials. The fundamental of this physical process

was better understood in late 19th century and early 20th century (Figure 1.6(b)).

With the development in the area of microelectronics, sputtering found an important place in

solid state device manufacturing. Slowly sputtering started to replace evaporation because of the

coming of DC magnetron (see Section 2.4.4 of Chapter 2 for details) and progress in vacuum tech-

nology in 1970s. In fact, sputtering improved step coverage (see Figure 2.2, Chapter 2) and better

controlled alloy thin film composition. It was possible to sputter Al-Cu, Al-Cu-Si and Ti-W con-

ducting thin films for interconnections. Unlike in evaporation, a single alloy target was used for

sputtering and these sputtered films retained stoichiometry. Other aspects such as purity, micro-

structure, resistivity and surface roughness of the films were found to be satisfactory. For relatively

low aspect ratio structures (see Figure 2.2, Chapter 2), satisfactory step coverage was achieved.

Table 1.5 Examples of Industrial Insulators used in Microelectronic Industry [3]

Insulator Symbol Type DepositionMethod

DielectricConstant

Silicon nitride Si3N4 Inorganic CVD 5.8�6.1

Silicon dioxide (PSG, BPSG) SiO2 Inorganic CVD, oxidation,bias sputtering

3.9�5.0

Spin-on-glass (PSG, BPSG) SOG Inorganic Spin-on-dielectric(SOD)

3.9�5.0

Modified SiO2 (e.g., fluorinatedSiO2, hydrogen silses-quioxane, HSQ)

� Inorganic CVD, SOD 2.8�3.8

Boron nitride (Si) BN(Si) Inorganic CVD .2.9

Polymide � Organic SOD, CVD 2.9�3.9

Fluorinated polymide � Organic SOD, CVD 2.3�2.8

Fluoropolymer � Organic SOD, CVD 1.8�2.2

Fluorine doped amorphouscarbon

� Organic CVD 2.0�2.5

Si-O-C hybrid polymers basedon organosilses�quioxanes(e.g., MSQ)

� Hybrids SOD 2.0�3.8

Porous SiO2 � Inorganic SOD 1.2�1.8

Gate oxide � Inorganic Thermally grown �Field oxide � Inorganic Thermally grown �Air/vacuum � � Air bridge 1.0�1.2

PSG: Phospho-silicate glass, BPSG: Boro-phospho-silicate glass; CVD: Chemical vapor deposition.


This was possible because sputtering is done from an extended source and shadowing effect is min-

imal. With wafer size increase (150 mm in 1987, 200 mm in 1992, 300 mm in 2000), it was possi-

ble to scale up magnetron size and sputtering target size (Figure 1.7).

Figure 1.7(a�d) shows examples of sputtering targets of various shapes and sizes that are used

in chip making, displays and photovoltaic cells [24]. These are disc-shaped bonded sputter target, a

dome-shaped hollow cathode magnetron target, a rectangular target and cylindrical target. A mod-

ern cluster tool (Enduras of Applied Materials Inc.), with sputtering chambers, which can sputter

disc-shaped targets is shown in Figure 1.7(e) [25]. A few examples of sputtering tools for other

Landmarks in sputter research

–Cathodic disintegration(W.R. Grove, 1852)

–Spluttering to describe disintegration(J. Thompson, 1921)

–Sputtering (dropped ‘I’)(J. Thompson, 1923)

–Sputter yield measurement(K.H. Kingdon & I. Langmuir, 1923)

–Cosine law(R. Seelinger & K. Sommermeyer, 1935)

(b)

FIGURE 1.6

(a) First experimental setup used for sputtering silver coated copper cathode [23], (b) historical landmarks in

sputter research.

111.2 Scope of sputtering in microelectronics

applications (e.g., display, magnetic media and solar cell manufacturing) are shown in latter sec-

tions. Depending on the device requirements, with such sputtering tools, materials can be sputter

deposited at required length scales.

Figure 1.8 shows such deposited material systems and their length scales for modern thin film

devices [26]. If one chooses the metal/semiconductor device option from this plot, an integrated

chip cross-section can reveal various materials at different length scales as given in the X-axis of

the plot. Figure 1.9 (p. 14) shows the entire cross-section of a chip that has five levels of metalliza-

tion [27]. Note the front end of line (FEOL), back end of line (BEOL) and back end in the form of

(a)

(d) (e)

(b) (c)

FIGURE 1.7

Examples of sputtering targets used in various microelectronic applications. (a) Diffusion bonded sputtering

target for semiconductor industry, (b) hollow cathode magnetron target for semiconductor industry, (c)

rectangular target for display and photovoltaic industries, (d) tubular target for display and photovoltaic

industries, [24], and (e) a cluster tool of Applied Materials (Enduras) showing sputtering targets and open

chambers for depositing sputtered films on 200 mm wafers [25].


under bump metallization (UBM). As leveled, cobalt silicide, tungsten plug, tantalum nitride barrier

layer, copper interconnect, etc., are formed by using suitable sputtering methods. Similarly, UBM

and bond pad (not shown here) preparation require sputtered thin films that have been discussed in

the assembly and packaging section. Similarly, other devices can also be examined to reveal the

role of sputtered thin films in device construction.

1.3 Sputtering materials for integrated circuits1.3.1 IntroductionFollowing the invention of the point contact bipolar transistor in 1947 by Bardeen, Brattain and

Shockley at Bell Laboratories, there has been remarkable growth of the semiconductor industry.

Photovoltaic multilayers

Compound oxides/nitrides/carbides

Simple oxides/nitrides/carbides

Alloy interfaces/heterostructures

Alloys/compoundsemiconductors/

organic molecules

Metals/semiconductors

0.1 1.0 10Length scale (nm)

Mat

eria

ls c

ompl

exity

100

Copper interconnects

Tantalum interconnectdiffusion barrier layers

GMR multilayersand spin valves

Magneticparticles

Qua

ntum

dot

dev

ices

Mol

ecul

ar e

lect

roni

cs

Gateoxides

Ultr

ahar

d m

ultil

ayer

s(C

u/C

r, A

I/AI 2

O3

lam

inat

es)

Tan, Tin inter connectdiffusion barrier layers

Magnetictunnellingjunction(MTJ)

devices

Thermal, environmentalbarriers and hard coatings,

high Tc superconducting thinfilms, ferroelectric metal

oxides

FIGURE 1.8

Vapor deposited materials systems and their length scale as used in various devices [26].

131.3 Sputtering materials for integrated circuits

The integrated circuit (IC) was invented in 1958 by Jack Kilby of Texas Instruments and Robert

Noyce of Fairchild Semiconductors, and the bipolar transistor technology was applied to make IC

memory for manufacturing computers in the 1960s. Figure 1.10 shows the first bipolar transistor

and the IC [28,29]. Bipolar transistors were used at the individual circuit level for speed, yet

FIGURE 1.9

Schematic illustration of a chip cross-section that has five levels of metallization [27]. Note that sputtering is

used for FEOL, BEOL and UBM.


because of the large power dissipation bipolar transistors had a limit of about 104 per chip. In 1960

the first metal oxide semiconductor field effect transistor (MOSFET) on a silicon substrate with

SiO2 gate insulator was fabricated. MOSFET devices were slow compared to the bipolar devices,

but MOSFET was easier to fabricate and had higher lay-out density. Both bipolar and single polar-

ity MOSFET suffered from high standby power dissipation and this restricted their use in large

integration on chips.

A major breakthrough occurred in 1963 when the CMOS was invented. Table 1.6 lists the

timeline for various inventions in the area of semiconductors. A CMOS circuit consists of an

n-channel MOSFET and a p-channel MOSFET, which are connected in series between power

supply terminals (Figure 1.11). Both types of MOSFETs are made of source�drain region, poly-

silicon gate with a refractory metal silicide and these MOSFETs are separated by oxide shallow

trench isolation (STI). One of the major characteristics of a CMOS transistor is its negligible

standby power dissipation. Only during switching, power is dissipated and now it is possible to

integrate hundreds of millions of CMOS transistors in a single chip and effectively air cool.

From the 1960s to the present CMOS gate length has dramatically shrunk from 100 μm to

35 nm driven by the competitive drive for improved performance and cost reduction.

The most common description of the scaling in CMOS devices is known as Moore’s law.

The observation of Gordon Moore in 1965 was that the number of components in an IC chip

would double each year for the following 10 years. In 1975, Moore noted that his prediction

made in 1965 had come true and he predicted that, in the future, the number of components per

chip would require nearly 2 years rather than one year to double. In the last 35 years, his predic-

tion has been realized from improvement in lithography and an increase in chip size due to

more creative techniques for forming components as Moore pointed out. As per the forecast,

CMOS gate length is expected to reach to less than 11 nm by about 2020. Figure 1.12 shows

device scaling data for Intel logic chips [30]. In addition to the reduction in device size, an

(a) (b)

FIGURE 1.10

(a) First transistor made in 1947 at Bell Labs [28]. and (b) first IC manufactured in 1966 at Motorola [29].


increase in overall chip size, reduction in operating voltage and increase in the functionality

continues to grow.

Pitch is defined as interconnection line-width plus spacing between two successive intercon-

nects at the same level. In the CMOS devices scaling literature, it is practice to define scaling

of interconnect using pitch of the metal layer starting from the M1 level, which is identified as

local interconnect (Figure 1.13) (p. 18) [31]. As shown in the figure, pitch values increase at

intermediate interconnect and global interconnect levels. The M0 level is typically a silicide

FIGURE 1.11

Schematic illustrations of n-channel and p-channel MOSFET. STI stands for shallow trench isolation.

Table 1.6 Major Inventions in Semiconductor Industry

Year Invention

1947 Bipolar transistor by John Bardeen, Walter Brattain and William Shockley at BellLaboratories, USA

1958 Integrated circuit by Jack Kilby (Texas Instruments) and Robert Noyce (FairchildSemiconductor)

1960 MOSFET

1963 CMOS

1968 One-transistor DRAM cell

1971 Microprocessor by Ted Hoff of Intel

1974 The Altair, first desktop computer for personal use

1980 �Present

VLSI and ULSI era


contact. With shrinking transistor size, contact resistance increases because of its inverse rela-

tion to the contact area. The method of reducing contact resistance using a low resistivity sili-

cide and its historical evolution is given in the next section. Figure 1.14 (p. 19) shows examples

of interconnect pitch used in an Intel made IC that has eight levels of interconnects [32]. The

first three levels have identical interconnect pitch values and then it increases with higher levels

of interconnect. Interconnect pitches are required to be scaled with every technology node/gen-

eration to keep pace with interconnect performance and density requirements. In order to deal

with the high interconnect density requirement, scaling of metal pitches can be done less

aggressively by adding more interconnect layers and increasing the interconnect aspect ratio

(23 thickness/pitch). Figure 1.15 (p. 19) shows how historically metal pitch has decreased and

number of metal layers has been added to accommodate device scaling [33]. It is to be noted

that pitch scaling of 0.73 per technology generation has been driven by roughly 0.73 gate

delay improvement per technology generation. In the semiconductor literature average pitch is

also used, which is the sum of the minimum pitch used for each layer of interface divided by

the number of interconnect layers.

In 1994, a workshop was organized by the Semiconductor Industry Association (SIA) in

Boulder, Colorado to produce a roadmap for the semiconductor industry. The National Technology

Roadmap for Semiconductors (NTRS) was the outcome of this effort. Since 1998, the International

Technology Roadmap for Semiconductors (ITRS) report has been the benchmark for scaling

devices in terms of technology node/generation. Each edition of the ITRS roadmap projects future

device scaling trends for the next 15 years.

FIGURE 1.12

Illustration of device scaling from 130 nm to 22 nm node in Intel logic chips [30].


Table 1.7 (p. 20) shows selected technology characteristics from the 2005 ITRS roadmap [34].

It is important to remember that the concept of technology node was straightforward when it repre-

sented the tightest metal pitch of dynamic random access memory (DRAM). In an era where a great

variety of products are serving as technology drivers, it will be misleading to continue with a single

driver such as DRAM. Hence, as of 2005 ITRS no longer uses the term technology node and

instead each distinct scaling feature is referred to as such. Though DRAM M1 half-pitch is shown

at the top of the table, it is no longer described as the measure of technology node anymore.

DRAM M1 half-pitch is one of several indicators of device scaling. But the node terminology will

continue to be used loosely by others. Note that ITRS uses half-pitch length for predicting technol-

ogy generation and also the time between nodes is not a constant time interval. The time interval

was 2 years for 250, 180 and 130 nm nodes, but it is 3 years for the remaining nodes.

Figure 1.16 (p. 21) shows projected scaling results from both the 1997 NTRS and 2004 ITRS

reports [35]. Note various device parameters in terms of technology generation and the year. The

upper-most curve labeled LTN represents the major technology generation and identified as half-pitch

of densely packed DRAM. Other critical dimensions include LL (printed gate length) and Lp (physical

gate length) after etching of the gate metal contact) for logic devices. Both 20 nm and 10 nm planar

devices have been demonstrated [36,37]. Figure 1.17 (p. 22) shows a chip manufacturing flow chart

and unit processes involved in wafer fabrication [38]. Wafer fabrication takes about 2�3 months and

Passivation

Dielectric

Dielectric capping layer

Pre-metal dielectricTungsten contact plug

Metal 1 pitch

Metal 1

Intermediate

Global

Wire

Via

Copper conductor withbarrier/nucleation layer

Etch stop layer

FIGURE 1.13

Schematic representation of local, intermediate and global interconnections [31].


FIGURE 1.14

Examples of interconnect pitch as used in an Intel chip [32].

FIGURE 1.15

Trend of metal pitch with device scaling. Note 0.7 times decrease in pitch every 2 years [33].


may involve more than 450 processing steps in a wafer fab. In the semiconductor industry, there are

certain terminologies that are used for chip makers. These are foundries, captive chip makers and

fabless companies. Foundries make chips only for other companies, while captive chip makers pro-

duce chips for their own products. Fabless companies design chips for a particular market and another

chip maker fabricates them. This kind of arrangement reduces the cost of chip making because a fab

for wafer fabrication may cost between $3 billion and $6 billion. Figure 1.18 (p. 23) shows an exam-

ple of the fab layout with various unit processes [39].

1.3.2 Silicide contactHistorically, various silicides have been used in CMOS devices to avoid increase in the resistiv-

ity due to scaling of the polysilicon line width in the gate and contact in source/drain regions

[40�48]. While Figure 1.19(a) (p. 24) illustrates the evolution of silicide contacts for CMOS

devices, Figure 1.19(b) shows the transmission electron microscopy images of various silicide

contact structures in actual scaled transistors [42]. A contact is a low resistance connection

between the active region and metal interconnect in a CMOS device. Contacts can be rectifying

(Schottky) or Ohmic in nature. The other requirements for silicides are thermal stability, oxida-

tion properties, chemical reactivity and diffusivity in silicon. Contacts are M0 level intercon-

nects and termed local interconnects. Figure 1.20 (p. 25) shows two types of silicides formed in

CMOS devices, i.e., polycides and salicides [43]. Polycides refer to refractory metal silicides

formed (e.g., WSi2, MoSi2, TaSi2) on polysilicon gate and salicides (e.g., TiSi2, CoSi2, NiSi2)

refer to self-aligned silicide formed on gate and source/drain regions of the device. Figure 1.21

(p. 26) shows polycide and salicide processes.

Note that in polycide process, a silicide with required stoichiometric composition is deposited

on the polysilicon gate before it is patterned (Figure 1.21(a)). Then an insulator material layer is

deposited to form the gate stack. Subsequently, an annealing treatment is required to convert amor-

phous polycide film to the crystalline low resistivity phase. After forming the side-wall spacers, a

silicide process is sometime used to form silicide contacts on source/drain regions. The earlier use

of refractory metal polycides successfully withstood the high temperature processing step in front-

end processing of CMOS devices. The resistivity of these refractory metal silicides being high

Table 1.7 Selected Technology Characteristics from 2005 ITRS Report [34]

Year 2005 2007 2010 2013 2016 2019

MPU (Microprocessor unit) 1/2 pitch 90 68 45 32 22 16

MPU patterned gate length (nm) 54 48 30 21 15 11

DRAM 1/2 pitch (nm) 80 65 45 32 22 16

MPU: frequency of on-chip clock for highperformance (MHz)

5204 9285 15,079 22,980 39,683 62,443

High volume MPU (cost performance) Mtransistors/cm2

174 276 552 1104 2209 4417

DRAM memory chip size at production (mm2) 88 110 93 93 93 93

DRAM memory chip Gbits/cm2 1.22 1.94 4.62 9.23 18.46 36.93


(30�100 μΩcm), thick layers of silicides were required to meet low gate resistance with device

scaling. Polycide structures became less attractive because of the high series resistance in the

source/drain region driven by the two edges of the gate and also process-related issues. Arrival of

the salicides made it possible to simultaneously form silicide layers both on the gate and source-

drain regions and reduce the series resistance in the source/drain region by reducing the width of

the oxide spacers on both sides of the gate.

FIGURE 1.16

(a) Dimensions of several important metal oxide semiconductor device parameters, and (b) their projection

for scaled devices [35].


As shown in Figure 1.21(b), in a salicide process the polysilicon gate is patterned and the side-

wall spacers are formed prior to the deposition of metal film using sputtering. The deposited metal

layer is then reacted with exposed silicon regions in the gate and source/drain areas using rapid

thermal processing (RTP) to form the silicide layer. Salicides have lower resistivity

(13�20 μΩcm) than the polycides. In case of titanium and cobalt, two-step annealing is conducted.

The first annealing temperature for titanium varies between 650�C to 700�C, which form the high

resistivity C49 TiSi2 phase. This is between 400�C and 600�C for cobalt, which forms Co2Si and

CoSi. It is important to note that low annealing temperature is required to avoid silicide bridging

across the oxide spacers (Figure 1.22) (p. 27) that may cause electrical short between the gate and

source/drain [43]. The second annealing temperature for titanium to obtain low resistivity C54

TiSi2 is above 850�C. The annealing temperature for CoSi2 to form is above 700�C. To form low

resistivity nickel silicide (NiSi), one annealing between 400�C and 550�C is required. Figure 1.23

shows a NiSi silicide MOSFET structure [48]. Table 1.8 (p. 28) lists processing temperature and

properties of various silicides. Silicides processing for titanium, cobalt and nickel are discussed in

Chapters 5 and 7 in more detail.

Waferpreparation

1.

3.

4.

5.

Electricaltesting/die

sorting

Diffusion

(Back-end processing)

Thin filmdeposition

Polishing

2. Wafer fabrication (Front-end processing)

Photolithography Etching

Ionimplantation

Assembly &packaging-UBM etc.

Final test

FIGURE 1.17

A representative chip manufacturing flow chart showing unit processes. This flow chart is based on Ref. [38].

Assembly and packaging (4) requires some of the same unit processes as wafer fabrication (2). This includes

sputtering of thin films (represented by shaded boxes).


1.3.3 Conductor, liner, barrier and anti-reflection coatingCMOS transistor performance has been achieved primarily by reducing the size of transistor geom-

etries and in particular gate length. This necessitated an increase in interconnect density to accom-

modate increased transistor density over a large chip. This was achieved by reducing line width of

global interconnect as well as adding more levels of interconnects. This leads to increases in line

resistance (R) and greater parasitic capacitance (C) because of the reduced spacing between inter-

connect lines. As a result, it increases interconnect RC delay that slows down the chip speed and

also lowers the chip performance. This means transistor scaling reduces gate delay and increases

interconnect RC delay. RC delay is given by

RC � ρl2

tm

� �Metal

xεtILD

� �Diel

(1.3)

Here ρ, l and tM are the resistivity, length and thickness of the metal interconnect, and ε and

tILD are the permittivity and thickness of the inter-level dielectric (ILD). In the literature dielectric

constant k is used, which is the ratio of ε and εo. εo is the permittivity of the free space.

Figure 1.24 (p. 28) shows that while intrinsic gate delay is reduced because of the transistor scaling,

interconnect RC delay increases sharply [49]. One of the ways to reduce RC delay is to divide long

interconnects into shorter segments and use repeaters between consecutive segments. However, a

disadvantage of this approach is increased power consumption, chip area and design cost.

Thin film deposition

Photo Photo EtchInspect

Waf

er c

lean

ing

Waf

er tr

acks

Wet

che

mic

al p

roce

ssin

g

Ion

impl

ant

FIGURE 1.18

An example of fab layout [39]. Various unit processes have been labeled to illustrate their locations inside

the fab.


Alternatively, lower IC operating temperature can increase switching speed. This adds complexity

and cost of chip design for faster cooling of the chip. Therefore, the technological solution for RC

delay opted for replacing the existing conductor and insulator with lower resistivity and lower

dielectric constant, respectively.

In addition to RC delay, the other important issue in interconnect is reliability, which revolves

around the capacity of interconnect to carry high current density without causing failure. Since sup-

ply voltage is not scaled down as aggressively as interconnect dimensions, interconnect lines at

high current density should not develop atomic diffusion assisted stresses that can cause voids (e.g.,

stress migration) or hillock formation in the interconnect line (e.g., electromigration). While void

causes open circuit failure, hillock protrudes through the encapsulating ILD lead to short circuit

failure with adjacent interconnects at different levels. Figure 1.25 (p. 29) shows via failure because

of voiding [50]. In Chapters 2 and 5 this subject is discussed in greater detail.

The important issue is the increased interconnect capacitance, also known as capacitive para-

sitic, with reduced size of interconnect geometries. This limits the IC performance by exacerbating

dynamic power dissipation and increasing cross-talk. As device density and operating frequency

increases, the density of power generated on the chip also increases. This can result in temperature

escalation from normal operating temperatures of 85�C to 120�C due to the device and interconnect

1990Year

Lg (μm)2.0 1.0 0.1 0.02

2000 2010

100(a)

(b)

10

ρ s (

Ω/s

q.)

PolycidePolycide MoSi2

WSi2

NiSiTiSi2 CoSi2

N+ poly-Si

Polycide

Salicide

Salicide1

TiSi2

180 nm 70 nm 50 nm

CoSi2

NiSi

FIGURE 1.19

(a) Progress of silicide materials [42]. and (b) transmission electron micrographs of salicide structures [49].


heating. This imposes additional demand of dissipating heat away from the chip in order to prevent

further temperature rise. On-chip power dissipation involves both static and dynamic components.

While static power dissipation is due to junction leakage in the transistor, dynamic power dissipa-

tion occurs during the switching transients. Lower-k ILDs reduce dynamic power dissipation.

Another undesirable issue of interconnect scaling is the cross-talk noise among interconnects of

minimum spacing. The smaller the spacing between interconnects, the larger the cross-talk peak

voltage. Hence, supply voltage cannot be lowered aggressively in order to keep adequate noise mar-

gin. Changing the aspect ratio (2 x thickness/pitch) of interconnect lines and spacing can help, but

in order to reduce RC delay and cross-talk for the scaling approach to be effective, a lower resistiv-

ity and higher reliability metal and insertion of low-k dielectric are required (Table 1.9) (p. 29).

Earlier interconnects consisted of aluminum alloy conductors isolated by SiO2 k5 3:5� 4:5ð Þ. Thissubject has been discussed in detail elsewhere [51,52].

The introduction of copper (ρB1.8 μΩcm) interconnect against aluminum alloys (ρB3.3 μΩcmfor Al-0.5Cu) enabled aggressive device scaling. For a fixed resistance per unit length, copper is a

better choice than aluminum alloys because thinner copper interconnect can be used. In addition,

improved electromigration resistance of copper (see Chapter 5) also allows higher current density

than its aluminum alloy counterpart. Subsequently the introduction of low-k dielectrics reduced the

side-wall capacitance and provided a large window for optimization of RC delay, power and cross-

talk as a function of interconnect thickness and spacing. Although aluminum/low-k dielectric

worked well, better device performance was achieved when copper/low-k dielectric were used

(Figure 1.26) (p. 30) [53]. In 1997, IBM and Motorola first declared their intention to use copper

FIGURE 1.20

Cross-section of two MOSFETs with (a) polycide and (b) salicide structures [43]. Drawing not in scale. The

actual dimensions for the device in (b) are much smaller than those for the device in (a).


with oxide (SiO2) dielectric in the CMOS logic chip. In the case of aluminum/low-k dielectric,

coating of interconnects with liner materials such as TiN markedly increase the lifetime of alumi-

num alloy interconnects.

Figure 1.27 (p. 30) shows an advanced CMOS structure in which cobalt, Ti, TiN and AlCu alloy

have been deposited using sputtering [54]. TiN is deposited using reactive magnetron sputtering

(with N2), while aluminum alloy interconnects are deposited using magnetron sputtering. It is

Amorphous silicide(high Rs)

Insulating cap

(a)

(i)

(ii)

(iii)

(i)

(ii)

(iii)

(b)

Polysilicon gate

Gate oxideP

P

P

P

P

P

n+

n+ n+

n+n+

n+ n+

n+ n+

n+

SiO2

SiO2

SiO2

SiO2

SiO2

SiO2

Sidewall spacer

Silicide

Sidewall spacerPolysilicon gate

Metal

HeatGate oxide

SilicideMetal/metal nitride

Silicide

Selective etching + heat

SilicideSilicide

Silicide

Heat

Crystalline silicide(low Rs)

FIGURE 1.21

Steps used in (a) polycide and (b) salicide processes.


copper that has a superior combination of electrical property, resistance to electromigration and

ease of depositing in deep submicron interconnects. Similar to aluminum alloy interconnect with

TiN/Ti stack, copper interconnect is also coated with a barrier, TaN/Ta stack [55,56]. The dama-

scene process is the most common method of forming the copper interconnects in scaled devices.

In Chapter 5 this subject is discussed in greater detail.

Table 1.10 (p. 31) lists various applications and corresponding Applied Materials sputter tools

used for silicide contact formation, liner and barrier deposition, advanced barrier and seed deposition,

interconnect formation, etc. Note that while this book was being prepared, the EnCoRetII RFX

sputtering tool for barrier/copper seed application aiming at 32 nm and 22 nm technology generations

FIGURE 1.22

Schematic illustration showing major process induced reliability issues with salicides structures [43].

FIGURE 1.23

Cross-section TEM image showing NiSi at sub 50 nm poly gate [48].


was released. It has improved magnetron motion capability and re-sputtering facility to provide

highly conformal films.

With continued device scaling and innovation in gate architecture, the demand for new materi-

als has been realized. A good deal of work in this area indicates that there will be no significant

device architecture change up to 22 nm technology generation. Three dimension gates (e.g., triple

gate MOSFET such as FinFET) may be incorporated in commercial manufacturing at or below

15 nm technology generation [57�59]. With regard to sputtered thin films, TaN barrier and copper

seed will remain the choice for most chip manufacturers up to 32 nm technology generation. At or

Table 1.8 Processing Temperature and Properties of Silicides

Silicide Resistivity(μΩcm)

FormationTemperature (°C)

nm of Silicide/nm of metal

Melting Point (°C)

Polycide WSi2 30�70 1000 2.58 2165

MoSi2 40�100 800�1000 2.59 1980

TaSi2 35�55 800�1000 2.41 2200

Salicide TiSi2�C49 60�70 500�700 2.51 �TiSi2�C54 13�16 700�900 3.52 1500

CoSi 100�150 400�600 2.02 �CoSi2 14�20 600�800 3.64 1325

NiSi2 40�50 600�800 3.65 �NiSi 14�20 400�600 2.34 992

FIGURE 1.24

Intrinsic gate and interconnect delays as a function of minimum feature size [49].


below 15 nm, ruthenium and ruthenium�tantalum alloys have the potential to be used as barrier

material perhaps with TaN. One of the chemical vapor deposition or atomic layer deposition

methods may soon become a mature technology for depositing ruthenium-based barriers.

Ruthenium�tantalum alloy sputtering targets have also been used to deposit such barrier layers.

Copper-manganese alloys have been found to form barrier layers as a result of reactions with

silicon, known as self-forming barriers, SFB, and attempts have been made to deposit barrier-

forming layers both by sputtering and chemical vapor deposition (see Chapter 5). To improve

electromigration resistance of copper for smaller technology generations, copper�aluminum and

copper�magnesium alloys have also been studied.

FIGURE 1.25

Electron micrograph showing via failure because of voiding [50].

Table 1.9 Metals and Dielectric Materials and their Properties

Interconnect MaterialsOptions

DielectricConstant

DepositionMethod

Al�SiO2 3.5�4.5 CVD

Al�low k 2.0 CVD

Cu�SiO2 (fluorinated) 3.5 CVD

Cu�low k 2.0 Spin-on

Low k: Silsesquioxane, polymide, xerogel, parylene, so on; CVD: Chemical vapordeposition.


FIGURE 1.26

Clock time as a function of metal layer thickness for various interconnect materials options [53].

FIGURE 1.27

Cross-section of a representative CMOS structure after M1 level interconnect deposition [54].


1.3.4 Assembly and packaging (back-end processes)Chips that pass wafer sort test, also called dies, undergo assembly and packaging [60]. In the

assembly, good dies are separated from the wafer and attached to the substrate. Assembly involves

back grinding (reducing wafer thickness), die separation (cutting die from wafer), die attach (attach-

ing die to the substrate) and wire bonding (attaching small diameter wires between die bonding

pads at the terminal of the substrate). In the packaging, dies are encapsulated in a protective pack-

age. Packaging usually serves four purposes, i.e., (a) provide electrical contact to and from the

chip, (b) pass on functionality from dense surface of a chip to the relatively less dense external cir-

cuitry, (c) provide environmental isolation to the chip and also (d) take away heat from the device.

The role of packaging has become more important as transistor scaling, complexity, functionally

and performance requirements have increased with each generation of technology. In other words,

increase in chip size, the transistor density and power dissipation have put forward new challenges

to packaging technology. As materials (conductor/inter-layer dielectric) in wafer level interconnect

changed from historic Al/SiO2 to Cu/low-k, packaging solutions involving chip-level interconnect

had to address more complex problems. Many of the inter layer dielectrics have low mechanical

strength and low thermal conductivity compared to SiO2. Because of the embedded layer of ultra-

fine interconnect metals in low-k inter-layer dielectric, interconnect structures can support little

strain and pose significant reliability risk. Figure 1.28 shows low temperature warping of an

Table 1.10 Standard Processes and Applied Materials Sputtering Tools for

Various Applications [25]

Application Chamber

Front end metallization Standard Co

Standard Ni

ALPS Co

PVD Clean W

Liner/Barrier IMP Ti

Barrier/Cu Seed SIP EnCoRe Ta(N)

SIP EnCoRe Cu

Al interconnect Hot Al

ALPS Al

SIP TTN

Al

Durasource TTN

Back end metallization (UBM/Bondpad) Standard PVD Cu

Standard PVD Ta(N)

Standard PVD Ti

Standard PVD Cu-Cr

Standard PVD AL

NiV


assembly involving flexing of chip/laminate ball grid array (BGA) on printed wiring board (PWB)

[61]. Therefore, reduction of strain in packaging solution requires minimum stress on the chip dur-

ing thermal cycling. Similar to transistor technology generation, packaging technology generation

is also captured in ITRS roadmaps [62].

1.3.4.1 Under bump metallization (UBM) and bond padThe flipchip process, also known as the C4 process after IBM’s Controlled Collapse Chip

Connection, has emerged as the best method to manufacture systems in package applications. In flip-

chip technology chips are turned upside down and bonded directly to substrate. This is done by using

solder bumps on the chip and a bonding material on the substrate (Figure 1.29) [63]. Typically, a

metallization scheme, know as under bump metallization (UBM), is used between the solder bump

and the chip. UBM selection is made based on the operating condition of the chip, current carrying

FIGURE 1.28

The flexing of chip/laminate ball-grid array (BGA) on printed wiring board (PWB) [61].

FIGURE 1.29

(a) Schematic illustration of a flipchip interconnect system [63].


requirement and also the overall back-end process requirements. As shown, UBM is the interface

between the chip metal pad and the solder bump. UBM layers are deposited to achieve a highly reli-

able electrical and mechanical interface between chip circuitry and the solder bump.

Figure 1.30(a) shows a cross-section of a representative UBM and materials used to construct

the UBM [25]. UBM usually consists of an adhesion layer covering the chip metallization, a bar-

rier layer, a wetting layer and an anti-oxidation barrier layer facing the solder bump. The common

adhesion layers are chromium, titanium, nickel, tungsten, tungsten�titanium, zincate, etc. The bar-

rier layer prevents diffusion of metal species and ionic contaminants into the chip metallization and

adhesion layer. Materials used in the barrier layer are chromium, chromium-copper alloy, titanium,

nickel, tungsten and tungsten-titanium. The wetting layer provides a consumable layer for the sub-

sequent solder bump metallization, and the anti-oxidation barrier layer is optional. Typically, cop-

per or nickel (or NiV) is used as the wetting layer, while a thin gold layer (100�200 nm) is usually

used as the anti-oxidation barrier layer because gold does not embrittle the UBM bump interface

due to the formation of intermetallics. Many of the thin UBM layers are sputter deposited, but thick

metallic layers and solder bumps can be deposited using electroplating. If solder bumps are depos-

ited by electroplating on top of the nickel, the gold layer is not required. In the case of solder

bumping, the wetting layer can be deposited by sputtering or by a combination of sputtering and

electroplating on the titanium or titanium�tungsten layer.

Table 1.11 (p. 35) lists some of the common UBM studied for flipchip applications [64]. The space

around the bumps is filled with epoxy, known as under-fill, to improve reliability. Silica-filled anhy-

dride resin polymer is one of the popular under-fill materials. Figure 1.30(b) shows gold-wire bonding

of the chip to the substrate and representative metallization layers [25]. For example, sputtering is used

for depositing metallization layers such as Al and TaN. Table 1.12 (p. 36) shows the ITRS Roadmap of

UBM metallization [62]. Figure 1.31 (p. 36) shows an illustration of the Clusterline 300 tool by Unaxis

that has sputtering chambers for UBM metallization [65]. For convenience, Table 1.13 (p. 37). lists

OEMs and their sputtering tools used for various chip-making applications [66].

1.3.4.2 Through-silicon-via (TSV)The driving force for miniaturization and high performance of devices is also the force for technol-

ogy innovation in the area of 3D integration of devices with higher density and performance

[67�69]. Figure 1.32 (p. 38) shows the evolution of chip-level and wafer-level bonding technology

with reduced vertical interconnect minimum pitch [70]. Increased demand for more attractive ways

to stack chips in 3D has opened up a new area known as through-silicon-via (TSV) [68,69]. TSV is

regarded as an evolution of 3D packaging, in which wafers or the chips are stacked on top of each

other and are connected using vertical conducting column (via). The chips can be of the same type

or of different types, referred to as homogenous or heterogeneous integration, respectively. TSV is

aimed at providing the shorter possible interconnection length and as a result reduced parasitic loss

and time delay during signal propagation. For optical application, TSV is aimed at providing elec-

trical and optical connections from different sides of the silicon and improve sensor performance.

Therefore, TSV technology will provide different advantages to different market segments, and

TSV manufacturing requirements will be application dependent.

It is believed that technology challenges of producing vias have more or less been solved. Deep

reactive ion etching (e.g., the Bosch process) has been found to be more efficient than laser drilling

of wafers to form deep vias. The other critical operations for forming TSVs include bonding of


FIGURE 1.30

Example of use of sputtered films in (a) under bump metallization (UBM) and (b) gold wire bonding [25].


Table 1.11 Examples of UBM Schemes Studied for Flip-Chip Applications [64].

Cr/Au Cr/Cu/Au TiW/Ni/Au Cr/Cu/Ni/Au TiW/Au

Thickness Cr: 200�300AAu: 50�300 μin

Cr: 200�300ACu: 500�2000 μinAu: 20�100 μin

TiW: 200�300ANi: 1000�2500 AAu: 50�300 μin

Cr: 200�300ACu: 50�2000 μinNi: 35�75 μinAu: 20�100 μin

TiW: 200�300AAu: 20�300 μin

Application Low temperature Low temp where PbSnsolder is required

Medium temp,good solderability

Medium temp,good solderability

High temp AuGeeutectic bonding

Temperaturelimit

300�C, 1 h 280�C, up to 30 min 325�C, 1h 250�C, 1 h 425�C, 1 h

Solderability(PbSn)

Poor Good Good Good Poor

Advantage Good electrical conductivity Excellent electricalconductivity,solderability to PbSnand AuSn, non-magnetic

Good electricalconductivity,solderability toPbSn and AuSn

Excellent electricalconductivity,solderability toPbSn and AuSn

Good electricalconductivity, AuGeeutectic bonding

Disadvantage Not suitable for PbSn or AuSnsoldering, Cr diffusion at AuGe,eutectic bonding temp, lowprocessing temp

Cu diffusion at AuGe,eutectic bonding temp,low processing temp

Ni diffusion atAuGe, eutecticbonding temp

Ni diffusion atAuGe, eutecticbonding temp

Not suitable forPbSn or AuSnsoldering

wafer to a carrier (glass or dummy silicon), thinning of wafer, wafer processing on bonded/thinned

wafers and subsequent debonding. Areas that are being studied now are thermal management to

counter heat generation, maintaining adhesion between the wafer and carrier, automatic testing

capability of TSVs and lower processing temperature below 200�C. The real challenge is to make

TSV cost effective. The major cost barrier to TSV lies in bonding/de-bonding and via barrier/fill.

Table 1.12 ITRS Projection of UBM Metal Layers [62]

UBM metallurgy 2010 2011 2012 2013 2014

Memory CuNi CuNi CuNi CuNi CuNi

TiCuNi TiCuNi TiCuNi TiCuNi TiCuNi

TiCu TiCu TiCu TiCu TiCu

Al/NiV/Cu Al/NiV/Cu Al/NiV/Cu Al/NiV/Cu Al/NiV/Cu

Ti/NiV/Cu Ti/NiV/Cu Ti/NiV/Cu Ti/NiV/Cu Ti/NiV/Cu

TiW/Cu TiW/Cu TiW/Cu TiW/Cu TiW/Cu

Cr�Cu Cr�Cu Cr�Cu Cr�Cu Cr�Cu

Standard Logic and Analog TiCuNi TiCuNi TiCuNi TiCuNi TiCuNi

TiCu TiCu TiCu TiCu TiCu

Al/NiV/Cu Al/NiV/Cu Al/NiV/Cu Al/NiV/Cu Al/NiV/Cu

Ti/NiV/Cu Ti/NiV/Cu Ti/NiV/Cu Ti/NiV/Cu Ti/NiV/Cu

TiW/Cu TiW/Cu TiW/Cu TiW/Cu TiW/Cu

Cr�Cu Cr�Cu Cr�Cu Cr�Cu Cr�Cu

FIGURE 1.31

Image shows Unaxis’ Clusterline 300 sputtering tool used for UBM [65].


Table 1.13 OEMs, Deposition Tools and the Sputtering Materials as used in Chip Making

OEMs Deposition Tool Sputtering Materials Used

AppliedMaterials

Enduras standard chamber Al and Al alloys, Cu, W/Ti, Co, Ti

Enduras G-12 Ti, Cr, Cu, Ta, W/Ti, W

SIP Ti, Cu, Ta, W

SIP EnCoRet II Cu, and Ta

ALPS (Advanced Low-Pressure Source) Al and Al alloys, Co and Ni alloys

Enduras other materials Cr, Mo, Cu, Ni and Co alloys, Ta, Ti, silicidesW, W/Ti, Ni, precious metals (Au, Pt)

Novellus HCM (200 mm, 300 mm) Ta, and Cu

INOVAs flat targets Al and Al alloys, Ti, Co, W

Varian/Novellus

Al and Al alloys, Ni alloys, doped Si, Ta, Ti,W/Ti, silicides

Conmag I and II Al and Al alloys, Ti, W/Ti

Quantum, Mini-Quantum Al and Al alloys, Ti

Anelva 1021, 1060, C7100, 1201,1051, 1080 Al and Al alloys, Ta, Cu, Ti, Co, Ni, C, W/Ti

ULVAC Ceraus ZX-100 Al and Al alloys, W

Oerlikon CLUSTERLINE 200 II & CLUSTERLINE 300 Al and Al alloys

Balzers/Unaxis

SWS 605, SWS-606, rectangular, AK515,AK517, AK618, AK525, AK530, AK535,ARQ300, ARQ151

Al and Al alloys, Cu, Cr, Ta, Mo, Ti, W, W/Ti,Ni, NiV, CrCu, NiPt, CrSiO, precious metals(Au, Pt)

MRC Eclipse Al & Al alloys, Cu, CuCr, Doped Ge, NiAlloys, Silicides, W/Ti, precious metals (Au,Pt)

11" Screw Eclipse Al and Al alloys

8" Eclipse Al and Al alloys, W/Ti, Ti

11" Superstep Al and Al alloys

RMA 10 and RMA 12 Precious metals (Au, Pt), Ta/Al

SPA 10 and SPA 12 Single-piece Al and Al alloys

RMX 10 and RMX 12 Ti, Ni, Ta, W/Ti, precious metals (Au, Pt)

Aviza/Trikon

8.875" round for Electrotech Al and Al alloys, Cr, Mo, Ta, W/Ti, Ta, NiV, Ti,precious metals (Au, Pt)

Sigmas fxPt Al & Al alloys, Ni, Ti, precious metals (Au, Pt)

KDF Planar Ti, Cr, Mo, NiV, W, TiW

Magnetic materials Ni and Co alloys

Enhanced Precious metals (Au, Pt)

Chi targets 4 pc or 1 pc Al and Al alloys, Cu, and Ag

Muset Al and Al alloys

Mu 4 piece Cr, Ta, Ti, NiV, Mo, W/Ti

IOTA Upsilon 4 pc or 1 pc Precious metals (Au, Pt)

Veeco Cymetra Al and Al alloys, Ta, W/Ti, Al2O3, preciousmetals (Au, Pt)

(Endura, SIP EnCoRe, and SIP EnCoRe II are trademarks of Applied Materials, Inc [66]. CLUSTERLINE 200 II andCLUSTERLINE 300 are trademarks of Oerlikon Systems. INOVA is a trademark of Novellus Systems, Inc.)


Figure 1.33 shows three basic schemes of TSVs (via-first, via-middle and via-last; from left to

right) [62]. We will consider via-first and via-last because of their importance. In the via-first

approach, vias are typically created using deep reactive ion etching before back-end-of-line

(BEOL) metallization, i.e., during front-end-of-line (FEOL) metallization. Via diameter usually var-

ies between 5 and 10 μm and the aspect ratio can be as high as 10:1. This process allows formation

of smooth and straight side-wall vias of the order of 700 μm in depth in thick wafers. These pose

challenges with respect to the liner and barrier step coverage and also the quality of copper fill. In

the via-last approach, vias are created after BEOL from the front side of a thick wafer or backside

of a thinned wafer [68]. The via-last approach has already been used in CMOS image sensors and

stacked DRAM. In order to thin down a wafer, usually the wafer is temporarily bonded to a carrier

for easy handling. In the via-last approach, usually the via diameter will be wider (20�50 μm) and

the aspect ratio can be 2:1 to 15:1. It is important to note that the packaging industry usually has

access to low-tech PVD tools for deposition barrier/seed layers and is usually not capable of

depositing vias beyond an aspect ratio of 3:1 to 5:1. As a result, for deep vias (e.g., 200�300 μm)

in thick wafers, the via diameter has to be large enough to have a low aspect ratio. Therefore, for

high aspect ratio TSV with low via diameter an investment for advanced PVD tools or technology

development for seed layer enhancement by electroplating companies is required.

Because TSVs are metal connections embedded in silicon wafer, a liner is required between

the wafer and via metal. The function of this layer is to electrically isolate the TSVs from the

substrate and each other. A barrier layer is also used between the liner and the TSV metal.

Major OEMs have already developed CVD processes for depositing conformal liner layers for

high aspect ratio vias for via-first and via-middle TSVs. These dielectrics have good adhesion to

FIGURE 1.32

Evolution of 3D packaging leading to use of through silicon via (TSV) technology [70].


barrier layers (Ti, Ta, TaN/Ta) deposited using sputtering. Both Ti and Ta are being used for

forming barrier layer for copper TSVs. Although other TSV fills such as polysilicon and tung-

sten have been studied in the via-first approach, copper TSV is the most popular approach today.

Applied Materials has developed its Extensat PVD tool for TSV application. Figure 1.34 shows

an example of TSVs in four die stack test vehicles [71]. It shows 50 μm thick die and 10 μmdiameter TSVs.

1.4 Sputtering materials for liquid crystal displays1.4.1 IntroductionThough discovery of liquid crystal took place in the late 19th century and the concept of the thin

film transistor (TFT) was proposed in 1935, the development of liquid crystal display (LCD) actu-

ally started in the 1970s [72�78]. It began as a way to replace the cathode ray tube (CRT) because

of its advantages including high contrast, high dpi (dots per inch), low power consumption, low

radiation and light weight. LCDs were also found ideal for mobile and portable applications.

Figure 1.35 shows the classification of displays by screen size and pixels [78]. Table 1.14 (p. 41)

lists major discoveries that led to today’s TFT-LCDs.

In 1888, Friedrich Reinitzer of Austria reported the existence of mesophase in cholesteryl

bezonate between the solid and liquid state. This behavior was further studied by Otto Lehmann

of Germany who named it “fliessende krystalle” (liquid crystal). Out of thermotropic and

BE

OL

FE

OL

Si

waf

erla

yer

devi

celo

cal

inte

rmed

iate

glob

al

inte

rcon

nect

win

ing

FIGURE 1.33

(a) Schematic illustrations of TSV, i.e. via-first, via-middle, and via-last (from left to right) [62]. (RIE: reactive

ion etching; BEOL: back end of the line; FEOL: front end of the line)

391.4 Sputtering materials for liquid crystal displays

FIGURE 1.34

Images of TSV in which 50 μm die thickness and 10 μm diameter TSV have been used [71].

FIGURE 1.35

Classification of displays by screen size and pixels [78].


lyotropic liquid crystals, a particular variety of lyotropic liquid crystals called nematic and

twisted nematic liquid crystals are predominantly used in displays. Nematic liquid crystals

appear as thread-like structures under microscope and exhibit anisotropic physical properties.

Refractive index, dielectric constant, permeability, electrical conductivity and viscosity measured

in the direction of the long axis are different than those measured in the plane normal to the

long axis. Before liquid crystals were used in displays, they were used in selective reflection of

light. Until 1960, not many institutions carried out research and made attempts to develop com-

mercial products based on liquid crystals.

The next major development was TFT. In 1961, Paul K. Weimer of RCA Labs, Princeton, NJ

first made a TFT based on a microcrystalline CdS semiconductor. In 1962, Richard Williams of

RCA Labs, Princeton, NJ first noticed the formation of domains due to ordering in the liquid crys-

tal, which eventually laid the foundation for LCD development. He sandwiched liquid crystal

p-azoxyanisole (PAA) between two glass plates 50 μm apart, which had transparent tin-oxide con-

ducting coating. The range over which PAA showed the liquid crystal phase was 117�134�C.G. H. Heilmeier’s work on liquid crystal at RCA labs established that cathode ray tubes (CRT)

could be replaced by LCDs. In 1973, Peter Brody first used CdS-based TFTs to control pixels in

LCDs to obtain superior characteristics such as the absence of a ghost-shadow image, a grayscale

capability and a large viewing angle, compared to a conventional (passive matrix) LCD [75,77]. He

named it active-matrix LCD (AMLCD). Later, AMLCDs were used for direct view as well as pro-

jection displays. Both direct and projection displays can be transmissive or reflective type. In-depth

discussion of this subject can be found elsewhere [72,75,77].

In the early 1980s, TFT made of semiconductors such as CdS, Te, InSb and Ge were inves-

tigated. However, real momentum in LCD commercialization was gained after doped a-Si was

successfully deposited using glow discharge techniques. In 1979, W. E. Spear and P. G.

LeComber first fabricated a-Si:H TFT. Subsequently, research activities in the area led to low

temperature and large area a-Si:H TFT array fabrication. By then, AMLCDs had experienced

Table 1.14 Major Inventions in Liquid Crystal Research and Display Industry

Year Invention

1888 Discovery of mesophase liquid (cholesteryl benzonate) by Friedrich Reinitzer, Austria

1889 Otto Lehmann of Germany named mesophase liquid “fliessende krystalle” (liquid crystal)

1907 Record of liquid crystal selling by E. Merch of Germany

1935 Concept of thin film transistor (TFT) presented

1961 First CdS based TFT made by P. K. Weimer of RCA Labs, Princeton, NJ

1962 Richard Williams of RCA Lab, Princeton, NJ demonstrated formation of domains

1964 G. H. Heilmeier’s work established that cathode ray tube (CRT) can be replaced by liquid crystaldisplay (LCD)

1973 First liquid crystal pocket calculator launched by Sharp Corp.

1973 First TFT-LCD developed by Peter Brody

1979 First amorphous silicon (a-Si) TFT developed by W. E. Spear & P. G. LeComber

1988 14 inch active matrix LCD display (AMLCD) produced


tremendous growth in the area of computers, avionic, automobile and consumer products. It is

important to note that although much of the fundamental work in the area of such

displays took place in the USA, countries such as Japan, South Korea and Taiwan have been

large players in display manufacturing. In the early stages of the development in Japan, new

and large facilities were constructed at the existing facilities for IC manufacturing sites

such as Tenri (Sharp) and Himeji (Toshiba/IBM Japan�DTI). In recent years, South Korea

and Taiwan have done extremely well in TFT-LCD technology development and their

commercialization.

In the last 20 years the electronic display industry has become a major part of the electronic

industry. The display industry has grown from $24 billion in 2000, $42 billion in 2003, $58 billion

in 2004 to approximately $100 billion in 2010. These displays include TFT-LCDs, plasma displays,

passive matrix liquid crystal displays, micro-displays and others. In recent years, TFT-LCDs

enjoyed almost 80% market share of all the displays. It has been projected that this trend will con-

tinue for some time. Light emitting diodes (LEDs) backlight has started to replace standard cold

cathode fluorescent back-light sources because of greater efficiency and low power consumption.

Overall consumption of the sputtering targets for the displays rose from $380 million in 2003 to

about $1500 million in 2010. These sputtering targets include indium tin oxide (ITO), alumi-

num�neodymium alloy (Al-Nd), chromium (Cr), molybdenum (Mo) and other materials. Because

of the importance of a-Si: TFT-LCDs, discussion on sputtering materials will primarily focus on

the a-Si: TFT-LCDs.

1.4.2 Active-matrix liquid crystal displaysFigure 1.36 shows the basic configuration of a transmission-type AMLCD revealing major com-

ponents and how liquid crystal transmits light to form images [73,74]. The major components of

a TFT-LCD include the front polarizer, color filter, front glass plate (coated with a transparent

electrode), front liquid crystal alignment layer, liquid crystal layer, back liquid crystal alignment

layer, back glass plate (with TFT array), rear polarizer and back light unit [75,77]. Color filters

consist of three primary colors such as red, green and blue pixels to be coated on the glass

plates [79,80]. The liquid crystals are twisted at an angle of 90�. If electricity is sent to the liq-

uid crystal, the liquid crystals in each layer are oriented in the same direction. Then the light

from the lower polarizer can pass through the upper polarizer. Thus liquid crystal controls the

light’s permeability using different molecular structures that vary in accordance with the voltage.

This means, in each pixel the liquid crystal layer functions as a light shutter that is controlled

by the TFT. Hence, through the control of light transmittance, a LCD displays the desired color

and image. In a reflective-type display, a reflective metal replaces the transparent pixels and

backlight is eliminated. Standard textbooks and current literature on this subject are a good

source of information on working principles of AMLCDs [72,75,77].

As shown in Figure 1.37, (p. 44) the bottom glass panel is made of an array of TFTs called

the TFT array, indium tin oxide (ITO) pixel electrodes, storage capacitors, gate buslines (rows),

data buslines (columns) and so forth [73,74]. Note the layout of TFT array along with gate bus-

line, source-drain layer, data busline and the pixels. Glass substrates used in AMLCDS are usu-

ally fused borosilicate glasses that have low sodium content and low thermal expansion

coefficient along with high strain point. The size of the glass substrates has increased over the


years (Gen 1: 3003 400 mm; Gen 5: 11003 1250 mm; Gen 10: 28803 3130 mm). The thick-

ness of glass substrate varies between 0.5 and 0.7 mm, though 1.1 mm thick glasses were used

in the 1990s. TFTs can be based on hydrogenated amorphous silicon (a-Si:H) or ploy-silicon

(p-Si). For example, Figure 1.38(a) (p. 45) shows the schematic cross-section of a bottom-gate

type (inverse staggered) a:Si-TFT and materials used for constructing it. A cross-sectional

transmission electron micrograph of a real TFT is shown in Figure 1.38(b). Depending on the

size and other requirements of a display, the gate is formed by depositing a bi-layer or tri-layer

(e.g., Ti-Al-Ti, Mo-Al-Mo, Al-Mo, Al-Nd/Mo). These films are deposited using sputtering and

usually from rectangular sputtering targets.

As shown in Figure 1.39 (p. 45), after forming the gate insulator and semiconductor layer using

PECVD, source-drain is formed by depositing similar stacks as that of gate using sputtering. The

reasons for choosing these metal and alloys are discussed in detail in Chapter 6. Table 1.15 (p. 46)

lists thin film materials typically used in TFT array-making for AMLCDs and their deposition

methods. Most TFTs are not transparent themselves but transparent ITO being the pixel electrodes,

terminals and interconnections are often transparent. Because glass cannot withstand high tempera-

ture, the processing temperature for TFTs is usually kept below 400�C.

FIGURE 1.36

A simplified version of the cross-section of an AMLCD revealing major components and how liquid crystal

transmits light and forms images [73,74].


1.4.2.1 TFT array fabricationIn broad terms, AMLCD manufacturing can be divided into two major segments, namely front-end

processing and back-end processing. In particular, front-end processing that involves TFT array

fabrication has similarities to semiconductor manufacturing in terms of equipment used, unit pro-

cesses and expertise. Front-end processing is capital-intensive, while back-end processing (color fil-

ter processing, cell assembly and module assembly) is more labor intensive. Manufacturing process

and yield issues are usually company secrets, so a brief description of a-Si: TFT array fabrication

for AMLCD will be presented.

Figure 1.39 shows a TFT array manufacturing flow chart, which requires unit steps such as

PECVD, sputtering, wet etch, plasma etch, photolithography, cleaning and thermal annealing.

FIGURE 1.37

(a) Cross-section of an AMLCD revealing major components, (b) top view of the TFT and (c) position of TFTs

and pixel electrodes in relation to the data bus-line and gate bus-line [73,74].


However, rather than building the transistors out of silicon that has been formed into a crystalline

wafer, a-Si: TFTs are fabricated from a silicon thin film deposited on a glass panel. Transistors

take up only a small fraction of the area of each pixel, and the silicon film is etched away in the

remaining areas, allowing light to pass through.

FIGURE 1.38

(a) Schematic cross-section of a bottom-gate a-Si: TFT. (b) Cross-sectional transmission electron micrograph

of a TFT [Internet]. Note sputtering requirement for gate and source�drain constructions.

Glass substratecleaning

ITO(Sputtering) a-Si patterning

SiNx/a-Si/+na-Si stack dep.

PECVD

ITO patterningSource – drain

(Sputtering)

SiNx depositionPECVD n+a-Si etch back

Source – drainpatterning

Passivation etch

Gate metal(Sputtering) Gate patterning

a-Si: TFT array fabrication flow chart

FIGURE 1.39

A typical flow chart for making a-Si:TFT array on glass substrate.


First, the gate metal layer is deposited using sputtering. This also functions as the gate busline

for the display. The thickness of the gate metal layer varies between 200 and 300 nm. The gate

metal electrode and gate busline materials must have low resistivity in order to avoid signal delay

and also satisfactory resistance to protrusions like hillock and whisker formation at elevated temper-

ature encountered in subsequent processing steps.

Figure 1.40 shows formation of whiskers in an annealed aluminum film (see Chapter 6 for more

details) [81]. Immediately after gate metal layer deposition and patterning, a gate dielectric such as

SiNx is deposited at about 350�C for 30 minutes to 1 hour using a plasma-enhanced chemical vapor

(PECVD) deposition technique. Because of the difference in the thermal expansion coefficients of

the glass substrate and the aluminum film, a large compressive stress is developed during annealing

and this stress is relieved in the form of hillocks and/or whiskers, as shown in Figure 1.40, because

of the enhanced diffusion of aluminum atoms in the film grain boundaries [82,83]. However, it is

also common to use a bi-layer or tri-layer for gate metal applications for relatively smaller displays

because of the less stringent resistivity requirement. In the bi-layer case, either titanium (Ti) or

molybdenum (Mo) under-layer is used between the glass and the aluminum film. Ti under-layer

has been found to improve the adhesion characteristics of aluminum film to the glass substrate and

also modify the crystallographic texture in aluminum film that has better hillock and whisker

resistance.

The bi-layer of aluminum (Al) or aluminum�neodymium (Al-Nd) alloy with Mo cap has also

been reported in the literature [82�84]. Mo cap is known to suppress the hillock and whisker gen-

erated in the aluminum film [83]. In the tri-layer cases Ti-Al-Ti and Mo-Al-Mo layers are used by

some manufacturers. With increasing demand for large displays there is growing demand for low

resistivity sputtering materials such as aluminum alloys. Table 1.16 lists materials that have been

sputtered to form TFT arrays and color filters on glass panels. All such thin film materials are

deposited from rectangular planar or tubular sputtering targets. For planar stationary targets and

conventional magnetrons, material utilization is 30�40%, while for moving magnetron material uti-

lization it can be between 40�50%. Tubular targets have shown better utilization (up to 80%) of

materials and in recent years, a few OEMs have made major advancement in this direction.

Table 1.15 Common Materials and Deposition Methods for AMLCD Fabrication

Function Thin Film Materials Deposition Methods

Gate electrode, gate line,data line

Al, Al-2Nd, Mo, Ta, Ti, Cr etc. Sputtering

Under-layer, cap Ti, Mo, Mo-W, Mo-Cr, Mo-Ta etc. Sputtering

Dielectric SiNx, SiO2, SixNy, Ta2O5. Al2O3, dualdielectrics etc.

PECVD, APCVD, sputtering,anodization, etc.

Semiconductors a-Si:H, polysilicon, CdSe etc. PECVD, LPCVD, evaporation, etc.

Transparent pixel &electrode

ITO Sputtering

Ohmic contacts P-doped n1 a-Si, n1microcrystalline-Si

PECVD: Plasma enhanced chemical vapor deposition; APCVD: Atmospheric pressure chemical vapor deposition.


Figure 1.41 shows the Unaxis UNI 1200 sputtering tool for TFT fabrication [85]. Other OEMs

include Applied Materials, Ulvac, Canon Anelva, etc. In the next step, the gate metal layer is pat-

terned using wet or dry etching.

In the subsequent step, the gate dielectric of SiNx (300�400 nm), a-Si:H (150 nm) and P-doped

n1 a-Si (20 nm) layers are deposited in sequence using PECVD in a cluster tool without breaking

the vacuum (Figure 1.42) [86]. NH3, silane (SiH4) and NF3 gases are used for the PECVD

FIGURE 1.40

A TEM showing aluminum whisker developed in a TFT structure [81].

Table 1.16 Sputtering Materials and their Property Requirements

Function Property Requirements Materials

Gate electrode andgate busline

Low resistivity, resistance to hillock & whisker formationduring annealing, etchability, adhesion to glass

Al, Al-2Nd, Mo, Ta,Ti, Cr, etc.

Under-layer Adhesion to glass and gate metal layer, low or moderateresistivity, ability to modify texture in metal layer to improveresistance to hillock & whisker formation

Ti, Mo

Cap layer Low or moderate resistivity, ability to suppress hillocks andwhiskers

Ti, Mo

Source-drain layerand data busline

Low resistivity, resistance to hillock & whisker formationduring annealing, etchability, suitable contact resistanceto ITO

Al, Ti, Mo, Mo-W,Mo-Cr, Mo-Ta, etc.

Barrier layer Ability to prevent Si diffusion to source-drain metal layerand the data busline

Mo, Mo-W, Mo-Cr,Mo-Ta, Ti, etc.

Transparent pixel &electrode

Refractive index, resistivity, etchability ITO

Black matrix Optical density, stability Chromium


deposition of SiNx/SiN, a-Si:H and cleaning of PECVD chambers, respectively. Then, this stack is

subjected to a second patterning to define the Si islands. Next, the source-drain metal layer and the

data busline are deposited using sputtering, and the choices of materials are the same as the gate

metals. This minimizes the process complexity by reducing the metallization type. An additional

requirement for the source-drain metal layer, in particular for aluminum, is not to see Si from the

bottom layer. Hence, it is important to prevent Si diffusion from underneath to the source-drain alu-

minum layer by applying a barrier layer. Often a barrier layer of refractory nature such as Mo or Ti

is deposited between the n1 a-Si layer and the source-drain metal layer. The subsequent patterning

is done to construct the source-drain of the TFT and also the data busline. Even after the source-

drain has been patterned, n1 a-Si layer may still be present in the TFT channel. This is removed

using a dry etch known as back-channel etching (BCE). The uniformity of this etching step is very

important for proper functioning of the TFT.

In the next step, a thick SiN passivation layer of the order of 200 nm is applied using PECVD.

This layer protects the TFT and the data busline from liquid crystal fluid. This SiN passivation

layer is patterned to form vias and contact holes at the drain location and also at the edge for inter-

connections. The final step involves making a transparent conducting oxide layer (e.g., ITO) using

sputtering. The thickness of the ITO layer varies between 300 and 700 nm. ITO makes contact to

FIGURE 1.41

(a) Schematic illustration of a Unaxis’ UNI 1200 sputtering tool (with BigMagTM cathode) that can hold

several sputtering targets. (b) Image showing real sputtering targets inside the chamber [85].


the TFT through the contact holes in the passivation layer of SiN. Some manufacturers deposit and

pattern the ITO layer before source-drain metal layer construction.

In recent years, to take advantage of reduced resistivity of copper and silver, copper, copper alloys

(Cu-Mg, Cu-Al, Cu-Ni, Cu-Ta, Cu-Sn, Cu-In, etc.) and silver alloys have also been studied for possible

application in the gate for large displays [87�92]. The results of these studies are discussed in Chapter 6.

1.4.2.2 Cell assembly and Module assembly fabricationThe back-end process consists of cell assembly and module assembly processes [77,93]. In the cell

assembly process, color filter fabrication on glass substrate, alignment layer printing on both TFT

array substrate and the color filter substrate, spacer spray on color filter substrate, liquid crystal

injection and sealing operations are completed. Figure 1.43 shows the architecture and various com-

ponents of the color filter, i.e., black matrix, pixels (red, green and blue), overcoat and common

electrode [73,74]. Note that here sputtered chromium film has been used for making black matrix

and ITO film for electrode preparation [94�98]. The black matrix plays an important role in block-

ing the light to TFT and preventing the contrast ratio reduction. As shown, sputtered chromium is

the most common black matrix material. Carbon black and chrome mixed oxide are some of the

alternatives. The requirement for color filter include high color purity, high transmissivity, high

contrast, low reflection, high stability against heat, light and chemicals.

There are four color filter fabrication methods, namely dying, pigment dispersion, printing and

electro-deposition. For example, pigment dispersion technology has found wider acceptance

because of high heat, light and chemical resistance as compared to die systems. Pigment dispersion

can be achieved using the etching or photolithography method. The pigment system shows high

resistance to the solvent and acid alignment layer used during etching of the ITO. Unit processes

such as photolithography, printing, alignment layer rubbing, cleaning, bake hardening, liquid crystal

injection and sealing are used in the cell assembly process. This completes the LCD panel

FIGURE 1.42

(a) Cluster tool of Applied Materials Inc., CA used for TFT-LCD manufacturing [86].


fabrication. In the module assembly process, the LCD panel is fitted to the chassis with a back-

light unit. For example, tape automated bonding (TAB) is used to attach the LDI chip to a tape-

carrier package, and the tape-carrier packages are then connected to the TFT-array substrate.

Figure 1.44 shows a schematic of a TAB-mounted module assembly.

1.5 Sputtering materials for magnetic storage systems1.5.1 IntroductionIn this age of information technology, there is ever-increasing demand for low-cost, high-

performance and non-volatile storage systems. A wide variety of information storage systems are

available, which include magnetic tape drives, magnetic floppy drives, magnetic hard disk drives

(HDD), magneto-optic disk drives, phase change optical drives, semiconductor flash memory, mag-

netic random access memory and holographic optical storage [99�102].

FIGURE 1.43

Color-filter of a representative AMLCD. Note sputtering requirement of chromium (Cr) and indium tin oxide

(ITO) [73,74].


The two building blocks for magnetic recording are (a) the magnetic recording read and write

heads and (b) the magnetic media. Figure 1.45 shows the basic components of a magnetic record-

ing. The write head emits flux driven by a current that carries the information to be stored in a

medium (flexible/rigid). This flux changes the state of magnetization in the magnetic medium. On

the other hand, the read head senses the flux produced by the magnetization pattern of the magnetic

medium. The read head produces a voltage out of the magnetic medium.

In a rigid disk drive, as in HDD (Figure 1.46), information is stored on concentric tracks of

magnetic media supported by disk platters that rotate with the help of a spindle motor [99]. Disk-

shaped platters are made using aluminum�magnesium alloys or glass ceramic composites (e.g.,

MemCor, a brand name of Dow�Corning Corp.). Media is either an iron oxide particle contain-

ing layer or a stack of thin films. The width of the track in media depends on the size of the write

head. The density of the recording (per square inch), also known as areal density, is the product

of number of tracks per inch and the density of track along a track, i.e., bits per inch (given by

Gb/in2).

Figure 1.47 shows the growth in areal density by year with the development of various storage

technologies [100,101]. Note that thin film MR and GMR heads as well as media require sputtered

thin film device fabrication. Since the 1960s, the areal density of information storage in hard disk

drive has doubled every 2�3 years leading to a 30% annual growth rate. In the mid-1990s, the

growth of areal density doubled to 60% per year. This was possible because of the use of magneto-

resistive (MR) heads and advanced thin film media. For example, 1 Gb/in2 was demonstrated by

FIGURE 1.44

Module assembly of an AMLCD.

FIGURE 1.45

Schematic illustration showing the operating principle of magnetic recording.

511.5 Sputtering materials for magnetic storage systems

IBM in 1991 [103]. This involved 158 kfci (thousand of flux changes per inch), 7470 tpi (track per

inch) and 3.4 μm track pitch in recording media. Because of the development of the spin-valve

read head based on the giant-magnetoresistive (GMR) effect and Co-Cr-Pt-Ta thin film media in

1997, it was possible to achieve areal density of 5 Gb/in2. This resulted in 0.7 μm track width and

140 nm long bit size (7 bits/μm).

Table 1.17 lists the major inventions in magnetic storage industry. The historical development

of individual technology can be found elsewhere [15,16,102]. In this section, a brief discussion on

the use of magnetic materials in HDD is given because of their very distinctive property

FIGURE 1.47

Areal density increase with time for magnetic hard disk drive. Note 60 to 100% compound growth rate between

1992 and 2000 because of (a) the advancement in thin film magnetic recording media [100]. (b)

Magnetoresistive head technologies (MR, GMR, TMR heads) [101]. Note the use of sputtered thin films in media.

FIGURE 1.46

Schematic illustration of showing various components of a hard disk drive (HDD) [99].


requirements and commercial importance. In particular, sputter-deposited thin films used in such

applications will be the main focus of this discussion.

1.5.2 Thin film heads1.5.2.1 Inductive headAn inductive head is made of a write head and read head. Inductive heads can be categorized into

two groups, namely bulk ring heads and thin film heads [15,16,100]. Traditionally, bulk ring heads

were made of magnetically soft ferrites (MnZn, NiZn) that had low coercivity and high permeabil-

ity. These ferrite heads evolved from IBM’s 30�30 Winchester drive, which had an iron-oxide

core wrapped with electromagnetic coils. A particular type of ferrite head design, known as a com-

posite ferrite head, comprising a smaller ferrite core bonded with glass in a ceramic housing

became popular in the 1980s for its smaller head gap and its ability to increase track density. In

such ring heads, magnetic poles were machined, coils were mechanically wound around a magnetic

pole and the recording head gaps were formed by glass bonding. This type of bulk ring heads could

not write to high coercivity media necessary for high density disk.

Subsequently, another improved version of ferrite head, called a metal-in-gap (MIG) head,

evolved in which a magnetic alloy film (Sendust, 85 Fe-9 Si-5.4 Al by wt%) was applied to the

head gap. This alloy showed twice the magnetization capability of ferrites. In a single-sided MIG

head, this magnetic film was deposited along the trailing edge of the head gap, while in the double-

sided MIG head, magnetic films were deposited on both sides of the gap. Deposition of the

Table 1.17 Major Inventions in Magnetic Storage Industry

Year Inventions

1898 Valdemar Poulsen of Denmark invented first recording device

1935 AEG developed Magnetophon used in audio recording

1953 IBM made first tape drive (726)

1956 IBM introduced first magnetic hard drive

1963 First compact audio cassette introduced

1966 First disk drive with bulk ring ferrite head

1971 First floppy drive

1978 Sony introduced first digital recorder

1984 Thin film MR recording head used in an IBM tape drive

1988 GMR effect discovered

1989 IBM achieved 1 Gb/in2 areal density

1991 First hard disk drive with MR heads

1997 GMR head introduced by IBM

2000 IBM introduced spin-valve based on GMR effect


magnetic films was done using sputtering. Hence, manufacturing of MIG ring heads required a

machining operation, thin film deposition and bonding operation. In the 1980s and early 1990s,

MIG heads were popular and used in many hard disk drives.

With the exception of a few specific applications, thin film heads have largely replaced the

bulk ring heads because ring heads cannot achieve the dimensional refinements needed for high

density recording. Relatively small and lightweight thin film heads can float at much lower

height above media than conventional ferrite and ferrite MIG heads. This enables thin film

heads to pick up and transmit stronger signal from media. The smaller size of thin film heads

also allows more platters to be stacked closer together into the same space. Hence, we will

focus on the thin film inductive heads that show improved recording density and resolution rela-

tive to bulk ring heads.

Thin film based heads evolved from IBM’s 3370 thin film head introduced in the 1970s. Thin

film heads are fabricated using processing steps similar to those in chip fabrication. Figure 1.48

shows a schematic cross-section of a thin film inductive head with multi-layer copper spiral coils

[15,16]. A scanning electron micrograph of a real thin film inductive head is shown in Figure 1.48

(b) [15]. Note that the image does not correspond to the schematic, and it has more layers of

copper coils.

Figure 1.49 (p. 56) shows a manufacturing flow chart of a thin film inductive head with a

single-layer copper spiral coil. The shaded boxes show steps where sputtering is used for depositing

thin films (e.g., Al2O3, copper, 81�19 Permalloy (P1), 50�50 Permalloy (P2), Sendust). Thickness

of the films can vary from as low as 100 nm to as high as 15 μm. A four-inch square wafer can pro-

duce more than 10,000 thin film heads.

In the given example, an Al2O3-TiC wafer was used. After mechanical polishing, a 15 μmthick Al2O3 layer was sputter deposited, which was lapped back to 10 μm thickness. Then the

bottom magnetic pole was either electroplated or sputtered to achieve a thickness of the order of

2�4 μm [15]. Usually electroplating is used for depositing NiFe film, while sputtering is used if

it is amorphous cobalt alloy or nano-crystalline FeN-bases alloy film (2�4 μm). Next, an Al2O3

gap layer of thickness 100�500 nm is deposited using sputtering and a via is etched out. The

thickness of the gap layer affects the resolution of the head. Then the insulating layer of the

order of 5 μm is formed using hard-cured photoresist. Subsequently, this insulating layer is pat-

terned and a copper seed layer is deposited using sputtering (later selectively etched) prior to

the electroplating of spiral copper coils. In the next step, the top magnetic pole layer (2�4 μm)

is deposited � the same as the deposition of the bottom magnetic layer. Then, 20�40 μm thick

copper studs are electroplated and a 10�15 μm thick Al2O3 overcoat layer is deposited by sput-

tering. Copper studs are then lap opened and a seed layer is deposited prior to the electroplating

of gold-bonding pads. Gold pads are used for wire bonding. Next, wafers are tested for

performance.

1.5.2.2 Magnetoresistive head (MR heads)In 1857, Williams Thomson discovered that some ferromagnetic materials show anisotropic magne-

toresistance. However, it was not until 1956 that this was put to successful use. Resistivity of such

ferromagnetic materials varies according to a cosine square function if the angle between the direc-

tion of magnetization and the direction of electric field is varied [15,16]. This effect was later called


the MR effect. The net result is that maximum resistivity (ρk) is reached when the direction of the

electric filed is parallel to the direction of magnetization. The minimum resistivity (ρ|) is reachedwhen they are perpendicular. The ratio (ρk�ρ|)/ ρ| is called the MR ratio (%).

The most common MR sensor material is Permalloy (Ni81Fe19), which has very high permeabil-

ity (. 2000). The MR ratio also depends on the thickness of the deposited film and the deposition

method. For an ion beam sputtered Permalloy film on a tantalum seed layer, the MR ratio values

were 1.2, 2.0, 2.3 and 2.6% for 50, 100, 150 and 250 A thick films, respectively. Conventionally

sputtered Permalloy film show relatively lower MR ratio values below 200 A thick films. The sig-

nal output of an MR head is directly proportional to the MR ratio of MR sensor material.

FIGURE 1.48

Thin film inductive head, (a) a schematic illustration, and (b) SEM image of a real inductive head [15,16].


The idea of a MR head for magnetic recording was first proposed in 1971 by R. Hunt. In 1990,

the introduction of an MR head showed promise of higher areal density. MR heads were capable of

increasing areal density by four-fold or more as compared to inductive heads. MR heads consist of

a MR reading head and a standard thin film inductive write head. MR read head produces voltage

directly proportional to the flux sensed by the head. The voltage produced by MR heads is larger

than inductive heads.

Figure 1.50 shows a schematic diagram of a representative MR head-and-slider assembly [103].

The slider carries the MR head. The MR read sensor in the head is a multi-layered structure depos-

ited by one of the sputtering methods. As shown in Figure 1.51, (p. 58) the shield layer protects the

MR sensor read element from stray magnetic fields [15]. When a second shield layer of the read

head functions as one of the magnetic poles of the write head, it is called a merged MR head.

Figure 1.51(a) shows a cross-section of a real merged MR head with an inductive write head

[15]. MR head fabrication technology is similar to thin film inductive heads, but the design and

fabrication steps are more complex in nature. Usually the MR read head is fabricated first and then

the inductive write head. The bottom shield is either sputter deposited or electroplated. The first

gap layer and also the second gap layer are deposited using sputtering. The top shield can be

electroplated or sputtered. The MR sensor element in the read head is a stack of thin films that are

not shown in Figure 1.51(b) [15]. Figure 1.50 shows the enlarged view of a typical thin film stack

that forms the MR sensor [103]. Typical values of MR sensor width, thickness and height are

Thin film inductive head fabrication flow chart

Al2O3 – TiCwater

Insulator layer(~5 µm)

cured photores.

Al2O3 (15 µm)(Sputtering)

Al2O3 gap layer(0.1-0.5 µm)(Sputtering)

Al2O3 (10-15µm) overcoat(Sputtering)

Pattern mag.pole & EP Cu

studs

Cu seed layer(Sputtering)

EP Au bondpadwith seed layer& wafer testing

EP Cu coil &pattern insulator

Magnetic poledep. (2-4 µm)

(EP / Sputtering)

Mag. pole (P2)dep. (2-4 µm)

(EP / Sputtering)

Lapping ofAl2O3

(to 10 µm)

FIGURE 1.49

A representative flow chart for thin film inductive head manufacturing.


2�4 μm, 10�20 nm and 1�2 μm, respectively. The bottom-most layer is the soft adjacent layer

(SAL). Then a spacer layer and MR layer are formed by sputtering. The choice of thin film materials

and sputter deposition techniques can vary from manufacturer to manufacturer. Table 1.18. Lists some

of the popular thin film materials used in MR sensors [104]. The fine details of MR head fabrication

are usually company secrets and selective information can be found elsewhere [15,16,104�106].

1.5.2.3 Giant magnetoresistive head (GMR head)The GMR effect was first described by Albert Fert of France and Peter Grunberg of Germany in

1988. They were awarded Nobel prizes for this discovery in 2007. In magnetic storage technology,

as track width decreased to accommodate high areal density, the demand drove the development of

the GMR-based spin-valve read head.

In 1997, IBM first introduced the GMR head, which was smaller in size than standard MR

heads. GMR enabled 20 Gb/in2 and more areal density, and virtually all HDD manufactured from

2000 used GMR heads. In simple terms, the MR layer in the MR head was replaced by additional

layers. A non-magnetic spacer layer was introduced between two ferromagnetic layers, which led

to pinning of a ferromagnetic layer with forced magnetization. This ferromagnetic layer was called

the pinned layer. On the other hand, the other ferromagnetic layer remained free from this effect

and was called the free layer.

FIGURE 1.50

Schematic illustration of a magnetoresistive head (MR head) and thin films used [103].


FIGURE 1.51

(a) Cross-section of a real merged MR head with inductive writer, (b) schematic illustration of MR head cross-

section [15].

Table 1.18 Film Materials used in MR Head (write and read heads) [104]

Layer Material Deposition Method

Shields Permalloy, Sendust Sputtering/Electroplating

Gap layer Al2O3

Soft adjacent layer (SAL) NiFeRh, NiFeMo,NiFeCo, CoZrMo

Sputtering

Spacer Ta, Ti, Al2O3, SiO2 Sputtering

MR layer Permalloy Sputtering

Hard bias CoPt, CoCr, CoCrPt Sputtering

Exchange bias FeMn, NiMn, IrMn,PtMn, PtMn, TbCo, NiO

Sputtering

Magnetic poles Permalloy (Ni81Fe19,Ni80Fe20), Ni45Fe55,CoNiFe, CoXZr, FeXN

Sputtering

Undercoat/overcoat Al2O3 Sputtering

Coils Ti/Cu, Cr/Cu Electroplating

Protective coating Carbon �


In GMR, the ferromagnetic/non-magnetic layers (e.g., iron/chromium) of certain thickness are

antiferromagnetically coupled in the absence of an external magnetic field. This makes it energeti-

cally preferable for the magnetization of the adjacent layers to align anti-parallel. The resistivity of

the multilayer is normally higher in the anti-parallel case. It is possible to align the magnetization

of the adjacent layers (ferromagnetic state) by applying a strong enough magnetic field, which sig-

nificantly lowers the resistivity of the multilayer. Hence, the GMR effect is electron spin dependent,

which involves electron scattering either at the ferromagnetic/non-magnetic layer interface or inside

the ferromagnetic layer. This led IBM to use the term spin valve to describe the GMR effect in

multilayers. Spin valve refers to a structure where the relative orientation of electron spins or mag-

netization in two adjacent layers controls the flow of the device current. In order to improve spin

valve performance, reflected in a higher MR ratio, either the interfacial resistance was increased or

a half non-magnetic layer was used in the structure.

Earlier studies used two ferromagnetic Permalloy layers and a non-magnetic copper spacer

layer. The most common three layer structures were made of a cobalt alloy based ferromagnetic

reference layer, non-magnetic copper layer and another cobalt-based alloy second ferromagnetic

free layer. The current flow in this device is electron-spin dependent. The resistance is at a mini-

mum when the magnetization of the reference layer and the free layer are parallel. The present-day

GMR sensors are much more complex than this three-layer structure.

Figure 1.52(a) shows the transmission electron micrograph of a multilayer GMR head [107].

The GMR sensor width is half of the track width and the sensor thickness is about 50 nm, which

is sandwiched between two shields (.1 micron thick). Figure 1.52(b) shows the enlarged sche-

matic version of the multilayer used in this GMR sensor. The bottom shield was electroplated.

Prior to depositing GMR sensor layers by sputtering, the shield layer was subjected to chemical

mechanical polishing (CMP). Then the alumina layer was deposited in order to electrically

isolate the GMR sensor from the shield. Next, a tantalum seed layer was deposited using sput-

tering. The tantalum seed layer provides good adhesion to the underlying layer (NiFeCr/NiFe)

and develops (111) texture favorable for the magnetic properties of the underlying layer. On the

top of the tantalum seed layer, first NiFeCr and then NiFe layers were deposited. During NiFe

layer deposition, coarsening of NiFeCr grains was recorded, which lowered the grain boundary

scattering and improved the spin valve performance. Next, the antiferromagnetic IrMn layer was

deposited. Then the ferromagnetic layer CoFe was deposited on the IrMn antiferromagnetic

layer. The pinning of the ferromagnetic layer’s magnetic moment by the exchange anisotropy

mechanism makes the ferromagnetic layer a reference layer. Next, a ruthenium (Ru) spacer layer

and CoFe layer, which were part of the pinned layer, were deposited prior to the deposition of

the non-magnetic copper spacer layer. The band structure of the copper layer (being close to

that of CoFe) allows electrons to pass without any significant spin loss. Next, CoFe and NiFe

layers were deposited, which were parts of the free layer. CoFe alloy and copper are immiscible

which improved spin valve output. Finally, the spin valve was capped with a copper�tantalum

bi-layer.

The tantalum layer prevents oxidation of the spin valve during processing. All these layers are

typically sputter deposited without breaking the vacuum [108�120]. Advanced lithographic techni-

ques are used to make such fine structures. The hard bias layer was magnetically hard CoPtCr

alloy. Next, the alumina gap layer and shield layer were deposited prior to write head fabrication.

In order to expose the GMR read sensor and to determine the strip height, heads were lapped. The


shape of the sensor is determined by the strip height and the track width. A standard wafer can pro-

duce 20,000 GMR heads.

Tunneling magnetoresistance (TMR) is an extension of the GMR effect in which electrons

travel with their spin oriented perpendicular to the layers across an insulating tunnel barrier that

replaces the non-magnetic spacer. This results in a large MR ratio and zero temperature

co-efficient. For high density recording, TMR heads have replaced GMR heads. Figure 1.53 shows

various thin film layers used in a representative TMR head [116]. Recently, Canon Anelva has suc-

cessfully achieved 230% magnetoresistance, three times the conventional value, and has claimed to

be the best-performing TMR device. A magnesium oxide tunnel barrier layer was used in this

device. Figure 1.54 shows an Anelva sputtering tool for TMR head fabrication [116].

1.5.3 Magnetic recording mediaMagnetic recording media in the form of disks are either magnetic particle based or continuous

magnetic thin film based. In the case of particles, an organic binder is used to retain these magnetic

particles. Modern magnetic disks are mostly thin film based and have complex multilayer

FIGURE 1.52

(a) Transmission electron micrograph of a representative GMR head, [107]; view as if looking up at the head

from the media, (b) a schematic illustration of the various layer used in this GMR head (drawing not in scale).


FIGURE 1.53

Schematic representation of various layer used in a TMR head [116].

FIGURE 1.54

A sputtering tool of Anelva for TMR head fabrication [116].


structures. Figure 1.55 shows an example of magnetic thin film based disk media. It has an alumina

substrate that is coated with NiP, often called an undercoat layer. This undercoat layer provides

stiffness, smoothness and proper texture to the media. This is coated with a chromium layer prior

to the deposition of the magnetic recording layer, which is usually a cobalt alloy. Both chromium

and cobalt alloy films are typically deposited using sputtering. The magnetic layer is then coated

with a carbon overcoat layer and a lubricant layer. These two layers are required to protect the

magnetic layer from tribological wear at the head�disk interface because of the high speed

(. 5000 rpm) rotation of the disk underneath the flying head. The distance between the head and

the top disk surface (fly height) is typically of the order of a few tens of nanometers (nm). This height

is a fraction of the distance between the head pole tip and the magnetic layer (magnetic spacing).

In the early years of magnetic recording using GMR and TMR heads, longitudinal recording

was used in thin film media in which magnetization of the bits lies in the plane of the magnetic

media (Figure 1.56(a); on the left) [121]. This geometry takes advantage of the strength of the

in-plane component of the head fringe field. The top illustration of Figure 1.56(b) shows an

enlarged view of the longitudinal media [122]. Information is coded in the locations where the

transition between opposing magnetization occurs.

Two major steps were taken to increase the areal density and signal-to-noise ratio of the media.

These involved increasing the in-plane coercivity of the media and decreasing the media grain size.

Such media are often called granular recording media [122,123]. Longitudinal recording has shown

bit density of 105 bits/inch. Typical alloys for granular media are cobalt (Co) based. Cobalt has the

magnetization along an axis of easy magnetization. Alloying additions such as chromium (Cr), plat-

inum (Pt) and tantalum (Ta) are used for controlling its intrinsic properties such as magneto-

crystalline anisotropy and exchange coupling between the grains. Pt is known to increase the

magneto-crystalline anisotropy constant of the cobalt alloy. Cr tends to segregate in the grain

Lubricant layer (3 nm)

Overcoat (10–20 nm)

Magnetic film (200–500 nm)

Crunderlayer (100–200 nm)

Al substrate (0.8 mm)

NiP (10 µm)

FIGURE 1.55

Schematic representation of various layers used in a longitudinal recording media. Drawing not in scale.


boundaries of the cobalt alloy and decrease exchange coupling among the grains that in turn

reduces the noise of the media. Cr also increases corrosion resistance of media. The addition of Ta

promotes segregation of Cr.

(a)

(b)

FIGURE 1.56

(a) Schematic illustration of two models of recording, i.e., longitudinal recording (at left) and perpendicular

recording (on right) [121] and (b) corresponding media in longitudinally and perpendicularly recorded state [122].


Figure 1.57 shows a TEM of a cobalt alloy media [121]. Media signal-to-noise ratio (SNR) has

been found to be inversely proportional to transition width (W), which is solely determined by the

location and distribution of the grains. As shown in Figure 1.57 transition centers do not lie precisely

where they are intended to. These misplacements are known as transition jitter, which dominates the

noise of the media. The other important factor is stability of bits, which is grain-size dependent. The

anisotropy energy of a grain is defined as Ea5KuV, where Ku is anisotropy energy density and V is

the volume of the grain. In order to withstand the effect of thermal agitation and magnetization to be

stable, the mean KuV value has to be in the range of 70�100 KBT. KBT represents the thermal

energy where KB is the Boltzman constant and T is the temperature in Kelvin. If KuV is too small,

because of very small grains, magnetization is no longer stable and this is called the superparamag-

netic effect. Therefore, for higher SNR, although smaller grains are preferred, a small KuV value can

lead to thermal instability of bits. The practical limit of longitudinal areal density reached to about

200 Gbits/in2. Further demand for even higher areal density drove the development of perpendicular

recording in which bits are written with magnetization pointing either up or down.

Perpendicular recording requires a different kind of write head than that used in longitudinal

recording. The read head is identical to longitudinal recording. Figure 1.56(a) (on the right) shows

a perpendicular recording head and media [121]. The magnetic flux for writing is sent through a

magnetic storage layer and then through a magnetically soft underlayer (SUL) beneath the magnetic

storage layer. The SUL guides the magnetic flux from write pole to the collector pole. It apparently

appears as if SUL performs like a mirror for the head structure and the media travels through the

gap field of the head rather than the fringe field. This arrangement can increase the magnetic field

significantly and allow writing transition in recording media with high anisotropy, which in turn

are thermally more stable. As a result, media with higher coercivity can be written with proper

selection of media material. In the design of SUL, materials with high permeability, high saturation

FIGURE 1.57

Transmission electron micrograph of a recording media showing written transition. The transition boundary

has to follow the microstructure of the media. The most optimistic case corresponds to recording within the

grain size limit [121].


magnetization and low coercivity such as NiFe, CoNbB, FeAlSi, CoFeB, FeTaN, FeTaC and CoFe

are the candidates. After film deposition, magnetic domain formation in the film is to be avoided as

their presence leads to increase in noise in the readback signal. Many of the above alloys form magnetic

domains in an as-deposited state. Annealing of films may remove the magnetic domains. Removal of

the magnetic domains is also possible by depositing SUL on an antiferromagnetic material.

Unlike parallel recording, fine-grain CoCrPt alloy film is not adequate for perpendicular record-

ing. A similar thin film deposition condition will result in coarse grains in the case of perpendicular

recording media. This has to do with keeping the axis of easy magnetization, i.e., the c-axis perpen-

dicular to the film surface. In order to develop a magnetic storage layer with low noise and high

thermal stability, additional property requirements are needed. These are reduced intergranular

magnetic interactions and alignment of easy axis of magnetization perpendicular to the media sur-

face. Usually an oxide has been used for grain isolation. In the case of perpendicular recording,

media architecture as well as thin film property requirements are different.

Figure 1.58(a) shows an example of a multilayer structure used in a perpendicular recording

media [122]. For high density recording, fine grain, uniform distribution, high anisotropy, good

magnetic coupling of grains, narrow alignment of c-axis in cobalt alloy and small distance from

SUL to the hard magnetic recording layer are desired. If a CoCrPt alloy, as used in parallel record-

ing, is used in perpendicular recording, media noise cannot be reduced because of the inadequate

segregation of Cr driven by the current heating of the media in perpendicular recording. Special

techniques of adding either oxygen or silicon dioxide (SiO2) in amorphous form to CoCrPt alloy is

used to control grain size and the segregation in the grain boundaries.

Figure 1.59 shows a transmission electron micrograph of the CoCrPt�SiO2 layer where grains

of CoCrPt have been magnetically isolated by SiO2 segregation in grain boundaries [121]. In order

to control the alignment of the c-axis of cobalt alloy grains, a ruthenium (Ru) layer has been found

useful. This is because of the epitaxial growth of Co(0002) on Ru(0002). Selection of a favorable

sputtering condition is also important to achieve columnar grains separated by oxide segregation.

Typically, high argon gas pressure (30�50 mTorr), low deposition rate and low substrate tempera-

ture favor formation of columnar grains. Table 1.19 (p. 67) lists various metallic films used in per-

pendicular recording media. The majority of the films are sputter deposited. Further details of

media fabrication can be found elsewhere [122�126].

It has been noted that in order to achieve 1 Tbit/in2 or more areal density, alternative technolo-

gies such as heat-assisted magnetic recording [127], patterned media [128] and cross-point memory

have larger roles to play [129]. In thermal-assisted magnetic recording, magnetic media (e.g., FePt,

CoPt) is heated to a temperature higher than the room temperature using a laser during the writing

process. Because coercivity and the remnant magnetization are known to vary approximately line-

arly with temperature, if a transition is written at elevated temperature a relatively small field is

required to write a transition. Thermal-assisted writing also enables sharp magnetic transition lead-

ing to higher stability and areal density [127]. The read process in heat-assisted magnetic recording

is similar to conventional magnetic reading systems.

In patterned media, a single magnetic domain (e.g., 3 nm in FePt) replaces many exchanged-

decoupled grains as seen in perpendicular recording. This means in patterned media, each single

island stores one bit of information as against many exchanged-decoupled grains in perpendicular

recording media. The 15�20 Tbit/in2 areal density was achieved by packing these islands in bit

cells as small as 6 nm3 6 nm in area [127]. Cross-point or cross-bar is a solid-state memory that


Substratepreparation

Protective layer(Sputtering)

⊥ magneticrecording layer

(Sputtering)

Surfacetreatmentprocess

Inspection

Non-magneticlayer

(Sputtering)

Lubricatingprocess

Precisioncleaning

Soft magneticlayer

(Sputtering)

Protective & lubricating layer (<5 nm)

Perpendicula magnetic recordinglayer (10 nm)

Non-magnetic interlayer (<5 nm)

Soft magnetic layer (150 nm)

Glass or aluminun substrate

(a)

(b)

FIGURE 1.58

(a) Perpendicular recording media (drawing not in scale), and (b) flow chart for media fabrication [122].

FIGURE 1.59

Cross-sectional transmission electron micrograph of a cobalt alloy based perpendicular recording

media [121].


utilizes active memory elements such as phase change materials, ferroelectric materials, magnetic

tunnel junctions, etc., in place of silicon-based transistors. These active memory elements are

placed at the intersections of two arrays of conducting lines. By this means the problem of scaling

in silicon-based flash memory is overcome. While oxide thickness of flash memory cannot be smal-

ler than 7 nm, because of increased tunneling current driven memory degradation, phase change

material has been found to be scaled-down to a cross-section of 3 nm3 20 nm [129]. Details of

these technologies and material use can be found elsewhere [15,16,127�129].

1.6 Sputtering materials for optical storage mediaWhile magnetic recording technologies are based on the switching of the magnetic polarity of mag-

netized domains, optical storage technologies use small areas (marks) on a media in the form of a

circular disc with optical properties that are different from their surroundings [130�132]. In order

to increase data storage capacity, the mark size in optical recording media has to be reduced the

same as the written bit size in magnetic recording media. Common optical storage media are com-

pact discs (CDs), digital video discs (DVDs) and Blu-ray discs (BD). Figure 1.60 shows the basic

components of a CD player and the construction of the optical media [133].

Typically a CD media has four layers: a polycarbonate plastic substrate, a thin metallic reflec-

tion layer, a spin-coated lacquer layer and a screen-printed artwork layer. As shown, the media

retains binary data (bits) in the form of pits (raised bumps) separated by lands (the flat area

between the pits). When a disc media is read, the pits correspond to 0 or off (due to the lack of

reflection) and lands correspond to 1 or on (due to a reflection). Optical discs can be divided into

three categories, namely pre-recorded, recordable (write once; R) and re-recordable (writable;

RW). Table 1.20 lists the various types of optical discs under these categories. All of them have

fairly simple construction in terms of layers used. Figure 1.61 (p. 69) shows the evolution of vari-

ous optical storage technologies in the data rate�storage capacity space and Table 1.21 (p. 69).

Lists key parameters for three generations of optical storage technologies [134]. Table 1.22 (p. 70)

lists major inventions that took place in the optical storage industry.

Figure 1.62 (p. 70) shows a CD manufacturing flow chart and typical unit processes. In the

beginning, a polished glass disc of diameter 240 mm and thickness 6 mm is spin-coated with a pho-

toresist layer (150 μm thick) that is hardened by baking at about 80�C for 30 minutes. Then a laser

Table 1.19 Examples of Thin Film Materials used in Media

Alloy Substrate Method of Deposition

γ-Fe2O3 NiP/Al Sputtering

Co Cr/NiP/Al Sputtering

CoP Plastic Plating

CoNiPt NiP/Al Sputtering

CoCrTa Cr/NiP/Al Sputtering

CoCrM Cr/NiP/Al Sputtering

CoNiCr CrGd/NiP/Al Sputtering

671.6 Sputtering materials for optical storage media

beam recorder is used to generate pulses of blue/violet laser to expose and soften portions of the

photoresist layer on the glass (known as the glass master). This is called laser recording [99].

In the next steps, i.e., master development, a sodium hydroxide solution is spun over the

glass master. This is done to dissolve the areas exposed to the laser, i.e., etch pits in the photo-

resist. Next, in the electroforming step, a nickel alloy layer is used to coat the glass master.

This develops a metal master called the father. Then, the metal master father is separated from

the glass master, which can be used for stamping discs. In the disc-stamping step, one disc of

polycarbonate can be pressed every 2�3 seconds in a modern stamping machine to press the

data image (pits and lands). Approximately, 18 gm of molten polycarbonate at 350�C is used

for this purpose.

Next, in the metallization step, polycarbonate disc base is sputter coated with aluminum

(50�100 nm thick) to make it reflective. In the protective coating step, metalized disc is spin-

coated (6�7 μm thick) with an acrylic lacquer followed by curing with ultra-violet light. This layer

prevents oxidation of aluminum reflective layer.

FIGURE 1.60

Schematic diagram showing major components of a CD player. The bottom-most figure shows construction of

a CD disc media including pits (raised bumps) and lands (flat area between pits) [133].

Table 1.20 Examples of Optical Discs

Optical Media Type Example

Pre-recorded CD, CD-ROM, DVD, HD-DVD, BD-ROM

Recordable CD-R, DVD-R, BD-R

Re-writable CD-RW, DVD-RW, DVD-RAM, BD-RE


Finally, a label is screen-printed on the disc and again cured with ultra-violet light. Most com-

mon CDs are 1.2 mm thick and 120 mm in diameter. The dimensions of each pit are 100 nm deep,

500 nm wide and length 850 nm to 3.5 μm. The distance between the tracks, the pitch, is usually

1.6 μm. The program area in a CD is 86.05 cm2 and the length of the recordable spiral is

(86.05 cm2/1.6 μm)5 5.38 km. Scanning velocity is usually between 1.2 and 1.4 m/s, which is

equivalent to approximately 500 rpm at the inside of the disc and approximately 200 rpm at the out-

side edge.

Sony first demonstrated an optical digital audio disc in September 1976 and then Phillips dem-

onstrated a CD audio player in March 1979. Its superior digital sound quality and large storage

1 KB 10 KB 100 KB 1 MB 10 MB 100 MB 1 GB 10 GB 100 GB 1 TB

Multimedia object size

1

0.01

0.1

10

100

1000

Dat

a ra

te (

Mbp

s)

HD-DVD or blu-ray technology

DVD technology

CD technology

CD-qualitystereoaudio

Broadcast-quality movie

(MPEG-2)

ProfessionalHDTV-quality

movie(compressed)

ConsumerHDTV-quality

movie(compressed)

VCR-qualitymovie

(MPEG-1)Scannedb/w page

(300 pixin)

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FIGURE 1.61

Evolution of optical recording technologies in terms of storage capacity and data rate [134].

Table 1.21 Key Parameters for Three Generations of Optical Storage Technologies [134]

Parameters 1st Generation 2nd Generation 3rd Generation

CD DVD HD-DVD BD

Laser wavelength (nm) 780 nm 658 nm 405 nm 405 nm

Capacity (single-layer disc) 650 Mb 4.7 Gb 15�20 Gb 25 Gb


capacity (650 Mb and more) led to the complete replacement of vinyl records and audiocassettes.

In playback mode, a laser of wavelength 780 nm (infrared) is used to read a CD through the bottom

of the polycarbonate layer. When the laser hits a land on the track, the light is reflected back. In

contrast, when the laser hits a pit, no light is reflected back. Therefore, in playback mode the laser

beam reads the modulation of the light reflected by these pits and lands from the disc media.

Table 1.22 Major Inventions in the Optical Storage Industry

Year Inventions

1958 Optical disc for video recording using pits (David Paul Gregg)

1972 Laser disc

1976 Sony demonstrated optical digital audio disc

1982 Compact disc (CD), digital audio

1985 CD-ROM (read only memory)

1988 CD-MO (magneto-optical re-writable)

1989 CD-R (write once)

1991 CD-R (recordable)

1995 CD-RW (read-write)

1996 DVD

1997 DVD-ROM & DVD-Video

2000 - Blu-ray disc (BD) and so forth

Photoresistcoating of glass

Disc stamping

Metallization(Sputtering)

Protectivecoating

Labeling(Screen printing)

Masterseparation

Electroforming

Laser recordingMaster

development

FIGURE 1.62

A representative flow chart for CD manufacturing.


Figure 1.63 shows typical configurations of CD-R (write once) and CD-RW (re-writable) [99].

In CD-R (write once), on the pre-groove side the polycarbonate disc is coated with a very thin layer

(110�120 nm) of organic dye. Then, the dye is coated with a thin (60�70 nm) reflecting layer (e.g.,

silver, silver alloy or gold). Finally, a protective coating of a photo-polymerizable lacquer is applied

on top of the metal reflector and cured with UV-light. Note that in the case of CD-R (write once)

Lacquer protective layer

Lacquer protective layerAluminum reflective layerDielectric insulating layer

Phase change recording layer

Dielectric insulating layerPre-Groove

Polycarbonate substrate

Gold reflective layer

Organic dye recording layer

Pre-Groove

Polycarbonate substrate

Burned “pits”

Read-Write laser

CD-R Media

CD-RW Media

(a)

(b)

Burned “pits”

Read-Write laser

FIGURE 1.63

Representative layered structures of CD-R (write once) and CD-RW (re-writable) optical media [99].


optical discs, the organic dye (e.g., Cyanine, Phthalocyanine, Azo and so forth) layer acts as an

information storage layer. CD-Rs based on cyanine dye are mostly green in color. Phthalocyanine

dye based CD-Rs are usually silver, gold or light green in color. Azo dye based CD-Rs are dark blue

in color. A CD-R recorder writes data to a media by using a laser in which it heats areas of the

organic dye layer.

The writing process does not produce pits and instead the heat permanently changes the optical

properties of the dye leading to change in the reflectivity of those areas. A CD-R can be recorded

in multiple sessions. Once a section of a CD-R is written, it cannot be erased or rewritten, unlike a

CD-RW. Using a relatively low laser power, so as not to further alter the dye, the disc media is

read back in the same way as a CD-ROM. The reflected light is not modulated by the alternating

regions of heated and unaltered dye. In the reading process, the change of the intensity of the

reflected laser radiation is transformed into an electrical signal, from which the digital information

is decoded. In CD-R media, the dye itself can degrade over time, causing data to become

unreadable.

For re-writable discs (e.g., CD-RW, DVD-RW, BD-RE), a metallic alloy layer made of phase

change materials (e.g., AgInSbTe, GeInSbTe, GeInSbSn) is the information storage layer

[131,132]. In a CD-RW disc media, typically the recording layer is made of AgInSbTe alloy. In its

as-deposited state AgInSbTe alloy film is polycrystalline in nature and has a certain degree of

reflectivity. In the writing process, the laser beam heats the AgInSbTe alloy layer to 500�700�C.On cooling, the AgInSbTe alloy layer loses its polycrystalline structure and assumes an amorphous

state. The amorphous material has reduced reflectivity. The lost reflectivity serves the same func-

tion as pits in a CD and the opaque spots in a CD-R. To erase the information from the disc media,

the write beam heats the amorphous regions of the AgInSbTe layer with low power that raises the

temperature to about 200�C. As a result, the AgInSbTe alloy film is not melted, but returns to the

polycrystalline state and thus becomes reflective again. Re-writable media with a suitable optical

drive can be re-written up to 100,000 times.

In the next stages of development, DVDs with two-disc construction emerged. Two 0.6 mm

thick polycarbonate discs coated with thin metallic layers were used in DVDs, which can be read

independently and from one or both sides. As compared to CDs, DVDs have a smaller feature size

and short wave-length (658 nm) readout laser. This lead to initial storage capacity of single-sided

and single-layer DVDs as large as 4.7 Gb. Figure 1.64 shows the materials typically used in a

DVD-RW disc media. The choices of phase change material are manufacturer dependent.

In the quest for greater storage capacity (15�25 Gb) in a DVD, smaller data bits and shorter

wavelength (405 nm) lasers are being used � as is the case of BDs and HD-DVDs. Note that the

majority of the layers in re-writable discs are sputter deposited (Table 1.23). With the exception of

single crystal silicon targets for semi-reflective layer applications, most sputtering targets are poly-

crystalline in nature. Reactive sputtering in a nitrogen atmosphere is used for Ge and GeCr targets

to form their nitride films for protective/capping layer applications. The common sputtering tools

used for depositing such films include Balzers ARQ tools, Singulus II, III and Smart, Shibaura

Stella, M2 Unisource, ODME Nova Focus, ODME Miniliner, 4M Phoenix and so forth.

Before CD-RW technology emerged, a standard for magneto-optical recordable and erasable

CDs, called CD-MO, was introduced in the early 1990s. CD-MO was essentially a CD with a

magneto-optical recording layer. Data recording (and erasing) was achieved by heating the

magneto-optical layer made of alloys such as DyFeCo, TbFeCo and GdFeCo up to their Curie


point. This resulted in erasing all previous data and then using a magnetic field to write the new

data. The details of magneto-optical recording can be found elsewhere [135].

1.7 Sputtering materials for photovoltaic devicesPhotovoltaic (PV) is a technology that generates electrical power from a semiconductor when

exposed to light [17,18,136�138]. This term has been used in the English language since 1849 and

is derived from the Greek words “φζ” (phos meaning “light”) and “voltaic” (after the Italian physi-

cist Volta). Figure 1.65 shows the basic components of a PV solar cell and building blocks of a

solar array used for power generation [139].

Polycarbonate layer

Reflective layer (e.g. Silver alloy)

Capping (e.g. GeNx, GeCrNx, SiNx)

Dielectric (e.g.80ZnS – 20 SiO2)

Dielectric (e.g.80ZnS – 20 SiO2)

Substrate (e.g.polycarbonate)

Capping (e.g.GeNx, GeCrNx, SiNx)

Active layer (Phase change alloy)

Capping (e.g.GeNx, GeCrNX, SiNx)

FIGURE 1.64

A schematic illustration of films typically used in a DVD-RW disc media.

Table 1.23 Films that are Sputtered Deposited on Optical Disc Media

Function Thin Films Deposition Method

Reflective layer Al, Al alloy, Ag, Ag alloy, Cu alloy Sputtering

Semi-reflective layer Ag alloy, Si Sputtering (reactivesputtering for Si)

Dielectric layer/protective(capping) layer

ZnS-SiO2/GeNx, GeCrNx, Si3N4 Reactive sputtering of Ge& GeCr

Recording layer Phase change materials (e.g., AgInSbTe,GeInSbTe, GeInSbSn)

Sputtering

731.7 Sputtering materials for photovoltaic devices

As we know, sunlight is a spectrum of photons distributed over a range of energy. Photons that

have higher energy than the band gap of a semiconductor can excite electrons from the valence to

the conduction band and these electrons can generate electrical power on exiting the PV device.

Photons that have lower energy than the band gap fail to excite free electrons. Table 1.24 lists

band-gap values of popular semiconductor materials that are in use in PV solar cells. The other

important property for PV energy conversion is the absorption coefficient (μ) of the semiconductor.

The absorption coefficient is a property of a material that defines the amount of light absorbed by

it. The significance of the absorption coefficient is that about 90% of the incident photons are

absorbed in a layer of the semiconductor of thickness μ/2. The absorption coefficient is photon

energy dependent and Figure 1.66 shows the absorption coefficients of various semiconductors as a

function of photon energy [140]. A small amount of high absorption coefficient semiconductor, in

the form of thin film, can be used for generating an equivalent or higher amount of power

Sunlight(photons)

Encapsulate seal

Top electrical contact

P-Type material(boran-doped silicon)

P/N junction

N-Type material(phoshorous-doped silicon)

Base contact

External circuit

Cell Module Array

(a)

(b)

FIGURE 1.65

Schematic illustrations of (a) a simple solar cell, and (b) building blocks/cell, module and array [139].


Table 1.24 The Band Gap and the Type of Semiconductor Materials Used in Photovoltaics

Semiconductor Band Gap (eV) Type

Silicon (Si) 1.11 Indirect

Cadmium telluride (CdTe) 1.49 Direct

Copper indium diselenide (CuInSe2, CIS) 1.01 Direct

Copper indium gallium diselenide(CuInxGa1-3Se2, x: 0 -1, CIGS)

1.0�1.7 Direct

Cadmium sulfide (CdS) 2.42 Direct

Copper sulfide (CuxS) 1.2 Direct

Tin oxide (SnO2) 3.7 Direct

Indium oxide (In2O3) and indium rich indium tinoxide (ITO)

2.8�3.07 Direct

Gallium arsenide (GaAs) 1.43 Direct

Indium phosphide (InP) 1.35 Direct

Amorphous silicon (a-Si) 1.6 Direct

1500 1000 500Wavelength (nm)

107

106

105

104

103

102

101

100

10–1

10–2

Alp

ha (

cm–1

)

0.5 1 1.5 2 2.5 3 3.5Photon energy (eV)

106

105

104

103

102

101

100

10–1

10–2

10–3P

enet

ratio

n de

pth

(µm

)

a-Si

c-Si

CdTe

CulnSe2 (CIS)

Microcrystalline Si

FIGURE 1.66

Absorption coefficient and penetration depth (1/α) of various thin film materials used in solar cells. CIGS has

a gap that is higher than that of CuInSe2 and its absorption curve is therefore slightly towards the right,

depending on the exact composition of the alloy, i.e., on the gallium content [140].


generated by low absorption coefficient semiconductors in the form of thick film or wafer (as is the

case in crystalline silicon, c-Si) [19,20,141�149].

Broadly, solar cells can be divided into two categories, namely wafer based (bulk) solar cells

and thin film based solar cells. Common thin film solar cells are cadmium-telluride (CdTe), cop-

per�indium�gallium�selenide (CIGS) and amorphous silicon (a-Si) based. Figure 1.67 shows the

basic components of wafer based c-Si solar cells [141]. The representative thin film solar cells

(CdTe, CIGS and a-Si based) are shown in Figure 1.68.

Another structure called the hetero-junction with the thin intrinsic layers has been found as

an alternative approach to attaining higher efficiency. This cell uses a hydrogenated a-Si coating

in combination with μc-Si wafer. These are called tandem and also micromorph solar cells.

150 µm3 mm Patterned metal contact

Phosphorus

Bulk of wafer

Rear metal contact

n++

n++n+

p+

p+

p-type

Metal

Metal

Oxideor

nitridep-type Plated metal

(buried contact)

(b)

(a)

FIGURE 1.67

(a) c-Si solar cell and (b) c-Si buried solar cell [150].


Figure 1.69 shows an example of a tandem thin film solar cell [140]. The advantage of thin

film solar cells over c-Si based solar cells are low production cost, less material use, lower

manufacturing facility cost, lower energy payback and also flexibility of using various types of

substrates. Because films can be deposited both on rigid and flexible substrates, thin film

solar cells offer several design possibilities (e.g., roll-to-roll processing, building integrated

photovoltaic).

c-Si is an indirect band-gap semiconductor with a low absorption coefficient that requires a

thicker layer ($100 μm) for the absorption of sunlight. Until recently the solar market was domi-

nated by c-Si in its multi-crystalline and mono-crystalline form. At least ten times more c-Si is

required to absorb a given fraction of solar radiation compared to other semiconductors like CdTe,

CIGS and even other forms of Si such as a-Si. Because preparation of c-Si ingots, diffusion of

dopants, sawing of wafers and interconnection of solar cells make c-Si technology expensive, such

solar cells have been used only in high-end applications.

Scrap silicon from the semiconductor industry has been one of the sources of silicon for photo-

voltaic industry. This is the reason c-Si solar cells are often categorized under bulk photovoltaic

technology. Typically, 180 to 240 μm thick Si wafers are used for single crystal c-Si solar cells.

Ribbon silicon is another form of c-Si that is formed by drawing thin films from molten silicon the

same as single crystal silicon ingot for making wafers [150].

The cost of production of ribbon c-Si based solar cells is lower than for c-Si wafer based solar

cells. Poly/multicrystal c-Si are made from cast square ingots cooled and solidified carefully.

However, for the production of tens of thousands of MW/year or even GW/year to meet the

demand, c-Si technology is not regarded as the cheapest considering the high cost of c-Si produc-

tion in large volume. As a result, the demand for thin film PV solar cells that use a smaller quantity

CdTe CIGS a-Si(a) (b) (c)

Glass substrate Glass substrate Glass substrate

Front contact(TCO)

Front contact(TCO)

Buffer layer (CdS) p-layer (a-Si)

i-layer (a-Si)

Back contact (Mo)

Absorber layer(CIGS)

Back contact (Mo)

Glass / metal foil

Front contact(TCO)

Buffer layer (CdS)

Absorber layer(CdTe)

Back contact (Mo)

FIGURE 1.68

Schematic diagrams showing various layers in thin film solar cells: (a) CdTe cell, (b) CIGS cell and

(c) a-Si cell.


of high absorption coefficient semiconductor materials in the form of thin films (a few μm thick)

has increased.

An important property of a solar cell is its energy conversion efficiency (η). Efficiency of a solar

cell is the percentage of power converted to electrical energy with respect to the power collected.

This is given by η5 Pm/E.A, where Pm is the maximum power point, E is the input light irradiance

under standard test condition (STC) and A is the surface area of the solar cell. STC refers to a tem-

perature of 25�C and irradiance of 1000 W/m2 with an air mass of 1.5 (AM1.5) spectrum.

Theoretical calculations showed that four junction thin film solar cells can reach an efficiency of

53%, while an infinite number of junctions can reach as high as 68% efficiency. Figure 1.70 shows

the evolution of various types of solar cells and their energy conversion efficiencies with time [151].

Note that this plot does not capture the recent advances made in solar research. Table 1.25 lists the

various types of solar cells. And the maximum efficiencies achieved until the end of 2010 [137].

The foundation of PV technology was established in 1883, when Charles Fritts first constructed

a junction with selenium (Se) and a thin film of gold as contact layer and noted that “the current, if

not immediately, can be either stored where produced, in storage batteries, . . . or transmitted a dis-

tance and there used.” The efficiency of the device was approximately 1%. Subsequently, in 1954

the accidental discovery of the voltage generation by a pn junction diode in the presence of room

light at Bell Labs (U.S.) paved the path for the modern era of photovoltaics. The team of Daryl

Chapin, Calvin Fuller and Gerald Pearson at Bell Labs, U.S. was able to produce a 6% efficient

solar cell within a year. In 1957, Hoffman Electronics of the U.S. was able to achieve 8% effi-

ciency. In 1959, this value increased to 10% and these PV arrays were used in an Explorer VI satel-

lite. In 1960, this value further increased to 16%.

Table 1.26 lists the notable events in the history of photovoltaic and solar cell development.

Traditionally, photovoltaic technology has been used in supplying power to space application, electronic

Back reflector

Back TCO (ZnO)

µc-Si:H

a-Si:H

Diffusion barrier (ZnO, TiO2)

High mobility TCO (SnO2/ITO)

Glass

Anti-reflection coating

Mirror layer (ZnO)

FIGURE 1.69

Micromorph tandem solar cell with an intermediate mirror layer between the amorphous top cell (a-Si:H) and

the microcrystalline bottom cell (μc-Si:H) and with a double layer as front TCO (a-Si/μc-Si tandem cell) [140].


Best research-cell efficiencies Spectrolab

Spectrolab

NREL/Spectrolab

Japanenergy

NREL

UNSWUNSWUNSW

Georgia tech UNSW

UNSWUNSW

Spire

Spire

ARCO

SolarexKodak

Kodak

Kodak

Boeing

Boeing

Boeing

Universityof maine

Matsushita

MonosolarRCA

RCARCARCA

RCARCARCA

solarex

Westing-house

No.State

Carolinauniversity

Stanford

NREL

Astro power Photon energyUnited solar

United solar

Astro power NREL

NREL

NREL

NRELCu(In,Ga)Se

214×concentration

NREL NREL

NREL NREL

Euro-CIS

SharpGeorgia techVarian

University oflausanne

University oflausanne

Universitylinz

PrincetonSiemens

CambridgeUCSB

UC berkeleyThe netherlands

ECN,

UniversitySo. Florida

AMETEK

ARCO BoeingBoeing

1975 1980 1985 1990 1995 2000 2005

Year

0

4

8

12

16

20

24

28

32

36

Effi

cien

cy (

%)

Emerging PVDye cells

Organic cells(various technologies)

Thin-Film Technologies

Cu(In,Ga)Se2CdTe

a-Si/a-Ge (stabilized)

single crystal

Crystalline Si Cells

MulticrystallineThin Si

Multi-junction concentratorsThree-junction (2-terminal,monolithic)

Two-junction (2-terminal,monolithic)

FIGURE 1.70

Progress in solar cell efficiencies (1976 to present) for various research and laboratory devices measured

under standard reporting conditions [151].

Table 1.25 State of Efficiency and Commercialization of Various Solar Cell Technologies Until the

End of 2010 [137]

Cell Type Efficiency State of Commercialization

Solar cell Si wafer based Mono-crystalline 15�18% Large-scale production

Polycrystalline 13�16% Large-scale production

Ribbon based 13�16% Small to mid scale production

Thin film based CIS/CIGS 9�11% Small to mid scale production

CdTe 8�10% Middle scale production

a-Si 5�7% Middle scale production

μc-Si 8�11% Small scale production

GaAs/GaInP2 20% in lab Small scale production

GaAs based triple junction� 42.3% Small scale production

InGaAs/CuInS2/CuInGaSe2 15% in lab Small scale production

Organic Dye sensitized 2�5% R&D

Organic 2�5% R&D

Hybrid 2�5% R&D

�Spire Semiconductor Corp.


calculators and applications in remote locations that are not connected to the conventional power supply

grid. Only in the 1990s the vast potential for photovoltaic technology was realized. As a result, three

new applications were tried in some developed countries. These were aimed at peak-load reduction, dis-

tributed generation and building integrated photovoltaics. In peak-load reduction application, photovol-

taic solar cells provided additional power to meet peak power demand in the afternoon. In distributed

generation application, power produced from solar cells was used for reducing the transmission losses.

In integrated photovoltaics, solar cells are built on the standard building components such as windows,

roof shingles, etc.

In recent years, although the cost of photovoltaic-generated power has come down because of

improved technology and innovation in high volume manufacturing, the success of solar energy

generation will depend on the efficiency of solar modules, energy payback time, government incen-

tives, carbon footprint generation, etc. Energy payback time is the length of time required for pho-

tovoltaic solar modules to generate an amount of energy equal to the energy used for

manufacturing them. Energy payback again depends on the solar cell efficiency, illumination

received and the manufacturing technology. The carbon footprint is the total amount of carbon

dioxide and other greenhouse gases emitted over the full life-cycle of a process/product. It is

expressed as grams of carbon dioxide equivalent per kWh of energy generation (gm CO2 equiva-

lent/kWh), which accounts for the different global warming effects of other greenhouse gases.

Table 1.26 Notable Events in the History of Photovoltaics and Solar Cells

Year Notable Events

1839 Edmond Becquerel (France) discovered the photovoltaic effect

1860 August Mouchet and Abel Pifre (France) constructed solar power engines

1873 Willoughby Smith (UK) discovered the photoconductivity in selenium

1883 Charles Fritts (US) described the first photovoltaic cell made from selenium wafer

1891 Clarence Kemp (US) patented the first commercial solar water heater

1905 Albert Einstein (US) published his paper on the photoelectric effect

1954 Daryl Chapin, Calvin Fuller and Gerald Pearson (US) developed siliconphotovoltaic cell at Bell Labs.

1955 Western Electric (US) began to sell commercial license for silicon photovoltaictechnology

1962 Bell Labs (US) launches the first telecommunication satellite, the Telstar poweredby 14 watts solar cells

1963 Japan installs 242 watt PV array on a lighthouse

1970 GaAs heterostructure solar cells were created by Zhores Alferov (USSR)

1973 World’s first solar powered residence built with Cu2S solar module (US); CherryHill, New Jersey conference on PV in the back drop of high oil prices

1980 First thin film solar cell with. 10% efficiency using Cu2S/CdS (US)

1985 Si solar cell with.20% efficiency under standard sunlight (Australia)

1995 German demonstration triggered present favorable PV legislation

2002 Cumulative worldwide installed solar modules reached 200 MW

2008 First Solar reaches cost per watt of $0.98 (US)


Results reported by Danish utility company Vattenfall in 1999 suggest that solar cells produce

50 gm of carbon dioxide per kWh of energy produced. Coal generates about 974 gm of carbon

dioxide per kWh. These results are somewhat old and because of the advancement in photovoltaic

technologies, today this difference could be even more. It is believed that the carbon footprint of

solar cells is at least 20 times smaller than coal and after three hours solar panels are carbon nega-

tive. While various university and government labs are working on the improvement of efficiency

of solar cells, many countries require government incentives to make solar cell generated power

more popular. Before the 2008 economic downturn, it was predicted that the thin film photovoltaic

market would grow at an annual growth rate of 100% in the next few years. This included a pro-

jected increase in revenue from $1.6 billion in 2008 to $7.0 billion in 2015. Thin film photovoltaic

technologies were expected to take market share of 15�40% of the photovoltaic market. However,

rather modest growth of thin film photovoltaic technologies has been noted in the last three years.

1.7.1 Silicon wafer based solar cellsFigure 1.67(a) shows a cross-section of a mono-crystalline c-Si screen-printed solar cell made using

bulk silicon wafer. The p-type silicon wafers used in such cells are doped with boron during single

crystal silicon ingot preparation [150]. A commercial module manufacturing process typically

involves steps such as wafer inspection, saw damage etching and texturizing of the front surface,

phosphorus diffusion to form p-n junction, phosphor-sillicate glass (PSG) removal, edge isolation

(etching of phosphorus containing oxide from the edge), deposition of antireflection coating,

screen-printing of front and back contacts, firing, testing, cell interconnection formation, encapsula-

tion, framing and module testing [152]. Usually 180�240 μm thick wafers are used for making c-Si

solar cells. Texturizing of the wafer surface reduces the reflection losses and this is done using a

solution of NaOH and cleaning in isopropyl alcohol.

In the next step, the p-n junction is formed by a phosphorus diffusion heat treatment. Usually

phosphorus is supplied by flowing nitrogen through liquid POCl3 and allowing a diffusion heat

treatment to take place between 900 and 950�C for about 10 to 15 minutes. Laser diffusion is an

alternative process. Phospho-sillicate glass is a byproduct of this reaction that needs to be

removed. Etchants such as HF and HNO3 are used to remove phosphosillicate glass. In the edge

isolation step, an etching method is used to remove residual phosphorus from edges. Next, an

anti-reflection coating (e.g., SiNx, TiO2) is deposited. For SiNx deposition, a mixture of SiH4 and

NH3 gases is used in a plasma-enhanced chemical vapor deposition (PECVD) process. TiO2 is

usually deposited using sputtering. The application of anti-reflection coating further reduces

reflectivity losses. Front and back contacts are made using screen-printing technology and firing.

In screen-printing of front contact, silver (Ag) paste from a dispenser is forced through a screen

to construct front contact. Aluminum (Al) back surface field (BSF), a uniform Al layer, is also

deposited using screen-printing.

Next, assemblies are subjected to a firing operation at elevated temperature (100�200�C) orinfrared treatment, which completes the cell fabrication. These cells are tested and, in the next

step, good cells are interconnected. This is followed by an encapsulation step in which cells are

placed on a suitable grade glass with sheets of silicon rubber or ethylene vinyl acetate (EVA) on

the top and bottom of the interconnected cells. Then a back sheet (e.g., Myler, Tedler) is placed

over this stack and subjected to a curing operation. In the next step, the encapsulated module is


framed using aluminum and subjected to final module testing. For commercial Si wafer based

modules, multi-crystalline silicon wafer are gaining momentum. In the fabrication of silicon

wafer based solar cell, the use of sputtering has been very limited, e.g., only in the deposition of

anti-reflection coating, TiO2.

Figure 1.67(b) shows the buried contact mono-crystal solar cell [150]. This design was a low-

cost approach that involved laser grooving of the surface of cells through the highly diffused layer

and dielectric coating. Such grooves expose fresh silicon that is heavily doped in a second diffusion

heat treatment. In terms of function, this structure allows full response to the blue-wave length and

lower series resistance. A 10�20% performance advantage was reported in buried contact c-Si cell

as compared to the screen printed c-Si cell.

1.7.2 Thin film solar cellsThin film solar cells are promising because of the scope of device design in terms of junction for-

mation, substrate types, substrate size and tailored performance. Although the solar cells appear to

be a simple junction device in which two electronically dissimilar materials are separated by an

electronic barrier to separate charges, process parameters for thin film deposition greatly affect the

device performance. The most common device junctions in thin film solar cells are CdTe, CIGS

and a-Si based.

Figure 1.68(a�c) show typical constructions of CdTe, CIGS and a-Si thin film solar cells.

Substrate (glass, metal, polymer) of a solar cell is a passive component, but it may play an impor-

tant role in determining the efficiency of the cell. For thin film solar cell that requires high temper-

ature processing of thin films, suitable glass or ceramic substrate is used. Sodium (Na) containing

soda-lime glass substrate is used in CIGS solar cell, because it improves cell efficiency. If Na-free

substrate is used, an Na precursor such as Na2Se, Na2S or NaF is incorporated on the substrate

surface during device fabrication. For CdTe solar cells, typically borosilicate glass substrate for

high temperature (up to 600�C) processing and soda-lime glass substrate for low temperature

(60�500�C) processing are used.

As shown in Figure 1.68, all three types of thin film solar cells require front and back contacts that

are usually sputter deposited. Adequate conductivity, transparency to light and haze are some of the

important property requirements for front contact layers. Haze describes the ability of a layer to trap

light. These requirements are fulfilled by transparent conducting oxides (TCOs). The choice of a TCO

also depends on the absorption edge of the thin film cell [153,154]. For CdTe and a-Si cells, with

absorption edge below 900 nm, fluorine-doped tin oxide, FTO (SnO2:F), or indium-tin-oxide (ITO), is a

suitable choice. For superstrate construction, where the absorption layer is directly deposited on the front

contact layer, commercially available FTO coated glass substrate is used for solar cell manufacturing.

As shown in Figure 1.71, after substrate inspection a TCO layer is sputter deposited on the glass

substrate. In the next step, the CdS buffer layer is deposited either by closed space sublimation

(CSS) or chemical bath deposition (CBD). A 3�10 μm thick absorber CdTe layer is typically

deposited by CSS, but sputtering, electrodeposition and spray pyrolysis can also be used. Both CdS

and CdTe can be deposited using CSS between 550�C and 600�C. Next, an activation heat

treatment is required in the presence of CdCl2 vapor at about 400�C irrespective of the deposition

method. Often an etch of phosphoric acid (H3PO4) and HNO3 or bromide-methanol is used

to remove CdCl2 salt resulting from the activation step. Also deposition of a thin layer of low


band-gap Sb2Te3 or copper alloy at surface “A” shown in Figure 1.68 helps to form an Ohmic con-

tact on CdTe. Next, the first laser scribing is completed followed by deposition of back metal con-

tact layer (e.g., molybdenum, Mo) using sputtering. In the next step, second laser scribing is

completed. Subsequently, module encapsulation, electrical lead attachment, testing and sorting and

packaging steps are completed. Alternatively, it is possible to sputter deposit back metal contact

first on the glass substrate and follow the reverse sequence of operations, which includes first laser

scribing, absorption layer (CdTe) deposition, buffer layer (CdS) deposition, mechanical scribing,

TCO deposition, mechanical scribing, interconnect formation and encapsulation.

In Chapter 6, a flow chart of CIGS-based cell manufacturing method is presented. Another class

of solar cells called earth abundant solar cells, which use more environment friendly and inexpen-

sive material in thin film solar cells, i.e., Cu-Zn-Sn-chalcogenide based kesterite Cu2ZnSnS4(CZTS) and Cu2ZnSn(S,Se)4 (CZTSSe) thin film solar cells, have also been discussed in section

6.6.2 of Chapter 6 [155�161].

From the above discussion it is clear that sputtering is extensively used for front and back metal

contact formation in thin film solar cells. In addition, absorber, buffer and anti-reflection layers can

also be sputter deposited. Depending on the solar module manufacturers, sputtering methods can

vary. A growing number of sputtering target manufacturers has started to supply such sputtering tar-

gets. Table 1.27 lists various metals and alloys that are sputter deposited for these applications. For

various turnkey lines, for solar module manufacturing, flat rectangular targets as well as cylindrical

targets are used. Metallic cylindrical targets such as Al, Ag, Ti, Ni-7V, Mo, etc., are readily available

in the market and have much higher use (up to 80%) than their flat target counterpart (typically up to

45%). Praxair, W. C. Heraeous, Umicore, Plansee, Bekaert, Soleras and GfE Fremat are some of the

important sputtering target suppliers for PV applications. OEMs that manufacture sputtering tools for

Glass cleaning& inspection

Activation &patterning

Back-contactdeposition

(Sputtering)

PackagingFinal testing &

sortingElectrical lead

attachment

Patterning Moduleencapsulation

CdTe deposition(possible bysputtering)

TCO deposition(Sputtering)

Patterning

CdS deposition

FIGURE 1.71

A representative flow chart for CdTe cell manufacturing.


solar cells include Von Ardenne, Leybold Optic, Applied Materials, Centrotherm Photovoltaic, Roth

and Rau, Hind Highvacuum and so forth. Figure 1.72 shows a Leybold Optic sputtering tool [164]. In

Chapter 6, the metallurgy of such sputtering targets and also thin films are discussed.

In addition to the above applications, there has been steady demand for sputtering materials for

various other applications and some of them have been listed in Table 1.28. A large number of

compound materials that are sputter deposited have been discussed elsewhere [165].

1.8 Sputtering target industryLeading manufacturers of sputtering materials and evaporation sources are based in the United States,

Germany, Japan, Korea and China. These include Praxair, Nikko, Honeywell Electronics, Tosoh SMD,

Table 1.27 Sputtering Materials for Photovoltaics and Solar Cells [162,163]

Cell Type Sputtering Materials

Wafer based Si

a-Si Al, Ag, Mo, Ni-7V,ZnO,ZnO-Al2O3 (0.5�2.0 wt%)

CIGS Mo, In, CuGa, CuIn, ZnO,ZnO-Al2O3 (0.5�2.0 wt%);Zn-Al (0.5�2.0 wt%); ZnAl,CIG

CdTe In2O3-SnO2 (10 wt%) Sn, Mo, Ni-7V

Application Sputtering materials

Transparent conducting oxide ZnO-Al2O3 (2 wt%) In2O3-SnO2 (10 wt%)

Back contact materials Mo, Cr, Al & Al alloys, Ti

PV diode, contact interface andanti-reflection coatings

CuGa, CuGaIn, CuIn, Se alloys, Sb2Te3, ZnO, ZnTe, NaF, Zn(O,S), (Zn, Mg)O, Si, In

FIGURE 1.72

Sputtering tool of Leybold Optic GmbH used for thin film solar cell manufacturing [164].


Global Advanced Metals, W. C. Heraeus, Umicore, Singulus, Plansee, Materion, Kobe Steel, Hitachi

Metals, Matsuda Sangyo, Mitsui Mining and Smelting, Mitsubishi Materials, Sumitomo Metals and

Mining, Sumitomo Chemicals, ULVAC, Bekaert and so forth. In addition, more than 50 small-to-

medium companies also supply a wide variety of specialty sputtering targets. Various data indicate that

the physical vapor deposition market was at $871 million in 2001, $1.8 billion in 2006 and $2.8 billion

in 2007. It was projected that the value of the market would increase to $5.9 billion in 2012. These

figures included materials, equipment and services.

Historically, on a yearly basis, the optical coating industry consumed the largest amount of sput-

tering materials followed by the semiconductor industry, the magnetic and optical storage industry

and the display industry. In recent years, Asian countries such as Taiwan, S. Korea and China have

seen tremendous growth in the semiconductor, display and photovoltaic industries. As described

earlier, display and photovoltaic industries have started using large rectangular and also cylindrical

targets for higher generation displays and large photovoltaic modules. As a result, target manufac-

turers who originally served the semiconductor industry have also been trying to get market shares

of display and photovoltaic industries. It is believed that target material consumption will rise at

slower rate than production of sputtered films because of efficient use of target and thinner films

for certain devices.

Looking at the potential growth of various technologies, e.g., through-silicon-via technologies

in the semiconductor industry, increased demand for transparent conducting oxides in display and

photovoltaic industries and increased demand for back contact materials in the photovoltaic

Table 1.28 Sputtering Materials for Miscellaneous Applications

Application Sputtering Materials

Ohmic contact in GaAs metallization Ge, Au-Ge alloy

Contact in light emitting diode (LED) Au-Sn

Resistors Ni-Cr, Ni-V

Electrode for capacitors in VLSI Pt, Ru, Ir

Thin film capacitor PbTiO, BaTiO, BaSrTiO, SrTiO, PbLaZrTiO

Insulator and protective film Al2O3, SiO2

Piezoelectric film LiNbO3

Magnetic bubble memory device Yttrium aluminum oxide (YAG), Yttrium iron oxide (YIG),Gd3Ga5O12, Gd-Co

Magneto-optical recording GdFeCo, TbFeCo, TbFeCoSi, NdFeCo, etc.

Reflective coating Al-Cr, Al-V, Al-Ti

Antireflection coating CeO2

Thermionic emitter LaB6

Plasma display Mg, MgO

Phosphorescent coating on specialcurrency paper

YVO3-Eu2O3

Mask material MoSix, Cr, TaB, TaGe

High temperature superconductor Cu3Ba2YO7

851.8 Sputtering target industry

industry, it is expected that the demand for materials such as copper, titanium, tantalum, aluminum,

tungsten-titanium, nickel�vanadium and transparent conducting oxides will increase. Target manu-

facturers who have access to inexpensive raw materials, efficient supply chains, low cost of

manufacturing and satisfactory quality control will dominate these new markets. Other factors that

would determine profitability are inexpensive recycling capability of spent targets and also bonding

technology for large cylindrical targets. In addition, material innovation for technologies such as

barriers for 15 nm or smaller technology nodes in semiconductors, light emitting diodes,

micro-electro mechanical systems and various sensors will also drive the growth of the sputtering

industry market.

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