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Industrial Motor Drive on a Single SoC FPGALower Cost, Higher Performance, and Faster Design

Drives and motors are an integral part o industrial equipment rom packaging,robotics, computer numerical control (CNC), machine tools, industrial pumps,and ans. Designing next-generation drive systems to lower operating costsrequires complex control algorithms at very low latencies as well as a fexible

plat orm to support changing needs and the ability to design multiple-axissystems.

Traditional drive systems based on ASICs, digital signal processors (DSPs), andmicrocontroller units lack the per ormance and fexibility to address these needs.Alteras amily o SoC FPGAs integrates an ARM-based processor subsystemwith an FPGA on a single monolithic device (Figure 1). Our SoC FPGAs eatureindustry-leading variable-precision DSP blocks and provide the ideal drive-on-a-chip plat orm or DSP processing, Industrial Ethernet, unctional sa ety, and I/Oexpansion.

Lower Costs Through Design Integration Reduce total cost of ownership with our drive-on-a-

chip system:- Combines a Cyclone V FPGA with a high-

performance, dual-core ARM processor subsystem,allowing you to tightly couple the processorsubsystem with hardware accelerators for motorcontrol

- Extend functionality by integrating industrialnetworking, encoder interfaces, I/O, analoginterfaces, and logic

Save board space and reduce power consumption withfewer required components and the ability to supportmulti-axis control

Adapt quickly to changing market requirements withless design work through our support for leadingindustrial Ethernet protocols and I/O standards

Reduce Time To Market Save development time and lower risk for designing

product variants by reusing intellectual property (IP)cores and leveraging the ARM ecosystem

Reduce your safety certication time by up to 24months with our TV Rheinland-qualied IEC 61508Functional Safety FPGA data package

Meeting Higher-Performance Drive Requirements Implement control-loop algorithm latencies of less

than 5 s using our variable-precision DSP blocks,multipliers, support for oating point, and arithmeticDSP functions

Optimize your design by partitioning between softwareand hardware elements using our model-based designmethodology with system-level design tools

Figure 1: Drive on a Chip: Cyclone V SoC FPGAs Include ARMProcessor, Motor Control Algorithm, I/O Logic, Industrial Ethernet

Protocols, and Safety Elements

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Altera Corporation101 Innovation DriveSan Jose, CA 95134USATelephone: ( 408) 544-7000www.altera.com

Altera European HeadquartersHolmers Farm WayHigh WycombeBuckinghamshireHP12 4XFUnited KingdomTelephone: (44) 1494 602000

Altera Japan Ltd.Shinjuku i-Land Tower 32F6-5-1, Nishi-ShinjukuShinjuku-ku, Tokyo 163-1332JapanTelephone: (81) 3 3340 9480www.altera.co.jp

Altera International Ltd.Unit 11-18, 9/FMillennium City 1, Tower 1388 Kwun Tong RoadKwun TongKowloon, Hong KongTelephone: (852) 2945 7000

2011 Altera Corporation. All rig hts reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks o AlteraCorporation and registered in the U.S. Patent and Trademark O ce and in other countries. All other words and logos identi ed as trademarks or service marks are the property o theirrespective holders as described at www.altera.com/legal.PDF; October 2011 SS-1033-1.0

System-Level Design Flow Tailored for DSP PerformanceTo optimize your motor control algorithms and designs, you will need versatile tools and apractical design methodology. Figure 2 shows a tool fow that helps model and simulate thesystem, implement complex algorithms with low latency, integrate the hardware/so waresystem, and ne-tune the per ormance to the exact needs o the motor drive.

You also can take advantage o easy-to-use development tools, such as Quartus II designso ware, and system integration tools, such as Qsys and DSP Builder or DSP optimization.With support or model-based environments such as Simulink/MATLAB to model thealgorithm, you can integrate a motor control system directly to the DSP Builder tool or themost optimized drive designs. Whats more, you can use the amiliar tool fow and resourceso the rich ARM ecosystem to reduce development time and take advantage o legacy code.

Altera SoC FPGA Portfolio

Our SoC FPGAs join a diverse amily o 28-nm Cyclone V FPGAs that are tailored to yourdesign requirements. Cyclone V FPGAs provide the industrys lowest system cost and power,along with multiport memory support such as DDR3/LPDDR, integrated transceiver options, variable-precision DSP blocks, and per ormance levels that make the device amily ideal ordi erentiating your high-volume applications. Youll also get up to 40 percent lower totalpower versus the previous generation and e cient logic integration capabilities.

Figure 2: System-Level Optimized Design Flow for an SoC FPGA Drive System

ModelSystem

Alg ori thmin Software

Optimize Algorithmin Hardware

Simulink /MATLAB

Integrate inHardware

CompileDesign

Integrate with App lic atio n Sof twar e

SystemPlacement

Software

Quartus II

ARM or Nios IISoftware Tools

SoC FPGA

Algorithmin C

AlgorithmUsing

DSP Builder

Qsys SystemIntegration

Want to Dig Deeper?For more in ormation aboutAlteras SoC FPGAs or motorcontrol applications, contact yourlocal Altera sales representative orFAE, or visit www.altera.com/industrial .