sv1d direct-attach serdes module

SV1DDirect-AttachSerDesModule

DataSheet

TableofContents

1

TableofContents

TableofContents.........................................................................................................................................1

ListofFigures...............................................................................................................................................2

ListofTables.................................................................................................................................................2

Introduction.................................................................................................................................................3

Overview..................................................................................................................................................3

KeyBenefits..............................................................................................................................................3

Applications..............................................................................................................................................3

Features........................................................................................................................................................5

Multi-LaneLoopback................................................................................................................................5

Multiple-SourceJitterInjection................................................................................................................5

Pre-EmphasisGeneration.........................................................................................................................7

ProgrammableSSCGenerationandFrequencySynthesis.......................................................................8

Per-LaneClockRecoveryandUniqueDual-PathArchitecture.................................................................8

AuxiliaryControlPort...............................................................................................................................9

Analysis...................................................................................................................................................10

Automation............................................................................................................................................11

PhysicalDescription...................................................................................................................................12

ElectricalDescription..................................................................................................................................14

Specifications.............................................................................................................................................16

TableofContents

2

ListofFigures

Figure1Illustrationofloopbackapplications............................................................................................5Figure2Illustrationofcalibratedjitterwaveform....................................................................................6Figure3Illustrationofjittertolerancecurve.............................................................................................6Figure4Illustrationofpre-emphasisdesign.............................................................................................7Figure5Illustrationofmultiplewaveformshapesthatcanbesynthesizedusingthepre-emphasisfunctionoftheSV1D....................................................................................................................................7Figure6ProgrammableSSCgeneration....................................................................................................8Figure7Per-laneclockrecoveryanddual-patharchitecture....................................................................9Figure8Samplingofanalysisandreportwindows.................................................................................10Figure9ScreencaptureofIntrospectESPuserenvironment..................................................................11Figure10(a)MotherboardlayoutrequirementsdepictingtheconnectorandmountingholefootprintsoftheSV1D(pinkoutline)(b)TopviewoftheSV1Badaptorboardlocation(brownoutline)relativetotheSV1D.....................................................................................................................................................12Figure11TopviewandsideprofileoftheSV1MshowingitsreliefandthetotalheightwiththeincludedheatsinkInsetfiguredepictsthesideviewoftheassembledSV1B,SV1Dandthemotherboard....................................................................................................................................................................13

ListofTables

Table1MotherboardJ1connectorQSH-020-01-L-D-DP-Apin-out........................................................14Table2MotherboardJ2connectorLPAF-10-03.5-L-06-2-K-TRpin-out..................................................14Table3MotherboardJ4connectorQMS-052-09.75-SL-D-Apin-out......................................................15Table4GeneralSpecifications.................................................................................................................16Table5TransmitterCharacteristics.........................................................................................................17Table6ReceiverCharacteristics..............................................................................................................18Table7ClockingCharacteristics..............................................................................................................19Table8PatternHandlingCharacteristics................................................................................................20Table9MeasurementandThroughputCharacteristics..........................................................................21Table10InstructionSequenceCache......................................................................................................21Table11DUTControlCapabilities...........................................................................................................22

Introduction

3

Introduction

OverviewTheSV1DDirect-AttachSerDesModuleisaversatile,high-performanceinstrumentthatcreatesanewcategoryoftoolforhigh-speeddigitalproductengineeringteams.Itintegratesmultipletechnologiesinordertoenabletheself-containedtestandmeasurementofcomplexSerDesinterfacessuchasPCIExpressGen3,MIPIM-PHY,Thunderbolt,orUSB3.Coupledwithaseamless,easy-to-usedevelopmentenvironment,thistoolenablesproductengineerswithwidelyvaryingskillstoefficientlyworkwithanddevelopSerDesverificationalgorithms.TheSV1Dmountsdirectlyonanapplicationortestboardwithoutcables.Itcontains8independentstimulusgenerationports,8independentcaptureandmeasurementportsandvariousclocking,synchronizationandlane-expansioncapabilities.Ithasbeendesignedspecificallytoaddressthegrowingneedofaparallel,system-orientedtestmethodologywhileofferingworld-classsignal-integrityfeaturessuchasjitterinjectionandjittermeasurement.

Withasmallfootprint,anextensivesignal-integrityfeatureset,andanexceptionallypowerfulsoftwaredevelopmentenvironment,theSV1Disnotonlysuitableforsignal-integrityverificationengineersthatperformtraditionalcharacterizationtasks,butitisalsoidealforFPGAdevelopersandsoftwaredeveloperswhoneedrapidturnaroundsignalverificationtoolsorhardware-softwareinteroperabilityconfirmationtools.TheSV1Dintegratesstateoftheartfunctionssuchasdigitaldatacapture,biterrorratemeasurement,clockrecovery,jitterdecompositionandjittergeneration.

KeyBenefits• Trueparallelbit-error-ratemeasurementacross8lanes• Fully-synthesizedintegratedjitterinjectiononalllanes• Fully-automatedintegratedjittertestingonalllanes• Optimizedpatterngeneratorrise-timeforreceiverstresstestapplications• Flexiblepre-emphasisandequalization• Flexibleloopbacksupportperlane• Hardwareclockrecoveryperlane• StateoftheartprogrammingenvironmentbasedonthehighlyintuitivePython

language• IntegrateddevicecontrolthroughSPI,I2C,orJTAG• Reconfigurable,protocolcustomization(onrequest)

Applications

Introduction

4

ParallelPHYvalidationofserialbusstandardssuchas:

• PCIExpress(PCIe) • HDMI• UHS-2 • Thunderbolt• MIPIM-PHY • XAUI• CPRI • JESD204B• USB • SATA

Interfacetestofelectrical/opticalmediasuchas:

• Backplane• Cable• CFPMSA,SFPMSA,SFP+MSA

Plug-and-playsystem-levelvalidationsuchas:

• PCIExpress• DisplayPortsink/source• MIPIM-PHY

Timingverification:

• PLLtransferfunctionmeasurement• Clockrecoverybandwidthverification• Frequencyppmoffsetcharacterization

Mixed-technologyapplications:

• High-speedADCandDAC(JESD204)datacaptureand/orsynthesis• FPGA-basedsystemdevelopment• Channelanddeviceemulation

Features

5

Features

Multi-LaneLoopbackTheSV1Distheonlybench-toptoolthatoffersinstrument-gradeloopbackcapabilityonalldifferentiallanes.TheloopbackcapabilityoftheSV1Dincludes:

• RetimingofdataforthepurposeofdecouplingDUTreceiverperformancefromDUTtransmitterperformance

• Arbitraryjitterorvoltageswingcontrolonloopbackdata

Figure1showstwocommonloopbackconfigurationsthatcanbeusedwiththeSV1D.Inthefirstconfiguration,asingleDUT’stransmitterandreceiverchannelsareconnectedtogetherthroughtheSV1D.Inthesecondconfiguration,arbitrarypatterntestingcanbeperformedonanend-to-endcommunicationslink.TheSV1Disusedtopassdatathroughfromatrafficgenerator(suchasanend-pointonarealsystemboard)totheDUTwhilestressingtheDUTreceiverwithjitter,skew,orvoltageswing.

(a) (b)

Figure1Illustrationofloopbackapplications

Multiple-SourceJitterInjectionTheSV1Discapableofgeneratingcalibratedjitterstressonanydatapatternandanyoutputlaneconfiguration.Sinusoidaljitterinjectioniscalibratedinthetimeandfrequencydomaininordertogeneratehigh-puritystimulussignalsasshowninFigure2.

Features

6

Figure2Illustrationofcalibratedjitterwaveform

ThejitterinjectionfeatureistypicallyexploitedtoperformautomatedjittertolerancetestingasshownintheexampleinFigure3.AsisthecaseforotherfeaturesintheSV1DDirect-AttachSerDesModule,jittertolerancetestingisconductedinparallelacrossalllanes.Foradvancedapplications,theSV1DalsoincludesRJinjectionandathird-sourcearbitrarywaveformjittersynthesizer.

Figure3Illustrationofjittertolerancecurve

Features

7

Pre-EmphasisGenerationConventionallyofferedasaseparateinstrument,per-lanepre-emphasiscontrolisintegratedonthe8-laneSV1Dtester.Theusercanindividuallysetthetransmitterpre-emphasisusingabuilt-inTapstructure.Pre-emphasisallowstheusertooptimizesignalcharacteristicsattheDUTinputpins.

EachtransmitterintheSV1Dimplementsadiscrete-timelinearequalizeraspartofthedrivercircuit.AnillustrationofsuchequalizerisshowninFigure4,andsamplesynthesizedwaveformshapesareshowninFigure5.

Figure4Illustrationofpre-emphasisdesign

Figure5Illustrationofmultiplewaveformshapesthatcanbesynthesizedusingthepre-emphasisfunctionoftheSV1D

Features

8

ProgrammableSSCGenerationandFrequencySynthesisTheSV1DincorporatesprecisionfrequencysynthesistechnologythatallowsforthegenerationofprogrammableSSCwaveformsatanydatarate.TheSSCwaveformsaresuperimposedonthepatterngeneratoroutputs,andtheycoexistwithotherjitterinjectionsourcesoftheSV1D.Thus,atrulycompletejittercocktailcanbeproducedforthemostthoroughreceivervalidation.Figure6illustratestheSSCcapabilityoftheSV1D.Inthefigure,theSV1Disprogrammedtosynthesizefourslightlydifferentmodulationfrequenciesshowcasingtheprecisionprogrammabilityofthetool.

Figure6ProgrammableSSCgeneration

Per-LaneClockRecoveryandUniqueDual-PathArchitectureLikepre-emphasis,conventionaltoolsoftenrequireseparateclockrecoveryinstrumentation.IntheSV1D,eachreceiverhasitsownembeddedanalogclockrecoverycircuit.Additionally,theclockrecoveryismonolithicallyintegrateddirectlyinsidethereceiver’shigh-speedsampler,thusofferingthelowestpossiblesamplinglatencyinatestandmeasurementinstrument.Theuserdoesnothavetomakespecialconnectionsorcarefullymatchcablelengths.ThemonolithicnatureoftheSV1Dclockrecoveryhelpsachievewidetrackingbandwidthformeasuringsignalsthatpossessspread-spectrumclockingorveryhighamplitudewander.Figure7showsablockdiagramoftheclockrecoverycapabilityinsidetheSV1DDirect-AttachSerDesModule.

AlsoshowninFigure7isthedual-pathreceiverarchitectureoftheSV1D.ThisuniquearchitectureallowstheSV1Dtooperateasbothadigitalcapture/analysisinstrumentandananalogmeasurementinstrument.AfeaturerichclockmanagementsystemallowsforcustomizationoftheSV1Dtospecificcustomerrequirements.

Features

9

Figure7Per-laneclockrecoveryanddual-patharchitecture

AuxiliaryControlPortTheSV1Dincludesalow-speedauxiliarycontrolport.ItenablescontrollingDUTregistersthroughJTAG,I2C,orSPI.Additionally,theportincludesreconfigurabletriggerandflagcapabilitiesforsynchronizingwithexternaltoolsorevents.

Features

10

AnalysisTheSV1DinstrumenthasanindependentBitErrorRateTester(BERT)foreachofitsinputchannels.EachBERTcomparesrecovered(retimed)datafromasingleinputchannelagainstaspecifieddatapatternandreportsthebiterrorcount.

Apartfromerrorcounting,theinstrumentoffersawiderangeofmeasurementandanalysisfeaturesincluding:

• Jitterseparation• Eyemasktesting• Voltagelevel,pre-emphasislevel,andsignalparametermeasurement• FrequencymeasurementandSSCprofileextraction

Figure8illustratesafewoftheanalysisandreportingfeaturesoftheSV1D.Startingfromthetopleftandmovinginaclock-wisemanner,thefigureillustratesbathtubacquisitionandanalysis,waveformcapture,rawdataviewing,andeyediagramplotting.Asalways,theseanalysisoptionsareexecutedinparallelonallactivatedlanes.

Figure8Samplingofanalysisandreportwindows

Features

11

AutomationTheSV1DisoperatedusingtheawardwinningIntrospectESPSoftware.Itfeaturesacomprehensivescriptinglanguagewithanintuitivecomponent-baseddesignasshowninthescreenshotinFigure9(a).Component-baseddesignisIntrospectESP’swayoforganizingtheflexibilityoftheinstrumentinamannerthatallowsforeasyprogramdevelopment.Ithighlightstotheuseronlytheparametersthatareneededforanygiventask,thusallowingprogramexecutioninamatterofminutes.Forfurtherhelp,theSV1DfeaturesautomaticcodegenerationforcommontaskssuchasEyeDiagramorBathtubCurvegenerationasshowninFigure9(b).

(a) (b)

Figure9ScreencaptureofIntrospectESPuserenvironment.

PhysicalDescription

12

(b)

measurementsinmilsunlessspecifiedotherwise

PhysicalDescription

TheSV1DissuppliedwithaheatsinkandtheSV1Badaptorboard.Themotherboardanditsconnectors,standoffsandscrewsaretobesourcedbyusers.TheSV1Dfeaturesahigh-speedlowprofile6x10-pinanda40-pin(in20pairs)Q-Strip®connectorsonthebottomsideprovidingclock,data,SPI,JTAGcontrolconnectionstothecarriermotherboard.AconnectoronuppersideprovidesGPIOconnectionstothemotherboardthroughtheincludedSV1Badaptorboard.

Figure10(a)illustratesthe3connectorand4mountingholelocationsrequiredonthemotherboard.Measurementsareinmilunlessstatedotherwise.TheSV1DandSV1Bboardsrequire2mountingholeseachforphysicalsupport.ThemotherboarddevicesshouldbekeptawayfromthelocationsoccupiedbySV1DandSV1B,asshowninFigure10(b).

Figure10(a)MotherboardlayoutrequirementsdepictingtheconnectorandmountingholefootprintsoftheSV1D(pinkoutline)

(b)TopviewoftheSV1Badaptorboardlocation(brownoutline)relativetotheSV1D

(a)

641

1693

1307

1035

QMS-05

2-09

.75-SL-D-A

PhysicalDescription

13

ThesideprofileoftheassembledboardsisshowninFigure11,wheretheSV1Dismountedonthemotherboardfirst,andthentheSV1Bboardmountsontopofit.PleasetakenoteofthelengthofthestandoffsneededtomaintainadequateverticalclearanceandtightconnectionsamongtheSV1D,SV1Bandthemotherboard.Thestandoffsshouldbetightenedbyscrewsafterassembly.

Figure11TopviewandsideprofileoftheSV1MshowingitsreliefandthetotalheightwiththeincludedheatsinkInsetfiguredepictsthesideviewoftheassembledSV1B,SV1Dandthemotherboard

ElectricalDescription

14


Thefollowingtablesdescribesthepinoutinformationofthe2Q-stripconnectorsontheSV1D,andtheIOconnectoronthemotherboard.Whendesigningtheinterfacelogic,pleaseensurenottodriveanyI/OpinsontheSV1Duntilthepowerrailshavebeencompletelypoweredon.

Table1MotherboardJ1connectorQSH-020-01-L-D-DP-Apin-outSignal PinLocation Description VoltageLevel

12.0V 10,12,14,16,18,20,22,24,26,28,30,32,34,36,38,40 InputPower(12.0V+/-5%atALLtimes)(Currentsourceminimum2A,applicationmaydemandmore)

12.0V

GND 0,11,13,15,17,19,21,23,25,27,29,31,33,35,37,39 Ground GND

TMS 9 JTAGTMS|DirectconnectiontoFPGA

2.5V

SCLK 1 SV1DslaveSPIcommunicationportclockSSN 3 SV1DslaveSPIcommunicationportchipselect|ActivelowMOSI 5 SV1DslaveSPIcommunicationportdatafrommasterMISO 7 SV1DslaveSPIcommunicationportdatatomaster|OpendrainoutputTRIG1 2 Multi-purposeTriggerinput|NegativeedgetriggeredTRIG2 4FLAG1 6 Multi-purposeFlagoutput

Multi-purposeFlagoutputFLAG2 8

Table2MotherboardJ2connectorLPAF-10-03.5-L-06-2-K-TRpin-out

Signal PinLocation Description VoltageLevelREFCLK_0_P,REFCLK_0_N

F02,E02 ExternalReferenceClock|LVDS|ACCoupled

GXB

RefertoconnectiondiagramsTX8_P,TX8_N B03,A03

GXBTransmitLink|DCcoupled|Programmablevoltageswing

TX7_P,TX7_N C04,B04TX6_P,TX6_N B05,A05TX5_P,TX5_N C06,B06TX4_P,TX4_N B07,A07TX3_P,TX3_N C08,B08TX2_P,TX2_N B09,A09TX1_P,TX1_N C10,B10RX8_P,RX8_N E03,D03

GXBReceiveLink|DCcoupled

RX7_P,RX7_N F04,E04RX6_P,RX6_N E05,D05RX5_P,RX5_N F06,E06RX4_P,RX4_N E07,D07RX3_P,RX3_N F08,E08RX2_P,RX2_N E09,D09RX1_P,RX1_N E10,F10

SV1_RST# B02 ResistordivideronSV1makes3.3VSV1_RST#signal2.5Vcompatible|Activelow|Mustbeactivelydrivenorpulledupwitharesistorsmallerthan1Kohms 3.3V

REFCLK_1_P B01 ExternalReferenceClock|Expectedtobe100MHzLVDS_2.5Vzczxcv|)Motherboarddeterminesvalue

2.5VLVDSREFCLK_1_N A01 Refertoconnectiondiagrams 2.5GLVDS

TDO C02 JTAGTDO|DirectconnectiontoFPGA2.5VTDI E01 JTAGTDI|DirectconnectiontoFPGA

TCK D01 JTAGTCK|DirectconnectiontoFPGA

GND

A02,A04,A06,A08,A10,C01,C03,C05,C07,C09,D02,D04,D06,D08,D10,F01,F03,F05,F07,F09

Ground GND


15

Table3MotherboardJ4connectorQMS-052-09.75-SL-D-Apin-out

Signal PinLocation Description VoltageLevelPAIR00_P,PAIR00_N 1,2 GenericIO,ProgrammablewithCustomFirmware 2.5VCMOS

12.0V 3,4 OutputPower(12.0V+/-5%) 12.0VPAIR04_P,PAIR04_N 5,6 LED:LockStatus,CmdProcReady 2.5VPAIR02_P,PAIR02_N 13,14 LED:LockStatus,CmdProcReady 2.5VPAIR08_P,PAIR08_N 9,10 GenericIO,ProgrammablewithCustomFirmware

2.5VCMOS

PAIR06_P,PAIR06_N 17,18PAIR01_P,PAIR01_N 21,22 LED:UserLEDmirror,LED:LockStatusmirrorPAIR05_P,PAIR05_N 25,26

GenericIO,ProgrammablewithCustomFirmwarePAIR09_P,PAIR09_N 29,30PAIR03_P,PAIR03_N 33,34PAIR07_P,PAIR07_N 37,38

GND

7,8,11,12,15,16,19,20,23,24,27,28,31,32,35,36,39,40,43,44,47,48,51,52,55,56,59,60,63,64,67,68,71,72,75,76,79,80,83,84,87,88,91,92,95,96,99,100,103,104,107,108,

111,112,115,116,119,120,123,124,127,128,131,132,135,136,139,140,143,144,147,148,151,152,155,156,159,160,163,164,167,168,171,172,175,

176,179,180,183,184,187,188191,192,195,196,199,200

Ground GND

PAIR10_P,PAIR10_N 41,42

GenericIO,ProgrammablewithCustomFirmware

2.5VCMOS

PAIR14_P,PAIR14_N 45,46PAIR18_P,PAIR18_N 49,50PAIR12_P,PAIR12_N 53,54PAIR16_P,PAIR16_N 57,58PAIR11_P,PAIR11_N 61,62PAIR15_P,PAIR15_N 65,66PAIR19_P,PAIR19_N 69,70PAIR13_P,PAIR13_N 73,74PAIR17_P,PAIR17_N 77,78PAIR20_P,PAIR20_N 81,82PAIR24_P,PAIR24_N 85,86 DUTreset(activelow,drivenloworhigh-z,pull-up

required)PAIR28_P,PAIR28_N 89,90

GenericIO,ProgrammablewithCustomFirmware

PAIR22_P,PAIR22_N 93,94PAIR26_P,PAIR26_N 97,98PAIR21_P,PAIR21_N 101,102PAIR25_P,PAIR25_N 105,106PAIR29_P,PAIR29_N 109,110PAIR23_P,PAIR23_N 113,114PAIR27_P,PAIR27_N 117,118PAIR30_P,PAIR30_N 121,122PAIR45_P,PAIR45_N 125,126PAIR34_P,PAIR34_N 129,130

MGT_RX0_P,MGT_RX0_N 133,134 Unusedinput,tietoGround



MGT_RX1_P,MGT_RX1_N 153,154 Unusedinput,tietoGround



MGT_TX0_P,MGT_TX0_N

173,174 Unusedoutput,leaveunconnected



MGT_TX1_P,MGT_TX1_N 193,194 Unusedoutput,leaveunconnected

PAIR41_P,PAIR41_N 197,198 GenericIO,ProgrammablewithCustomFirmware

Specifications

16

Specifications

Table4GeneralSpecificationsParameter Value Units DescriptionandConditions

Ports NumberofDifferentialTransmitters 8 NumberofDifferentialReceivers 8 NumberofDedicatedClockOutputs 2 Individuallysynthesizedfrequencyandoutputformat. NumberofDedicatedClockInputs 1 UsedasexternalReferenceClockinput. NumberofTriggerInputPins Multiple Consultusermanualforincludedcapability.Contact

factoryforcustomization.

NumberofFlagOutputPins Multiple Consultusermanualforincludedcapability.Contactfactoryforcustomization.

DataRatesandFrequencies MinimumProgrammableDataRate 312.5 Mbps Contactfactoryforextensiontolowerdatarates. MaximumProgrammableDataRate 14 Gbps MaximumDataRatePurchase

Options4 Gbps

8.5 Gbps 12.5 Gbps 14 Gbps DataRateFieldUpgrade 4-12.5 Gbps Contactfactoryfordetails. FrequencyResolutionof

ProgrammedDataRate1 kHz Finerresolutionispossible.Contactfactoryfor

customization.

MinimumExternalInputClockFrequency

25 MHz

MaximumExternalInputClockFrequency

250 MHz

SupportedExternalInputClockI/OStandards

LVDS(typical400mVppinput)LVPECL(typical800mVppinput)

Specifications

17

Table5TransmitterCharacteristics

Parameter Value Units DescriptionandConditionsOutputCoupling DCcommonmodevoltage 750 mV typical

(differentoffsetsarefirmwareprogrammable) ACOutputDifferentialImpedance 100 Ohm typicalVoltagePerformance MinimumDifferentialVoltageSwing 20 mV MaximumDifferentialVoltageSwing 1000

800

mVppmVpp

312.5Mbpsto5Gbps,50ohmACcoupledtermination.5Gbpsto12.5Gbps,50ohmACcoupledtermination.

DifferentialVoltageSwingResolution 20 mV AccuracyofDifferentialVoltage

Swinglargerof:+/-10%ofprogrammedvalue,and+/-

10mV

%,mV

RiseandFallTime 50 ps Typical,500mVppsignal,20-80%,50ohmACcoupledtermination.

75 ps Typical,500mVppsignal,10%-90%,50ohmACcoupledtermination.

Pre-emphasisPerformance Pre-EmphasisPre-TapRange -4to+4 dB Bothhigh-passandlow-passfunctionsareavailable.This

isthesmallestachievablerangebasedonworst-caseconditions.Typicaloperatingconditionsresultinwiderpre-emphasisrange.

Pre-EmphasisPre-TapResolution Range/32 dB Pre-EmphasisPost1-TapRange 0to6 dB Onlyhigh-passfunctionisavailable.Thisisthesmallest

achievablerangebasedonworst-caseconditions.Typicaloperatingconditionsresultinwiderpre-emphasisrange.

Pre-EmphasisPost1-TapResolution Range/32 dB Pre-EmphasisPost2-TapRange -4to+4 dB Bothhigh-passandlow-passfunctionsareavailable.This

isthesmallestachievablerangebasedonworst-caseconditions.Typicaloperatingconditionsresultinwiderpre-emphasisrange.

Pre-EmphasisPost2-TapResolution Range/32 dB JitterPerformance RandomJitterNoiseFloor 1000 fs Basedonmeasurementwithhigh-bandwidthscopeand

withfirst-orderclockrecovery.

MinimumFrequencyofInjectedDeterministicJitter

0.1 kHz Contactfactoryforfurthercustomization.

MaximumFrequencyofInjectedDeterministicJitter

80 MHz

FrequencyResolutionofInjectedDeterministicJitter

0.1 kHz Contactfactoryforfurthercustomization.

MaximumPeak-to-PeakInjectedDeterministicJitter

1400 ps Thisspecificationisseparatefromlow-frequencywandergeneratorandSSCgenerator.

MagnitudeResolutionofInjectedDeterministicJitter

500 fs Jitterinjectionisbasedonmulti-resolutionsynthesizer,sothisnumberisaneffectiveresolution.Internalsynthesizerresolutionisdefinedinequivalentnumberofbits.

InjectedDeterministicJitterSetting Per-bank Commonacrossallchannelswithinabank. MaximumRMSRandomJitter

Injection0.1 UI

Specifications

18

MagnitudeResolutionofInjectedJitter

0.1 ps

AccuracyofInjectedJitterMagnitude largerof:+/-10%ofprogrammed

value,and+/-10ps

%,ps

InjectedRandomJitterSetting Common Commonacrossallchannelswithinabank.Transmitter-to-TransmitterSkewPerformance LanetoLaneInteger-UIMinimum

Skew-20 UI

LanetoLaneInteger-UIMaximumSkew

20 UI

EffectofSkewAdjustmentonJitterInjection

None

LanetoLaneSkew +/-30 ps

Table6ReceiverCharacteristicsParameter Value Units DescriptionandConditions

InputCoupling ACInputDifferentialImpedance 100 Ohm ACPerformance MinimumDetectableDifferential

Voltage25 mV

MaximumAllowableDifferentialVoltage

2000 mV

MinimumProgrammableComparatorThresholdVoltage

-550 mV

MaximumProgrammableComparatorThresholdVoltage

+550 mV

DifferentialComparatorThresholdVoltageResolution

10 mV

DifferentialComparatorThresholdVoltageAccuracy

largerof:+/-10%ofprogrammedvalue,and+/-

10mV

%,mV

MeasuredEyeWidthAccuracy 10%

15%

25%

Maximumerror,312.5Mbps–2.0Gbps,200mVppminimuminputamplitudeMaximumerror,2.0Mbps-5Gbps,200mVppminimuminputamplitudeMaximumerror,5Gbps–12.5Gbps,200mVppminimuminputamplitude

ResolutionEnhancement&Equalization DCGain 0 dB 2 dB 4 dB 6 dB 8 dB CTLEMaximumGain 16 dB CTLEResolution 1 dB DCGainControl Per-receiver EqualizationControl Per-receiver

Specifications

19

JitterPerformance InputJitterNoiseFloorinSystem

ReferenceMode25 ps

InputJitterNoiseFloorinExtractedClockMode

10 ps

TimingGeneratorPerformance ResolutionatMaximumDataRate 31.25 mUI Resolution(asapercentageofUI)improvesforlower

datarate.Contactfactoryfordetails.

DifferentialNon-LinearityError +/-0.5 LSB IntegralNon-LinearityError +/-5 ps Range Unlimited Skew LanetoLaneSkewMeasurement

Accuracy+/-10 ps

Table7ClockingCharacteristicsParameter Value Units DescriptionandConditions

InternalTimeBase NumberofInternalFrequency

References2 Relevantforfuturecustomization.

EmbeddedClockApplications TransmitTimingModes System Extracted Clockcanbeextractedfromoneofthedatareceiver

channelsinordertodrivealltransmitterchannels.

ReceiveTimingModes System Extracted Allchannelshaveclockrecoveryforextractedmode

operation.

LanetoLaneTrackingBandwidth 4 MHz Single-LaneCDRTrackingBandwidth 3-12 MHz

ForwardedClockApplications TransmitTimingModes System Forwarded Channel1actsasforwardedclockforsamplers. ReceiveTimingModes System Forwarded Channel1actsasforwardedclockforsamplers. ClockTrackingBandwidth 4 MHz Secondordercriticallydampedresponse.SpreadSpectrumSupport ReceiveLanesTrackSSCData Yes Requiresoperationinextractedclockmode. TransmitLanesGenerateSSCData Yes Consultfactoryforavailability. MinimumSpread 0.1 % MaximumSpread 2 % SpreadProgrammingResolution 0.01 % MinimumSpreadingFrequency 31.5 kHz MaximumSpreadingFrequency 63 kHz

Specifications

20

Table8PatternHandlingCharacteristicsParameter Value Units DescriptionandConditions

Loopback RxtoTxLoopbackCapability Perchannel LanetoLaneLatencyMismatch 0 UI PresetPatterns StandardBuilt-InPatterns AllZeros D21.5 K28.5 K28.7 DIV.16 DIV.20 DIV.40 DIV.50 PRBS.5 PRBS.7 PRBS.9 PRBS.11 PRBS.13 PRBS.15 PRBS.21 PRBS.23 PRBS.31 PatternChoiceperTransmitChannel Per-transmitter PatternChoiceperReceiveChannel Per-receiver BERTComparisonMode Automaticseed

generationforPRBS

AutomaticallyalignstoPRBSdatapatterns.

UserProgrammablePatternMemory TotalAvailableMemory 2 GByte Memoryallocationiscustomizable.Contactfactory. IndividualForcePattern Per-transmitter IndividualExpectedPattern Per-receiver MinimumPatternSegmentSize 512 bits MaximumPatternSegmentSize 65536 bits TotalMemorySpaceforTransmitters 1 Mbits Memoryallocationiscustomizable.Contactfactory. TotalExpectedMemorySpacefor

Receivers1 Mbits Memoryallocationiscustomizable.Contactfactory.

PatternSequencing SequenceControl Loopinfinite Looponcount Playtoend NumberofSequencerSlotsper

PatternGenerator4 Thisreferstothenumberofsequencerslotsthatcan

operateatanygiventime.Theinstrumenthasstoragespacefor16differentsequencerprograms.

MaximumLoopCountperSequencerSlot

216-1

AdditionalPatternCharacteristics PatternSwitching Waittoendof

segment WhensourcingPRBSpatterns,thisoptiondoesnotexist.

Immediate RawDataCaptureLength 8192 bits

Specifications

21

Table9MeasurementandThroughputCharacteristics

Parameter Value Units DescriptionandConditionsBERTSync AlignmentModes Pattern Modulecanaligntoanyuserpatternorpresetpattern. PRBS MinimumSYNCErrorThreshold 3 bits MaximumSYNCErrorThreshold 232-1 bits MinimumSYNCSampleCount 1024 bits MaximumSYNCSampleCount 232 bits

SYNCTime 20 ms AssumesaPRBS7patternthatisstoredinauserpatternsegmentandworstcasemisalignmentbetweenDUTpatternandexpectedpattern;datarateis3.25Gbps.

BERT ErrorCounterSize 32 bits SamplecountsintheBERTareprogrammedin

incrementsof32bits.

MaximumSingle-ShotDuration 232-1 bits Repeatmodeisavailabletocontinuouslycountoverlongerdurations.

ContinuousDuration Indefinite Alignment CDRLockTime 5 us Self-AlignmentTime 50 ms

Table10InstructionSequenceCacheParameter Value Units DescriptionandConditions

SimpleInstructionCache InstructionLearnmodeInstruction Start Stop Replay AdvancedInstructionCache LocalInstructionStorage 1MInstructions InstructionSequenceSegments 1000

Specifications

22

Table11DUTControlCapabilitiesParameter Value Units DescriptionandConditions

DUTIEEE-1149-1(JTAG)Port(Option) JTAG-PortTransmitSignals TCK TRST TDI JTAG-PortReceiveSignals TDO JTAG-PortTransmitVoltageSwing

(Fixed)0to2.5 V

JTAG-PortReceiveMaxVoltageSwing 0to2.5 V TDIBitMemory 4k TDOBitMemory 4k DUTSPIPort(Option) SPISignals SCLK SSN MISO MOSI VoltageSwing(Fixed) 0to2.5 V

IntrospectTechnology http://introspect.ca [email protected]

RevisionNumber History Date

1.0 Documentrelease Feb27,2013

1.1 Updatedjitterinjectionspecs,SSCspecs,clockrecoveryspecs;addedblockdiagramdescriptions

Oct07,2013

1.2 Minoredits Oct07,2013

1.3 Updatetospecifications Nov12,2013

1.4 Updatetospecifications Apr15,2014

1.5 Updatetospecifications;removedtestsequences

August1,2014

1.6 Updateddocumenttemplate June11,2015

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