multi-rate serdes transceiver for ieee 1394b applications

JOURNAL OF ELECTRONIC SCIENCE AND TECHNOLOGY, VOL. 10, NO. 4, DECEMBER 2012 327

Abstract⎯This paper presents the implementation of

a multi-rate SerDes transceiver for IEEE 1394b applications. Simple and effective pre-emphasis and equalizer circuits are used in the transmitter and receiver, respectively. A phase interpolator based clock and data recovery circuit with optimized linearity is also described. With an on-chip fully integrated phase locked loop, the transceiver works at data rates of 100 Mb/s, 400 Mb/s, and 800 Mb/s, supporting three different operating modes of S100b, S400b, and S800b for IEEE 1394b. The chip has been fabricated using 0.13 μm technology. The die area of transceiver is 2.9×1.6 mm2

including bonding pads and the total power dissipation is 284 mW with 1.2 V core supply and 3.3 V input/output supply voltages.

Index Terms⎯Clock and data recovery, equalizer,

firewire, IEEE 1394, pre-emphasis, SerDes.

1. Introduction Requirements for high speed transmission never stop.

Nowadays, communication has been playing an unprecedented important role. When the speed becomes faster and faster, transmitting the data by the conventional parallel bus for a long distance has become no longer suitable in terms of power, area, and reliability. Timing errors caused by jitter and skew on the parallel bus make the receiver synchronization very hard, and limit the transmission speed. On the other hand, cross talk, noise, and coupling from adjacent lines limit the bandwidth. One

Manuscript received August 18, 2012; revised November 2, 2012. This

work was supported by the National Natural Science Foundation of China under Grant No. 61006027 and the New Century Excellent Talents Program under Grant No. NCET-10-0297.

L.-F. Wei, J.-Y. Ji, and Q. Li are with the Centre for Communication Circuits and Systems, University of Electronic Science and Technology of China, Chengdu 610054, China (e-mail: [email protected]; [email protected]; [email protected]).

H.-Q. Liu is with the Integrated Device Technology, Shanghai 200233, China (e-mail: [email protected]).

L.-N. Li is with the Department of Electronic Information Engineering, Beijing Jiaotong University, Beijing 100044, China (e-mail: [email protected]).

Q. Li is also with the Integrated Circuits & Electronics (ICE) Lab, Department of Engineering, Aarhus University, Denmark.

Digital Object Identifier: 10.3969/j.issn.1674-862X.2012.04.008

promising solution is replacing the parallel bus by serial links with SerDes transceivers. At low frequencies, the transmission line behaves as an resistance-capacitance (RC) interconnect. Repeaters are inserted along the interconnect to improve the signal, which will increase the area and power cost. Serializing the data allows transmitting high frequency signals to benefit from the characteristics of the transmission line controlled by the lateral dimensions. The IEEE 1394 communication network, also known as FireWire, is based on a high-speed serial bus which was developed to provide the same services as modern parallel buses. The features that separate this bus from many other network solutions in a control perspective include: determinism, synchronization features, high bandwidth, flexible utilization, generic tree topology, redundancy, plug-and-play, relatively long distance, noise immunity, wireless support, and an attractive performance-to-cost ratio[1],[2].

As data rates increase, especially in Gb/s, the channel bandwidth becomes limited by the frequency dependent loss of the channel. To compensate for the channel attenuation and other impairments, the pre-emphasis circuit is utilized at the transmitter and equalizer of the receiver in the high speed transceiver[3]. To meet the multi-rate requirement with low cost, in this work, a two-stage continuous-time equalizer is designed at the receiver and the pre-emphasis circuit is used in the transmitter, respectively. Clock and data recovery (CDR) is a critical block in the receiver to recover the data and clock from incoming signals. A phase interpolator (PI) based digital control CDR is designed in this work. The proposed CDR uses all 4-phase clocks generated from a phase locked loop (PLL) and an averaging process to improve the linearity of the digital control step. A fully integrated PLL has also been employed to supply clocks for different operation modes.

The rest of this paper is organized as follows. Section 2 presents the circuit design and analysis of the proposed SerDes transceiver. The overall simulation has been done in Section 3 and experimental results of some key signals are presented, too. We summarize this paper in Section 4 and show our gratitude at last.

2. Circuit Design and Analysis The proposed SesDes transceiver is shown in Fig. 1. It

Multi-Rate SerDes Transceiver for IEEE 1394b Applications

Long-Fei Wei, Jin-Yue Ji, Hai-Qi Liu, Li-Nan Li, and Qiang Li


mainly consists of a receiver (RX), transmitter (TX), CDR, common part, and PLL. Some digital parts, like the 8 B/10 B encoder/decoder, I2C, built-in self test (BIST), have also been implemented on-chip or off-chip but not be discussed in this paper. The final data rates achieve 125

Mb/s, 500 Mb/s, and 1 Gb/s with 8 B/10 B coding/decoding in the SerDes transceiver to meet the standard data rate 100

Mb/s, 400 Mb/s, 800 Mb/s as the specification defined.

2.1 Receiver The structure of RX is shown in Fig. 2. The RX

contains a preamplifier, equalizer, limiting amplifier, and signal detector. An equalizer is used after the preamplifier compensates the channel loss. In the conventional design, four general kinds of receiver equalizers for over Giga data transmissions are adopted: the passive-component equalizer, active continuous-time equalizer using the split-path amplifier, active equalizer using the discrete-time finite impulse response (FIR) filter, and active equalizer using the continuous-time FIR filter. In this work, an active continuous-time equalizer using a split-path amplifiers is applied for cost and performance consideration. This kind of equalizer works without knowing the information of data and clock. The equalized signals are reshaped by the following limiting amplifier, then they are sent to CDR for further processing. On the other hand, a signal detector circuit is applied for the tone test process as specification required.

There are two stages of equalizing amplifier in the proposed equalizer. Each amplifier can be turned on or off by the control register to deliver different channel compensation. One stage of the proposed equalizer has been drawn in Fig. 3. Ignoring high-order effects, the transfer function of the differential pairs is approximately expressed as

Fig. 1. Top view of transceiver.

Fig. 2. Receiver.

( )( )

1 1( )1 2 1 2

d m s s

s s m s d d

R g R C sH s

R C s g R C R s+

= ⋅+ + −

where gm is the transconductance of the input NMOS transistors. The single stage yields a zero at

( )1z s sw R C= and two poles are ( )1 1 2p d dw C R= and

( ) ( )2 1 2p m s s sw g R R C= + ( )1 2z p pw w w< < , with a

low frequency gain ( )0 1 2d m m sA R g g R= + . In our circuit, Rd is fixed while Cd, Rs, and Cs can be adjustable to get different peaking frequencies and low frequency gains[4]. In this design, 2 dB, 0 dB, −2 dB, and −4 dB low frequency gains and a high frequency peaking gain nearly 5 dB occured at the frequencies 110 MHz, 160 MHz, 250 MHz, and 400 MHz can be achieved with the changes of Cd, Rs, and Cs at each stage. The total high frequency boosting gain could be 18 dB compared with the low frequency part by using the equalizer. It must be clear that, in order to get high frequency boosting, the location of poles in each stage of equalizer are always kept at a higher frequency than zero.

Fig. 3. Single-stage amplifier of equalizer. Fig. 4. Frequency responses of the equalizer, channel, and their combined frequency response.

105 106 107 108 109 1010

Frequency (Hz)

20

0

−20

−40

−60

−80

−100

−120

Gai

n (d

B)

Equalizer

Channel

Total

din Cable

Cable dout

RX

TX

d_la

D_TX_in <9:0>

d_dex<9:0>

CDR

Switch array

din<9:0>

dout<9:0

Terminal

PLL Common

clk0 clk45 clk90 clk135 Reference current

Vdd

Rd Rd

outp outn

inn inp

Rs

Cs

Vss

din

sig_on

Preamplifier equalizer

Limiting amplifier Signal detector d_la

WEI et al.: Multi-Rate SerDes Transceiver for IEEE 1394b Applications 329

Fig. 5. CDR. The frequency response of the 100-m unshielded

twisted paired (UTP) model (introduced in Section 3) combined with the impedance matching circuit and ac-coupling circuit is plotted in Fig. 4, together with the frequency response of the equalizer and total frequency response. For the maximum transmission rate of the transceiver is 1 Gb/s, the flat bandwidth required in the system is 700 MHz. Without equalization, the bandwidth of the channel is about 2 MHz (the real line). The equalizer provides 18 dB boosting at 110 MHz (the broken line). After equalization, the total bandwidth is increased to about 60 MHz (the cross line). The final bandwidth does not reach 500 MHz, but it can provide enough eyes opening to the following process. On the other hand, the power consumption of the equalizer can be effectively reduced by the reduced bandwidth.

2.2 Clock and Data Recovery The CDR is a critical part of the SerDes system. In this

design, a PI based CDR is designed. The proposed CDR composes of a slicer, deserializer (it contains a 1-to-2 deserializer and a 2-to-10 deserializer), PI, digital filter, and frequency divider, which is presented in Fig. 5. The clock divider provides full data rate clocks for different operation modes while PI always provides a 1 GHz clock. In order to obtain better linearity, averaging process and digital control are applied.

The presented CDR works as follows: the recovered clock samples the signal d_la by the rising edge as the data information and by the falling edge as phase information respectively in the slicer. Following the slicer, the deserializer transforms the serial one-bit data into 10 parallel data bits. We use 5 bits parallel data and phase information with the conventional NOR (NOT OR) based phase detector (PD) to get the up and down information in 2-to-10 deserializer. In order to achieve better performance, a third-order low pass filter is chosen to process the up and down information between the deserializer and PI. The digital filter is not only used to reduce the high frequency noise but also to function as a decoder. The output codes of the filter, ctrl_bit<63:0>, are sent to the PI to adjust the phase of clk_recover by controlling the magnitude of the PI’s source current. The source current of PI_sub (subset PI, as shown in Fig. 6) is generated by the parallel NMOS

transistors in our design (see Fig. 7). Sixteen NMOS transistors in each differential stage and 64 NMOS transistors in total are used in each subset PI. Each bit of ctrl_bit<63:0> controls one NMOS transistor. The magnitude of current is proportional to the number of transistors turned on. Because the size of NMOS transistors is the same, the PI presents excellent linearity for accurate digital current control.

The PI used in this design consists of two subset PIs namely PI_sub as shown in Fig. 6. One subset PI’s inputs are the clk0 and clk90, while the other one’s are clk45 and clk135. All the clocks are provided by the PLL on-chip. The schematic of the subset PI is plotted in Fig. 7. Each subset PI acts as a mixer. It can be expressed as a weighted summation of the two quadrature clock signals. The weight of each clock is proportional to the source current of its branch. The function expression of the PI_sub can be written as

( ) ( )1 2 3 4clk1 clk0 clk90I I I I= × − + × − where I1, I2, I3, and I4 are the currents of the first, second, third and fourth branches, respectively.

Let a=I1−I2 and b=I3−I4, then the equation becomes

clk1 clk0 clk90a b= × + × . Under the same condition, the output clock of the next

subset PI can be expressed as clk2 clk45 clk135c d= × + ×

where c and d substitute the source current magnitude of clk45 and clk135 respectively like a and b. In order to get the constant output amplitude, the sum of the squares of a and b must be a constant. After normalization, the sum of the squares of absolute value must be 1, expressed as

2 2 1a b+ = .

Fig. 6. Phase interpolator with averaging stage. Fig. 7. Subset phase interpolator.

d_la Slicer 1 to 2 deserializer

2 to 10 deserializer d_des<9:0>

up&down1/2rate_clk clk0 clk45 clk90 clk135

full_rate_clk

ctrl_bits <63:0>

clk_recover PI

Digitalfilter

Clk divider

Vdd

clk1nclk1n

clkln clklp clkln clkQn

clkQp clkQn

Vbias

ctrl_bits1

I1 I2 I3 I4

ctrl_bits2 ctrl_bits3 ctrl_bits4Vss

PI_sub

PI_sub

average

clk0

clk90

clk45

clk1

clk2

clk_recover

clk135


The same derivation applies to c and d. But it is difficult to generate the control signals to meet the above conditions because of the nonlinearity of coefficients changes. So a degraded control signals relationship with small jitter toleration reducing is used[5]. The new equalization is

1a b+ = The coefficients change linearly when adopting the new

equalization. So it can be got from the digital control. In [5], a complicated analog control core was used to generate the control signals. In this work, a digital coder and decoder are adopted with a digital filter to accurately generate the control signals. Each subset PI can obtain a phase ranging from 0° to 360° in this design by applying four differential stages without switching the polarity of the input clock. Coefficients a, b, c, and d can be either negative or positive when reflected in the equation. So, the subset PI in Fig. 7 can avoid the jitter generated by the switch. Both subset PIs generate the same phase clock from different input clocks by the control codes ctrl_bit<63:0> from the digital filter. Another PI combines the outputs of the foregoing subset PIs with the same proportion is added as an averaging stage. So, the expression of the output of the whole PI after normalization is

clk _ recover 0.5 (clk0 clk90 )a b= × × + × + 0.5 (clk45 clk135 )c d× × + × .

In a conventional simple PI structure, the waveform of the output changes with the phase because of the nonlinearity of the mixing process in PI. Even though it can be reshaped by buffers, the phenomenon still exists. For verification, we adopt the output of subset PIs to observe the proposed phenomenon. The differences of differential outputs of each PI are used for observation. The outputs of subset PIs which act as conventional ones are clk1 and clk2, while the output of averaging stage is plotted as clk_average. The clk1 and clk2 are achieved from different phase clocks with the same waveform. When ideal sine waves are used as clk0, clk45, clk90, and clk135, the worst case of waveforms’ difference is plotted in Fig. 8 (a). From Fig. 8, it is clear that when the weight of each input clock changes, the waveform of the output clock changes besides the phase. For the system samples data by the rising edge or falling edge of the clock, the phase of the output clock is actually affected because of its rising edge and falling edge shifting. This leads to a nonlinearity that cannot be ignored in the phase control steps.

In this work, as mentioned previously, the two subset PIs generate the same phase clock from different input clocks. Special care should be taken to the weights of different input clocks used in each subset PI when generating output clocks of identical phase. For example, to get a clock with 45° phase, the coefficients in equation

should be set as follow: a=b=0.5, c=1, and d=0. The waveforms of subset PIs are clearly different. After the averaging process, the final output waveform’s rising edge/falling edge is set between the two subsets’, as shown in Fig. 8 (b). That effectively reduces waveform’s influence to the phase control step benefiting from smaller edge shifting. The same analysis can be extended to the whole phase range. So the phase step of the whole PI in this work is closer to a constant equaling to 360/64=5.625º (15.625 ps) than the conventional simple PI structure. Benefiting from the averaging stage and using all four-phase clocks, the presented CDR can reduce the influence suffered from offset and mismatch. The simulation result has been drawn in Fig. 9. The ctrl_bit<63:0> are changed in turn to get a uniform change to the phases of the subset PIs’ and averaging stage’s output clocks. The delay time between each output clock and clk0 is simulated as the difference of their phases. In Fig. 9 (a), phase delays of the two subset PIs are plotted, while the phase delay of averaging stage is plotted in Fig. 9 (b). It is clear that the curve of the proposed CDR is nearly a straight line while the subsets’ curves show some nonlinearity. It can also be seen from Fig. 9 that the worst case of the difference between the subset PIs’ output waveforms mentioned above occurs at the maximum deviation places of the two curves in Fig. 9 (a). The excellent linearity is a powerful guarantee to reduce the jitter and precisely control the digital controlled CDR.

(a)

(b) Fig. 8. Different waveforms of (a) subset PIs (clk1&clk2) and (b) overall presented PI (clk_average).

(a) (b)

Fig. 9. Phase delays: (a) subset PIs and (b) overall presented PI.

0.264 0.266 0.268 0.270Time (μs)

0.50

0

−0.50Am

plitu

de (V

)

0.50

0

−0.500.264 0.266 0.268 0.270

Time (μs)

Am

plitu

de (V

)

5.0

4.5

4.0

3.5

Del

ay (s

)

5.0

4.5

4.0

3.5

Del

ay (s

)

0.4 0.8 1.2 Time (μs)

0.4 0.8 1.2Time (μs)


Fig. 10. Transmitter. Fig. 11. Subset driver.

2.3 Transmitter The TX dominates the function of receiving the parallel

data from the logic core, transferring the parallel data into serial data before sending them out to cable. It consists of a serializer and line driver with pre-emphasis. The serializer outputs the full rate data to the line driver, and the line driver accomplishes the function of pre-emphasis. The pre-emphasis at TX is an important part to overcome the poor high frequency characteristics of the channel. In this work, we adopt a low-cost symbol-spaced FIR filter based pre-emphasis cell in the line driver for its simplicity.

The function diagram of the line driver is depicted in Fig. 10. Each driver (shown in Fig. 11) provides the current to the load to generate the voltage. The current provided by each pre-emphasis driver (driv_emp) is 10% of that provided by main driver (driv_main). Each driv_emp can be turned on and off by the control register demp<1:0>. Because of the current mirror based structure, the emphasis proportion can be precisely controlled. The proportion can be 20%, 10% or 0 in this work. The direction of driv_main’s and driv_emps’ currents flowing through the load is opposite. Because of 1 bit delay between the main driver and pre-emphasis driver, the pre-emphasis can be achieved. A common-mode feedback (CMFB) circuit is applied to ensure the common-mode voltage of output d_ser_out to be 1.65 V, which is equal to half of the I/O supply voltage. The DC offset cancellation function is achieved by controlling the Vds (source-drain voltage) of the main driver’s P-channel metal oxide semiconductor (PMOS) current bias transistor P1. The CMFB circuit will return a

control current paralleled with the P1’s current. Under the ideal condition the feedback current is 20% of the main current that the main driver provides. When the common mode voltage changes, the feedback current will change to make a change of Vds. For the loop is negative feedback, the DC offset can be effectively controlled.

2.4 Phase Locked Loop A fully integrated PLL is designed to provide the clock

network for the whole system without any external component, and is compatible with the different operation modes defined by the IEEE 1394b protocol to coordinate the operation of all the blocks, ports, and nodes. As shown in Fig. 12, the PLL consists of the phase/frequency detector (PFD), differential charge pump, second-order low pass loop filter, quadrate phase voltage controlled oscillator (VCO), and feedback frequency divider. In order to improve the duty cycle of the output clock to accommodate possible double edge operations in digital parts, duty correction technique is employed in the divider.

In order to achieve full integration, a lot of design efforts have been put in the design of the PLL. For the VCO, if an inductor-capacitor (LC) oscillator is used, the inductor and capacitor’s size will be too large to be integrated, and it is hard to generate different phases. Thus, a 4-stage ring oscillator is chosen[6]. The delay cell is the commonly used source coupled delay cell, which has good linearity. And to suppress the variation of the output swing, a replica circuit has been adopted to stabilize the amplitude. The VCO’s output waveforms are shown in Fig. 13.

refF

divFctrlV outF

CP

upupb

downdownb

LF

VCO

N÷ Fig. 12. Design of PLL.

Fig. 13. Output waveforms of VCO.

397 6.3975 6.398 6.3985 6.399 6.3995 6.4Time(us)

PFD

d_sern

P2 P1

N1

N4

N3

N2

P3

n p d_serp

Vdd

Vss

Vbiasp

Vbiasn2

Vbiasn1

Am

plitu

de (V

)

6.397 6.398 6.399 6.400Time (μs)

d_TX_in <9:0>

Serilizer d_ser d_ser_out

Line driver

d_ser

delay demp<1>

delay demp<0>

driv_main

driv_emp

driv_emp

d_ser_out_n d_ser_out_p

n

n

n

p

p

p

load

CMFB

1.1

1.0

0.9

0.8

0.7

0.6

0.5


The second-order loop filter used here is implemented by passive devices. In order to validate the filter’s topology and configure the appropriate value of the passive devices, behavior models built by Verilog-A are used after other loop parameters being determined. The results of the simulation of the behavior model show that the passive second-order loop topology can fulfill the loop requirement. The total power consumption of the PLL is 16.54 mA. The simulated settling time is less than 2 μs.

3. Test and Experimental Results The layout of this work is shown in Fig. 14. The chip

has been fabricated by using 0.13 μm technology. To simulate the channel characteristics of long-distance transmission, the RLC transmission-line model for 100-m UTP is adopted. The model described in [7] is shown in Fig. 15. For short distance transmission, we directly connect the impedance matching circuit to the ac_coupling circuit. The testbench is illustrated in Fig. 16. A loopback test simulation is carried out, which loops the transmitted data back into the receiver.

Fig. 14. Layout of the presented transceiver. Fig. 15. RLC transmission-line model for 100-m UTP (the units for R, L, and C is Ω, H, and F, respectively.)

Fig. 16. Testbench.

(a) (b) (c) Fig. 17. Eye diagrams of signals: (a) din, (b) d_la, and (c) dout.

(a)

(b)

(c) Fig. 18. Waveforms of (a) din, (b) d_la, and (c) dout.

When 20% pre-emphasis is enabled in TX, under long-distance transmission simulation, the eye diagrams of signals including the input of RX (din), the output of limiting amplifier (d_la), and the output of TX (dout) are drawn from left to right in Fig. 17. In Fig. 17 (a), after transmission through the cable, the eye almost closes and the jitter of din is up to 262 ps because of the poor high frequency characteristics of the channel. After equalization, the eye of d_la is restored with jitter less than 154 ps. The TX output dout has the maximum jitter of 22 ps and 431 mV output swing. The waveforms of din, d_la, and dout are plotted in Fig. 18 from top to bottom.

4. Conclusions In this work, a SerDes transceiver for IEEE 1394b is

presented. It works at data rates of 100 Mb/s, 400 Mb/s, and 800 Mb/s with 1.2 V core supply and 3.3 V I/O supply. The PI based CDR with digital control possesses excellent linearity and the jitter of the PLL remains relatively small at high speed. The simple pre-emphasis circuit and programmable equalizer are used in the transmitter and receiver respectively to compensate the channel loss. The transceiver occupies a die area of 2.9×1.6 mm2, and consumes a power of 284 mW.

Random code

generator din <9:0> SerDes dout

<9:0> din dout

AC coupling Cable

Impendancematching

14.35 14.36 14.37 14.38 14.39Time (μs)

50

0

−50

Am

plitu

de (m

V)

1.2

1.0

0.814.35 14.36 14.37 14.38 14.39

Time (μs) Am

plitu

de (m

V)

Am

plitu

de (m

V) 2.0

1.6

1.214.35 14.36 14.37 14.38 14.39

Time (μs)

Out

put p

ort

Inpu

t por

t

L=1μ L=7μ

L=7μ L=1μ


Acknowledgment The authors would like to thank Hui-Yu Feng from UESTC

for discussion in digital section of the transceiver.

References [1] M. Hosek, “Clustered-architecture motion control system

utilizing IEEE 1394b communication network,” in Proc. of American Control Conf., Portland, 2005, pp. 2939–2945.

[2] IEEE Standard for a High Performance Serial Bus Amendment 2, IEEE 1394b-2002.

[3] J. Liu and X.-F. Lin, “Equalization in high-speed communication systems,” IEEE Circuits and Systems Magazine, vol. 4, no. 2, pp. 4–17, 2004.

[4] J. S. Choi, M. S. Hwang, and D. K. Jeong, “A 0.18 μm CMOS 3.5-Gb/s continuous-time adaptive cable equalizer using enhanced low-frequency gain control method,” IEEE Journal of Solid-State Circuits, vol. 39, no. 3, pp. 419–425, 2004.

[5] R. Kreienkamp, U. Langmann, C. Zimmermann, T. Aoyama, and H. Siedhoff, “A 10-Gb/s CMOS clock and data recovery circuit with an analog phase interpolator,” IEEE Journal of Solid-State Circuits, vol. 40, no. 3, pp. 736–743, 2005.

[6] H.-Q. Liu, W. L. Goh, L. Siek, W. M. Lim, and Y.-P. Zhang, “A low-noise multi-GHz CMOS multiloop ring oscillator with coarse and fine frequency tuning,” IEEE Trans. on Very Large Scale Integration (VLSI) Systems, 2009, vol. 17, no. 4, pp. 571–577.

[7] A. A. Fayed and M. Ismail, “A low-voltage low-power CMOS analog adaptive equalizer for UTP-5 cables,” IEEE Trans. on Circuits and Systems I, vol. 55, no. 2, pp. 480–495, 2008.

Long-Fei Wei was born in Chongqing, China in 1988. He received the B.S. degree in communication engineering from the University of Electronic Science and Technology of China (UESTC), Chengdu in 2010. He is currently pursuing his M.S. degree with the Centre for Communication Circuits and Systems, UESTC. His research

interests include high-speed SerDes transceiver and ADC.

Jin-Yue Ji was born in Chongqing, China in 1988. She received the B.S. degree in communication engineering from UESTC, Chengdu in 2010. She is currently pursuing her M.S. degree with the Centre for Communication Circuits and Systems, UESTC. She is now also working with the Centre for Communication Circuits and

Systems, UESTC. Her research interests include analog/mixed- signal integrated circuits design, phase-locked loops, and SerDes and data converters.

Hai-Qi Liu received the B.S. degree from Tianjin University, Tianjin, China in 2000, the M.S. degree from Tongji University, Shanghai, China in 2003, respectively, both in electrical engineering, and the Ph.D. degree from the School of Electrical and Electronic Engineering, Nanyang Technological University, Singapore in 2007. From 2006 to

2008 he was with Institute of Microelectronics, Singapore, where he was involved with analog/mixed-signal circuits development for biosensor and RFID. From 2008 to 2009 he was with Oxford Semiconductor, Singapore, where he was involved in high speed SerDes products development. In 2009 he joined the Institute for Infocomm Research, Singapore, and worked as the Research Fellow on the 60-GHz millimeter-wave project. Since December 2010 he has been with the Integrated Device Technology (IDT) in Shanghai, China, where he has been designing circuits for temperature sensors and a multi-Gb/s SerDes. He is currently a Staff Engineer/Project Leader with IDT.

Li-Nan Li was born in Shanxi Province, China in 1969. He received the B.S. degree from Harbin Institute of Technology, Harbin in 1991, the M.S. degree from Shanxi Institute of Microelectronics, Xi’an in 1994, and the Ph.D. degree from the Institute of Microelectronics of Chinese Academy of Sciences, Beijing in 2001. Now he is an

associate professor with Beijing Jiaotong University. His research interests include RF and analog circuit design, submicron CMOS process, and VLSI IC design.

Qiang Li received the B.Eng. in electrical engineering from the Huazhong University of Science and Technology (HUST), Wuhan, China and the Ph.D. in electrical and electronic Engineering from the Nanyang Technological University (NTU), Singapore. He has been working on analog/RF and mixed-signal circuits in both academia and

industry, holding positions of RTP trainee, senior/research engineer, project leader and technical consultant during 2001–2009 in Singapore. In 2009, he returned to China as a professor at UESTC, Chengdu, where he has brought up the Analog group. His research interests include ultra-low voltage and micro power analog/RF & mixed-signal circuits, data converters, and digital-intensive analog design techniques.

Dr. Li was the author of 30+ scientific publications, 2 international patents and the book Analysis and Design of CMOS Ultra-Wideband Impulse Radio Transceiver (VDP/LAP Lambert Academic Publishing, June 2010). He serves as a member of Editorial Board for the International Journal of RF and Microwave Computer-Aided Engineering (SCI-indexed) and reviewer for a number of scientific publications and funding agencies. He was the recipient of the New Century Excellent Talents Program Award from the Ministry of Education of China, and Teaching Excellence Award for Young Faculty Members from UESTC.

multi-rate serdes transceiver for ieee 1394b applications

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