synchron’08 jean-françois le tallec inria sop lab, aoste inria sop lab, epi aoste scaleochip...
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Synchron’08
Jean-François LE TALLECINRIA SOP lab, INRIA SOP lab, EPI AOSTEAOSTEScaleoChip CompanyScaleoChip Company
SoC Conception Methodology
System on Chip3
What’s a SoC ?
• Piece of software
• IP software for modularity
IP softwareIP software
IP softwareIP software
IP softwareIP software
System on Chip4
What’s a SoC ?
• Piece of software & hardware
• IP software for modularity
• IP hardware for fast execution
IP softwareIP software
IP softwareIP software
IP softwareIP software
IP hardwareIP hardware
IP hardwareIP hardware
IP hardwareIP hardware
System on Chip5
What’s a SoC ?
• Piece of software & hardware & interconnect
• IP software for modularity
• IP hardware for fast execution
• interconnect
IP softwareIP software
IP softwareIP software
IP softwareIP software
IP softwareIP software
IP softwareIP software
IP softwareIP software
IP hardwareIP hardware
IP hardwareIP hardware
IP hardwareIP hardware
System on Chip6
What’s a SoC ?
• Piece of software & hardware & interconnect
• IP software for modularity
• IP hardware for fast execution
• interconnect
IP softwareIP software
IP softwareIP software
IP softwareIP software
IP softwareIP software
IP softwareIP software
IP softwareIP software
ChipSystem
IP hardwareIP hardware
IP hardwareIP hardware
IP hardwareIP hardware
SoC conception7
full designfull design softwaresoftwareSpecSpec Final productFinal product
Usual methodology up to now:Usual methodology up to now:
SoC conception8
full designfull design softwaresoftwareSpecSpec
FPGApre-design
FPGApre-design
softwaresoftware
ScaleoChip methodology:ScaleoChip methodology:
Real designReal design
Final productFinal product
Final productFinal product
Speed up SoC conception
More tolerant to bug
Speed up SoC conception
More tolerant to bug
SpecSpec
Usual methodology up to now:Usual methodology up to now:
Designing problems9
Problems up to now
• Hardware needed to test software
• Interconnect Dimensioning
• HW/SW partitioning
Designing problems10
Problems up to now
• Hardware needed to test software
• Interconnect Dimensioning
• HW/SW partitioning
Potential solution
• Physical one : ScaleoChip
• Virtual one : virtual platform
• ARM SoC designer (SystemC inside)
• Virtutech
• Vast
• Coware
• Cofluent
SystemC11
• C++ library
• Aiming to describe HW & SW
•Different level of description
• PV to RTL
• Simulation & event based
• wait on event or on time
• Hierarchical description
• modules, ports, signals
• Process type
• sc_method • sc_thread
Early experiments12
Encoding of a realistic case study of an IP component :
Proprietary Flash Controller from Verilog to SystemC (our running example)
Cortex M3Cortex M3
AHB2APBBridge
AHB2APBBridge
FlashController
FlashController
Flash AFlash A
Flash BFlash B
AHB Bus
Early experiments13
Several steps
• replace Verilog version by SystemC-RTL rewritting
• verify behavior preservation
• plug in a larger system description for RTL simulation
Early experiments14
Several steps
• replace Verilog version by SystemC-RTL rewritting
• verify behavior preservation
• plug in a larger system description for RTL simulation
Results
• Time consuming
• Behavior can be maintained
• Simulation consumes 11% more than original one
Early experiments15
Several steps
• replace Verilog version by SystemC-RTL rewritting
• verify behavior preservation
• plug in a larger system description for RTL simulation
Results
• Time consuming
• Behavior can be maintained
• Simulation consumes 11% more than original one
=> Don’t really scale up
Some other results16
• SystemC scheduler Parallelism emulation
• method re-activation during delta-cycle til stabilization
=> event partially ordered may be more efficient
• Assume static cycle will stabilize
• Known at simulation time if scenario is well chosen
Next17
• Flash Controller
• control oriented
• three different interfaces
• kind of synchronous behavior
Next18
• Flash Controller
• control oriented
• three different interfaces
• kind of synchronous behavior
• Rise level of description (abstraction)
Two options :
• SystemC-TLM
• Multi-clock Esterel
Models control part in Esterel See what could be TLM programming in Esterel
SystemC vs Esterel19
•Event driven + physical time
•Input / Sensitivity list
•Wait()
•Parallelism emulation
•Can describe different level of abstraction
•PV to RTL
•Simulation based approach
•Activity stabilization (delta cycle)
• Clock driven + logical time
•Input / Interface
•Await()
• Parallelism
•Can describe different level of abstraction (maybe …)
•Esterel multi-clock ?
• Synthesis based approach
•Static cycle must be avoided
Convert sc_thread into sc_method + clock24
thread << event
loop
wait(event)
body1
wait(time)
body2
end loop
method1 << event << ready_to_restart
do
body1
emit event_start_count
end do
clock (min_time_resolution)
method2 << event_start_count&clock
do
when event_start_count
count time clock period
emit event_time_elapsed
end do
method3 << event_time_elapsed
do
body2
emit event_time_elapsed
end do
SystemC module representation25
Here state are methods that potentially emit signal when terminating and then activate other methods