sys verilog interfaces

7/27/2019 Sys Verilog Interfaces

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SV INTERFACES


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DISADVANTAGES OF VERILOGS

MODULE PORTS

Declarations must be duplicated in multiple

modules.

Communication protocols must be duplicated

in several modules.

There is a risk of mismatched declarations in

different modules.

A change in the design specification can

require modifications in multiple modules.


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EXAMPLE


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ADVANTAGES OF SYSTEM VERILOG

INTERFACES

an interface is an abstract port type

An interface allows a number of signals to be

grouped together and represented as a single

port.

The declarations of the signals that make up

the interface are contained in a single

location.


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Interface Definitions


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Top-level Netlist


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SYSTEM VERILOG INTERFACE

CONTENTS

interfaces can contain functionality

Communication protocols can be defined in the

interface.

Protocol checking and other verification routines

can be built directly into the interface.

Interfaces eliminate redundant declarations


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DIFF B/W MODULES & I/Fs

Interfaces are not the same as modules

1. an interface cannot contain design hierarchy

2. an interface can be used as a module port, which

is what allows interfaces to represent

communication channels between modules.

3. an interface can contain modports, which allow

each module connected to the interface to seethe interface differently


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I/F DECLARATIONS

interfaces are defined in a similar way as modules

An interface can have ports, just as a module

does.

This allows signals that are external to the

interface, such as a clock or reset line, to be

brought into the interface and become part of

the bundle of signals represented by theinterface.

SystemVerilog greatly simplifies netlists


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Source code declaration order

an interface name can be used before its

definition

any module can use an interface as a module

port, without concern for the order in which

the source code is compiled.


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GLOBAL & LOCAL I/F DEFs

interfaces can be global declarations

This allows an interface definition to be used as a portby any module, anywhere in the design hierarchy.

interfaces can be limited to specific hierarchy scopes An interface definition can be nested within a module,

making the name of the interface local to that module.Only the containing module can instantiate a locallydeclared interface. This allows the use of an interfaceto be limited to just one portion of the designhierarchy, such as to just within an IP model.


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USING I/Fs AS MODULE PORTS

Explicitly named interface ports

A module port can be explicitly declared as a specific type of interface. This isdone by using the name of an interface as the port type.

module ( );

For example:interface chip_bus;

...

endinterface

module CACHE (chip_bus pins, // interface port

input clock);

...

endmodule


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Generic interface ports

A generic interface port defines the port type usingthe keyword interface, instead of a using the name ofa specific interface type.

module (interface );

module RAM (interface pins,

input clock);...

endmodule


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INSTANTIATING & CONNECTING I/Fs

interface ports must be connected

the port of an interface can connect to another

interface

This capability allows one interface to be connected

to another interface.

The main bus of a design, might have one or more

sub-busses.


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REFERENCING S/Ls WITHIN AN I/F

signals in an interface are referenced using the port

name


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I/F MODPORTS

modports define interface connections from

the perspective of the module


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Selecting the modport in the module instance

the modport can be selected in the module instance


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USING TASKS & FUNCTIONS IN I/Fs

Interface methods

an interface method is a task or function

Methods encapsulate functionality in one place

an interface can be used not only to encapsulate the data

connecting modules, but also the communication

protocols between the modules.


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Importing interface methods

modules can import interface methods

1. a method can be imported using just its name


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2. a method can be imported using a full prototype


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USING PROCEDURAL BLOCKS IN I/Fs

interfaces can contain protocol checkers and other functionality

an interface can contain functionality that can be described using

always, always_comb, always_ff, always_latch, initial or final

procedural blocks, and assign statements.

An interface can also contain verification program blocks.

usage of procedural blocks within interfaces is to facilitate

verification of a design.


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RECONFIGURABLE I/Fs

Interfaces can use parameter redefinition and generate

statements, in the same way as modules.

This allows interface models to be defined that can be

reconfigured each time an interface is instantiated.

interfaces can use parameters, the same as modules


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interfaces can use generate blocks

Generate blocks can be used to replicate continuous

assignment statements or procedural blocks within

an interface any number of times.


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VERIFICATION WITH I/Fs

Communication protocols can be verified before a design

is modeled

An interface can contain methods for the communication

protocols, the interface can be tested and verified

independent of the rest of the design.

Modules that use the interface can be written knowing

that the communication between modules has already

been verified.

sys verilog interfaces

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