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    SV I/Fs

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    DISADVANTAGES OF VERILOGSMODULE PORTS

    Declarations mst !e "#licate" inmlti#le mo"les$

    %ommnication #rotocols mst !e"#licate" in se&eral mo"les$

    T'ere is a ris( o) mismatc'e""eclarations in "i*erent mo"les$

    A c'an+e in t'e "esi+n s#eci,cationcan re-ire mo"i,cations in mlti#lemo"les$

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    E.AMPLE

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    ADVANTAGES OF SSTEM VERILOGINTERFA%ES

    an interface is an abstract port type

    An inter)ace allo0s a nm!er o)si+nals to !e +ro#e" to+et'er an"re#resente" as a sin+le #ort$

    T'e "eclarations o) t'e si+nals t'atma(e # t'e inter)ace are containe"in a sin+le location$

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    Inter)ace De,nitions

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    To#1le&el Netlist

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    SSTEM VERILOG INTERFA%E%ONTENTS

    interfaces can contain functionality %ommnication #rotocols can !e

    "e,ne" in t'e inter)ace$

    Protocol c'ec(in+ an" ot'er &eri,cationrotines can !e !ilt "irectl2 into t'einter)ace$

    Interfaces eliminate redundantdeclarations

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    DIFF 3/4 MODULES 5 I/Fs

    Interfaces are not the same as modules

    6$ an inter)ace cannot contain "esi+n 'ierarc'2

    7$ an inter)ace can !e se" as a mo"le #ort8

    0'ic' is 0'at allo0s inter)aces to re#resentcommnication c'annels !et0een mo"les$

    9$ an inter)ace can contain mo"#orts8 0'ic'allo0 eac' mo"le connecte" to t'e

    inter)ace to see t'e inter)ace "i*erentl2

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    I/F DE%LARATIONS

    interfaces are dened in a similar way asmodules

    An inter)ace can 'a&e #orts8 :st as a

    mo"le "oes$ T'is allo0s si+nals t'at are e;ternal to t'e

    inter)ace8 sc' as a cloc( or reset line8 to !e!ro+'t into t'e inter)ace an" !ecome #art

    o) t'e !n"le o) si+nals re#resente" !2 t'einter)ace$

    SystemVerilog greatly simplies netlists

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    Sorce co"e "eclarationor"er

    an interface name can be usedbefore its denition

    an2 mo"le can se an inter)ace as amo"le #ort8 0it'ot concern )or t'eor"er in 0'ic' t'e sorce co"e iscom#ile"$

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    GLO3AL 5 LO%AL I/F DEFs

    interfaces can be global declarations

    T'is allo0s an inter)ace "e,nition to !e se" as a#ort !2 an2 mo"le8 an20'ere in t'e "esi+n'ierarc'2$

    interfaces can be limited to specic hierarchy scopes

    An inter)ace "e,nition can !e neste" 0it'in amo"le8 ma(in+ t'e name o) t'e inter)ace local tot'at mo"le$ Onl2 t'e containin+ mo"le can

    instantiate a locall2 "eclare" inter)ace$ T'is allo0st'e se o) an inter)ace to !e limite" to :st one#ortion o) t'e "esi+n 'ierarc'28 sc' as to :st 0it'inan IP mo"el$

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    USING I/Fs AS MODULEPORTS

    Explicitly named interface ports A mo"le #ort can !e e;#licitl2 "eclare" as a s#eci,c t2#e o) inter)ace$T'is is "one !2 sin+ t'e name o) an inter)ace as t'e #ort t2#e$

    module

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    Generic interface ports A +eneric inter)ace #ort "e,nes t'e #ort t2#e sin+

    t'e (e20or" interface8 instea" o) a sin+ t'e nameo) a s#eci,c inter)ace t2#e$

    module

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    INSTANTIATING 5 %ONNE%TING I/Fs

    interface ports must be connected

    the port of an interface can connect to

    another interface

    T'is ca#a!ilit2 allo0s one inter)ace to !e

    connecte" to anot'er inter)ace$

    T'e main !s o) a "esi+n8 mi+'t 'a&e one

    or more s!1!sses$

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    REFEREN%ING S/Ls 4ITCINAN I/F

    signals in an interface are referencedusing the port name

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    I/F MODPORTS

    modports dene interfaceconnections from the perspectiveof the module

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    Selecting the modport in the moduleinstance the modport can be selected in the module

    instance

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    USING TASS 5 FUN%TIONSIN I/Fs

    Interface methods

    an interface method is a task or function

    Methods encapsulate functionality in one place

    an inter)ace can !e se" not onl2 to

    enca#slate t'e "ata connectin+ mo"les8 !t

    also t'e commnication #rotocols !et0een t'emo"les$

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    Importing interface methods modules can import interface methods

    1. a method can be imported using just itsname

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    7$ a method can be imported using a fullprototype

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    USING PRO%EDURAL 3LO%S IN I/Fs

    interfaces can contain protocol checkers and other

    functionality

    an inter)ace can contain )nctionalit2 t'at can !e "escri!e"

    sin+ always, always_comb, always_, always_latch,

    initial or nal procedural blocks, and assign

    statements

    An inter)ace can also contain &eri,cation program blocks

    sa+e o) #roce"ral !loc(s 0it'in inter)aces is to )acilitate

    &eri,cation o) a "esi+n$

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    RE%ONFIGURA3LE I/Fs

    Inter)aces can se #arameter re"e,nition an"

    +enerate statements8 in t'e same 0a2 as

    mo"les$

    T'is allo0s inter)ace mo"els to !e "e,ne" t'at

    can !e recon,+re" eac' time an inter)ace is

    instantiate"$ interfaces can use parameters the same as

    modules

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    interfaces can use generate blocks

    Generate !loc(s can !e se" to re#licate

    continos assi+nment statements or

    #roce"ral !loc(s 0it'in an inter)ace an2

    nm!er o) times$

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    VERIFI%ATION 4ITC I/Fs

    !ommunication protocols can be veried before a

    design is modeled

    An inter)ace can contain met'o"s )or t'e

    commnication #rotocols8 t'e inter)ace can !e teste"

    an" &eri,e" in"e#en"ent o) t'e rest o) t'e "esi+n$

    Mo"les t'at se t'e inter)ace can !e 0ritten

    (no0in+ t'at t'e commnication !et0een mo"les

    'as alrea"2 !een &eri,e"$


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