7/23/2019 System Verilog Interface

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SystemVerilog Virtual InterfacesThis is most common SystemVerilog interview question that is asked while you will appearing for the position of Verification Engineer.

As you know an interface encapsulate a group of inter-related wires, along withtheir directions (via mod-ports) , synchronization details (via clocking block), functions and tasks.

The major usage of interface is to simplify the connection between modules.But Interface cant be instantiated inside program block, class (or similar non-module entity in System Verilog).

But we needed to be driven from verification environment like class.

To solve this issue virtual interface concept was introduced in System Verilog.A virtual interface is just a pointer to a physical interface. i.e. Virtual interface is a data type (that implies it can be instantiated in a class) which holdreference to an interface (that implies the class can drive the interface usingthe virtual interface).

Virtual interfaces provide a mechanism for separating abstract models and test programs from the actual signals that make up the design. A virtual interface allows the same subprogram to operate on different portions of a design and to dynamically control the set of signals associated with the subprogram. Instead of re

ferring to the actual set of signals directly, users are able to manipulate a set of virtual signals.

interface sample_if() ; // SystemVerilog Interface logic a ; logic b ; modport TB(input a, output b) ; // Modport declarationendinterface

class Driver ; virtual sample_if inf ; // Virtual Interface declaration in class function new (sample_if inf) this.inf = inf ;

endfunction task main () ; inf.a =a ;endtaskendclass