TE-MPE-EP New DQLPU type A Production of 1300 new protection units TE-MPE-EP, VF, 23-Nov-2012 TE-MPE-EP TE-MPE-EP, VF, 23-Nov-2012 Why a new DQLPU type A? To improve protection of 1232 dipole magnets thanks to: Integration of the enhanced quench heater supervision Compatibility with new fully redundant linear power supplies Remote commands, TE-MPE-EP, VF, 23-Nov-2012 DQLPU: old / new configuration SYKO DQQDL#A DQQDL#B DQAMC Fip connector Current front view New front view External linear DC power supplies Fip connector Programming connector x 1300 Internal hardware change in the new implementation TE-MPE-EP, VF, 23-Nov-2012 Motherboard (viewed from inside): 1300 boards to be produced DQQDL#A DQQDL#B DQCSU SPAREDQHSU DQAMC DQAMC: Communication board to the supervision boards to be produced. FIP con./PROG. V taps Voltages power supplies DQHSU Input signals UHDS+trigger and Spare I loop in/out Re-use local quench detector Crate supervision unit: Supervise all voltages. Test presence of the current loop. Remote power cycling boards to be produced. For future upgrades Quench heater supervision unit. DQHDS voltage measurement. Fast current and voltage recording during a discharge of DQHDS through the Heaters boards to be produced. Fip connector + DQAMC reprogramming connector and future nanoFip board emplacement boards to be produced. TE-MPE-EP TE-MPE-EP, VF, 23-Nov-2012 Why during LS1? What are the risks and/or the impact if not done during LS1? More physical interventions will be necessary due to more SEUs on uFip circuits (higher energy). Risk of not detecting fault in quench heaters. To take advantage of this long shutdown To improve the reliability of this equipment. E.g. fully redundant power supplies. To have more diagnostic tools such as the state of the quench heaters or to localise a interruption of the quench loop current. To save some physical interventions by some remote commands. Remark: Old DQLPU_A is highly dependable. Might be difficult to reproduce this dependability, given the increased complexity of the new system. TE-MPE-EP TE-MPE-EP, VF, 23-Nov-2012 Production of DQPLUs Starts beginning of February Final Assembly Starts in June Final Tests July December Reinstallation January sectors See LS 1 schedule Rev crates ready by 01/2014: 9 racks/day 45 racks/week 4weeks/sector Timeline Manpower TE-MPE-EP, VF, 23-Nov-2012 External AGH Poland: 2 people (WP n.3) Assembling crates and working on the test bench BE-OP: 1 person Support for the programmation of the test bench for DYPBs (yellow racks) Internal (EP section) - Design - Type tests - Firmware - Upgrade QPS Low Level supervision (see Jenss presentation) - Procurement of components - Definition of test benches - Production of test benches Identification of missing ressources: Ressources as usual very tight Resources from other MPE sections: New DQLPU Type A EM Production of circuits boards Assembling of Boards Mechanical drawings Routing of some cards MS Software analysis tools: Quench heater data analysis Post-operational check sequences Device configuration database PE Support for re- commissioning the LHC EE Common operation on the yellow racks: test bench Definition of interface between DQLIM and DQLPU Resources from other groups: New DQLPU Type A TRANSPORT See Brunos talk CABLING EN-EL: Fieldbus network upgrade Electricity network Extension cables CONTROLS Upgrade of QPS supervision (see Jenstalk): BE-CO, EN-ICE, BE- OP Potential issues Company orders from internal purchase services may not be delivered Building 281 not ready on time Late delivery components Conflict with other activities (CSCM, LINAC4) TE-MPE-EP, VF, 23-Nov-2012 Safety measures Personal safety: Bd.281: standard procedure like any other laboratory space. No particular risk to test the DQLPUs, except for the Hipot test at 2.5KV, which will require H1T/H2T habilitation. Safety inspection required with EE (Mathieu) for the machine tools and mechanics space. Tunnel equipment: As usual, but access only required for uninstallation and reinstallation. All the DQLPUs must be cleared by RP before taking them out and NO destructive operation foreseen on the reused equipment. That means no soldering work on them. TE-MPE-EP, VF, 23-Nov-2012 What SW tools are planned to be used? Are they ready to be used? Who will provide them? Before installation Firmware DQLPU + all circuits boards: EP (internally) Test bench: DQLPU functional tester: EP --> LabWindows/CVI Functional test DYPB: BE-OP>LabVIEW Working progress After installation QPS console (QPS expert): Java: managed by BE-OP, EN-ICE QPS high level supervision(PVSS): EN-ICE Configuration database: MS section Post operational checks: to be defined but probably MS section Analysis of Quench heater data: to be defined, but probably by MS or PE section (in Java or LabVIEW) SW tools TE-MPE-EP, VF, 23-Nov-2012 Questions Is there any benefit to further automate the process of your tasks (testing, commissioning)? YES What would be the effort implied? Automatic tools for commissioning IST. E.g. interlock tests. To be defined. Current tools already done in LabVIEW but might be better to move them to Java. Work package for MS section (to be defined). What is the long term strategy regarding to maintainability of testing equipment and related software? Test benches will be maintained by EP section (Building 281). Tools for system exploitation: there are still LabVIEW and Java based tools: common strategy to be defined to have a unique platform. Do you foresee other potential showstoppers? (Like delay for supplying components, administrative constraints..). Implementation of the power supplies redundancy in DQLPU type B: to be done on-site (no external resource). In case of problems it must be understood that the DQLPU upgrade and the R2E activities are critical for the restart of the machine (priority must be given). Other less critical tasks may be delayed if necessary, during Christmas shutdown for instance. Finance TE-MPE-EP, VF, 23-Nov-2012 Current status for new boards Motherboard EP design starts week 48 (Spyros) Waiting for a third quote for press- fit connectors (Nicolas) DQCSU EP design starts week 48 (Vincent) Protype for all Analog and digital stages done and tested (Reiner) Major part of components ordered DQHSU Almost ready to launch the production Second protype tested and approved (Jens/Reiner) Major part of components ordered Extension board EP design starts week 50 (Vincent) Type test done Very basic board Time frame Action already taken TE-MPE-EP, VF, 23-Nov-2012 Current status for re-used boards DQAMC Re-use all old DQAMC spares in the pipeline New firmware (EP) DQQDL Re-use all old DQQDL new ones to be tested (Nicolas) New firmware (EP) TE-MPE-EP, VF, 23-Nov-2012 Current status for mechanical enclosures All parts, but Tender form sent week 46 Standard delay: 4 weeks ATOS: 10 prototypes end of January Backpanel To be designedEM: week 49 TE-MPE-EP, VF, 23-Nov-2012 Current status for connectors for mechanical enclosures Harting Han 32B/42 Prototype of matrix (set of 32 pins linked together) Week 48 Waiting for a quote for 2600 connectors (EE/EP) Harting Han E modules Prototype of matrix (set of 6 pins linked together) Week 48 Waiting for a quote (EP) Burndy pieces Waiting for a quote. (Nicolas) Harting Q12 Transmission of signals from current pulses transformers to the motherboard. Tests to be performed to verify the quality of the transmission of signals before acceptance If not concluding, BNC connectors would be the alternative Time frame Action already taken TE-MPE-EP, VF, 23-Nov-2012