technology trends & roadmaps for package...
TRANSCRIPT
Technology Trends & Roadmaps for
Package Innovation
Grace O’Malley
iNEMI
Manager of
European Operations
May 26, 2011
1
Topics To Be Discussed
• Introduction
• The iNEMI Roadmap
• Packaging Technology Trends
• Key Issues Identified
• Critical Long Term Research Needs
Introduction to iNEMI
2
International Electronics Manufacturing Initiative (iNEMI) is an industry-led consortium
of over 90 global manufacturers, suppliers, industry associations and consortia,
government agencies and universities. Working on advancing manufacturing
technology since 1994.
Visit us at www.inemi.org.
5 Key Deliverables:
• Technology Roadmaps
• Collaborative Deployment
Projects
• Research Priorities Documents
• Proactive Forums
• Position Papers
4 Major Focuses:
• Environment
• Miniaturization
• Medical Electronics
• Alternative Energy
Mission: Forecast and Accelerate improvements in the Electronics
Manufacturing Industry for a Sustainable Future.
3
Product
Needs
Technology
Evolution
GAP Analysis
Technology Plan
Research
Priorities
Research
Projects
Methodology
Competitive
Solutions
Roadmap
Industry Solution
Needed
Academia
Government
iNEMI
Members
Collaborate
No Work
Required
Available
to Market
Place
Global
Industry
Participation Disruptive
Technology
2011 Roadmap
Process
2011 Technology Working Groups (TWGs)
55
Organic PCBBoard
Assembly Customer
RF Components &
Subsystems
OptoelectronicsLarge Area, Flexible Electronics
Energy Storage &
Conversion Systems
Modeling, Simulation,
and Design
Packaging
&
Component
Substrates
Semiconductor
Technology
Final
Assembly
Mass Storage (Magnetic & Optical)
Passive Components
Information
Management
Systems
Test, Inspection &
Measurement
Environmentally
Conscious
Electronics
Ceramic
Substrates
Thermal
Management
Connectors
MEMS/
Sensors
Red=Business Green=Engineering Aqua=Manufacturing Blue=Component & Subsystem
Solid State Illumination
Photovoltaics
6
Roadmap Development
Product Emulator GroupsTWGs
Med
ical P
rod
ucts
Au
tom
oti
ve
Defe
nse a
nd
Ae
rosp
ace
Semiconductor Technology
Design Technologies
Manufacturing Technologies
Comp./Subsyst. Technologies
Modeling, Thermal, etc.
Board Assy, Test, etc.
Packaging, Substrates, Displays, etc.
Product Sector Needs Vs. Technology Evolution
Business Processes
Prod Lifecycle Information Mgmt.
Po
rtab
le / C
on
su
mer
Off
ice / L
arg
eS
yste
ms
Netc
om
2009/11 Product Emulator Groups
77
Product Emulator Chair(s) 2011
Automotive Products Jim Spall, Delphi
Medical Products Anthony Primavera, Micro Systems Eng. Bill Burdick, GE Research
Consumer / Portable Products Shahrokh Shahidzadeh, Intel
Office/Large Business System Products David Lober, Intel Dale Becker, IBM
Network, Data, Telecom Chuck Richardson, iNEMI
Aerospace/Defense William Murphy, Lockheed Martin
Optoelectronics and
Optical Storage
Organic Printed
Circuit Boards
Magnetic and
Optical Storage
Supply Chain
Management
Semiconductors
iNEMI
Information
Management
TWG
iNEMI
Mass Data
Storage TWG
iNEMI / IPC / EIPC
/ TPCA
Organic PWB
TWG
iNEMI / ITRS /
MIG/PSMA
Packaging
TWG
iNEMI
Board Assembly
TWG
Interconnect
Substrates—Ceramic
iNEMI Roadmap
iNEMI
Optoelectronics
TWG
Thirteen Contributing Organizations
8
iNEMI / MIG
/ ITRS
MEMS
TWG
iNEMI Roadmap/ITRS Road map Links
One Example
iNEMI/ITRS Packaging TWG
iNEMI PEGS
ITRS Design and System ITWG
iNEMI/ITRS
MEMS TWG
Green = Shared Leadership/Sub-teams
Blue = iNEMI Supplied Product Sector Drivers
New holistic packaging approach to close the gap between chip and substrate interconnect density
Statistics for the 2011 Roadmap
• > 575 participants
• > 310 companies/organizations
• 18 countries from 4 continents
• 21 Technology Working Groups (TWGs)
• 6 Product Emulator Groups (PEGs)
• > 1800 pages of information
• Roadmaps the needs for 2011-2021
• Workshops held in Europe (IMEC, Belgium), Asia (TPCA, Taiwan) and North America (ECTC, Las Vegas) in June 2010
• A Full Global Perspective
• Available to iNEMI members 12/22/10 at: www.inemi.org
• Available to industry beginning March 29 at www.inemi.org
10
iNEMI 2011 Roadmap
Packaging & Component
Substrates TWG
Chairs:
Bill Bottoms, 3MTS
& Bill Chen, ASE
12
Internet Usage Growth Remains Strong 48% of Users in only 5 Countries
Source: 2009 Estimates Morgan Stanley
Connectivity is the Key to Consumer Growth
13
Source: 2009 Estimates Morgan Stanley
Ease of use Improvements Drive Growth
User Interface + Smaller Form Factor + Lower Prices + New Services
14
Source: Morgan Stanley Estimates
State Of The Industry Upbeat Since March 2010
Consumer Market Needs are Driving Technology
Development
Lower Cost
Higher Performance
Longer Battery Life
Innovative Features
Connectivity
Smaller Form Factor
Less Weight
Less Heat Generation
Short Time to Market
Today packaging is a limiting factor to meeting all
these needs, but everything is changing –
design concepts, packaging architectures,
manufacturing processes and systems integration
Technology Trends in Packaging
Single Chip Packaging
• Single chip packaging types are migrating to more compact surface
mount and flip chip packages.
19
OVERVIEW OF IC PACKAGE UNIT GROWTH
Package Type
(Bn Units) 2008 2009 2014
2009 2014
CAAGR
% of Total IC
2014
DIP 6.0 5.3 3.5 -7.8% 1.6%
SO 72.4 67.3 85.0 4.8% 38.8%
QFP/LCC 17.7 14.8 16.7 2.5% 7.6%
QFN 12.8 13.7 35.3 20.9% 16.1%
Wire Bond FBGA 16.6 15.3 25.1 10.4% 11.4%
Stacked FBGA 4.1 3.7 6.6 12.4% 3.0%
Wire Bond BGA 1.2 1.1 1.3 5.1% 0.6%
COB (Wire Bond) 7.3 6.6 10.3 9.1% 4.7%
Flip Chip FBGA 0.20 0.3 1.7 38.8% 0.8%
Flip Chip BGA/LGA 0.93 0.9 1.4 7.9% 0.6%
DCA/WLCSP 8.9 9.0 22.4 20.0% 10.2%
COF/COG/TAB 7.3 6.8 9.7 7.5% 4.4%
Total Flip Chip 17.3 17.0 35.1 15.6% 16.0%
Total Wire Bond 138.0 127.6 183.8 7.6% 84.0%
IC Total 155.3 144.6 218.9 8.6% 100.0%
• Primary issues identified in roadmap were meeting cost targets for both
low end (0.20-32 cent/pin) and harsh (0.20 to 1.40 cent/pin) applications
by 2016 & also for memory and mobile device packages by 2024. • Also meeting operating temperatures for harsh applications
System-in-Package - SIP
• SIP is rapidly penetrating most major market segments
• Benefits in term of size, lower power, shorter time to market, better
assembly efficiencies and lower cost.
• In 2009, 9 Billion SIP units assembled; in 2014 estimated to reach 15.9
Billion units
20
Horizontal Placement
Stacked
Structure
Interposer Type
Interposer - less
Type
Wire Bonding Type Flip Chip Type
Wire Bonding
Type
Wire Bonding +
Flip Chip Type
PoP, e.g Flip Chip Type
Terminal Through Via Type
Embedded Structure
Chip(WLP ) Embedded +
Chip on Surface Type
3D Chip Embedded
Type
WLP Embedded + Chip on
Surface Type
Technology
Ma
turi
ty
Basic
R&D
Applied
R&D
Mass
Production
Commercia-
lization
Die
Stacking
with wire
bonds
Package
on
Package
Stacking
(PoP)
C2C, C2W,
W2W
Stacking
W2W
Stacking
Full swing production for memories.
Every 18 months one layer increase
Testing and yield challenges give
way for Package stacking
Active applied R&D is undertaken
by Research Institutes. System
level challenges are key. In the
phase of industrialization.
Still in Upstream research,
technological challenges such
as yield & device architecture
are key issues.
3D Integration Technology3D IC Packaging 3D IC Integration 3D Si Integration
3D Integration Technology
21
3D Packaging (No
TSV)
3D IC Integration
C2C/C2W/W2W; microbump bonding; 5 ≤ TSV ≤ 30μm;
20 ≤ memory stack ≤ 50μm; 100 ≤ interposers ≤ 200μm
3D Si Integration W2W
pad-pad bonding (TSV
≤ 1.5μm)
3D Stacking
(wirebonds)
PoP
CMOS image sensor
with TSV
Memory (50μm) with
TSV and microbump
Passive TSV interposer to
support high-performance
chips
CMOS image
sensor with DSP
and TSV
32 memory (20μm)
stacked
Active TSV Interposer
(e.g., Memory on Logic
with TSVs)
Mass Production
Low Volume
Production 2008 2010 2012
Don’t care to guess!Mass
Production2011-13 2013-15 2015-17
Low volume production = only a handful of companies are SHIPPING it;
Mass production = many companies are SHIPPING it.
Cu-Cu bonding
SiO2-SiO2 bonding
3D MEMS; 3D LED
Lau, 3D IC Integration PDC
Bumpless
Bumpless
3D Integration Roadmap
22
TSV Interposer
PCB
BT-Substrate
High Performance Chip
Micro Solder Bumps
Ordinary Solder
Bumps
Solder Balls Ordinary Underfill
Special Underfill
RDL
A High-Performance Chip on a TSV interposer
Passive
Interposer
TIME
SIZ
E
IC Moore’s Law
PCB Technology
Organic Technology
Silicon Technology
Reduce the gap
Polyimide Technology
Reliability of RoHS Compliant 2D & 3D IC Interconnects, McGraw-Hill, 2010
TSV Applications in 3D IC Integrations
Renesas uses a TSV interposer to redistribute interconnects in stacked chips
Lau Lau, 3D IC Integration PDC
3D MEMS/ASIC Integrations
ASIC
MEMS
MEMS
ASICTSV
(Through Silicon Via)
ASIC integrated with the
MEMS device in 3D
• Less footprint• Higher performance• Lower cost• Smaller form factor
Advantages:
PCB
PCB
Lau, Lee, Premachandran, and Yu, Advanced MEMS Packaging, McGraw-Hill, 2010
Difficult Challenges For SIP
26
Difficult Challenges for SiP
Category Difficult challenges for SiP
- Heat-dissipation design
- Heat-isolation design between stacked die with different
maximum operation temperatures
- Chip-package-system co-design
- 3D-Design and simulation tools
- Complex standards for information types and management of
information quality along with a structure for moving this
information will be required.
- Partitioning of system designs and manufacturing across
numerous companies will make optimization for performance,
reliability, and cost of complex systems very difficult.
- Stress resistant, superior electrical characteristics, high
temperature resistant, low elasticity
- Substrate; CTE, fine pattern, low elasticity, water permeability
- Development and selection of materials which minimizes high-
temperature warpage
- Wafer thinning, handling, and stress relief
- Molding requirement: narrow gap fill, better flow
characteristics over larger map format, less wire sweep, better
package flatness- DAF attachment method for dicing-before-grinding process,
and thinner DAF
- Less fluctuation of heat-exposed duration of TSV dice while
being stacked
- Device yield immune from accumulating individual defect rates
- Wafer to wafer bonding
- Singulation of TSV wafers/die
- Bumpless interconnect architecture
- KGD assurance
- Test access for individual wafer/die
- TSV nondestructive observation
Design
Material
Process
Test
Wafer Level Packaging - WLP
27
MEMS Packaging
28
MEMS Packaging ExamplesM arket Automotive Consumer 2D Optical
Switch
3D Optical
Switch
Network
Switch
Wireless
Application Acceleration,
airbag sensor
Video games,
appliances
OADM, enable WAN, LAN
Networks
Electronic
Switches
Saw Filters
M EM S Type 2 axis
accelerometer
3 axis
accelerometer
64 Mirrors, 90o
motion
1800 Full
motion mirrors
Contact
switch
Planar filter
Clean Room 100, 10000 100, 10000 100, 10000 100, 10000 100 10000
Die Bond Epoxy Epoxy AuSn Eutectic Epoxy AgSEutectic Epoxy
Wire Bond 0.7 – 1.0 Au ball 0.7 – 1.0 Au ball 1.25 Al, 1.25 Au,
6.0 m Al
1.25 Au
Wedge/ball
1.0 – 1.25 Au
ball
1.0 Au ball
Seal Seam seal Molded Seam seal Seam seal Epoxy Epoxy lid seal
Leak Test Gross/fine None Gross/fine Gross/fine Gross/fine None
Additional - - Fiber optics,
connectors
Flex circuit,
connectors
PWB
connectors
SMT connector
M anufacturing
Level
Production Production Pre-production Pre-production,
R&D
Pre-
production,
Proto
Pre-
production,
Proto
Package Ceramic, CERDIP,
Hermetic
Plastic, ceramic,
hermetic, CLCC
Custom-68 I/O Custom – 800
I/O
LTCC Panel PWB Panel
3. See the iNEMI MEMS and ITRS Wireless MEMS Chapters for more detail on RF applications.
2. These new device types require new packaging technology. The complexity is further increased by the penetration of SiP technology into
an increasing number of products.
1. After several years with only a limited number of applications such as relays, accelerometers and specialized sensors being implemented
with MEMS technology there is now a rapid rise in the number of designs and types of applications. An expanded array of sensors, fluidics,
RF components and other applications are growing rapidly.
Notes for Table AP28
Package Size TO8, 14 ld CerDip Surface mount
CLCC
Custom metal,
82 mm 2
Custom
Ceramic, 184
mm 2
LTCC,
27mm 2
PWB, 40mm 2
Key Issues & Long Term
Research Needs
For single chip packaging there is shift from hard
tooling to more flexible manufacturing platforms
Impact of move to 450mm wafer: in particular for wafer
thinning, saw, die attach and placement
SIP and WLP are demanding new equipment
capabilities both for handling and processing
Pick and place of 3D thin chips
Pick and place of bare 3D stacked chips with
irregular shapes
Rework is more difficult
Heat sink attachment is more difficult
Manufacturing Processes
Challenges
Higher thermal cycles in consumer products
More prone to vibration and drop
Need development of failure classification standards
Identification of failure mechanisms
Improved failure analysis techniques
Electrical/Thermal/Mechanical simulation
Lifetime models with defined acceleration factors
Need to develop understanding to be able to apply
these packaging technologies in longer life time and
high reliability applications.
Reliability Challenges
Migration to ―greener‖ materials and processes
Need for low-ĸ and ultra low-ĸ
Improved materials properties at thermal interfaces
Methodology and characterization database for frequencies > 10GHz
Low stress die attach
TSV- low cost low stress via filling materials and processes
Rigid organic substrates with low loss dielectric, lower TCE and
higher Tg all at lower cost
Embedded passive – improved performance and high reliability
Cu wire bonding for high reliability applications
Solder bump replacement
Thin wafers may need combined dicing film and die attach film
Improvement in properties of molding compounds and edge epoxies.
Materials Challenges
Package Substrates (Mobile product SOP, PoP)
33
Package Substrates: Mobile Products (SiP, PoP)
Year of Production 2009 2010 2011 2012 2013 2014 2015 2016
Parameter unit
Chip to Substrate Interconnect Land Pitch µm 50 50 50 50 50 50 50 50
Min. Finished Substrate Thickness mm 0.2 0.2 0.2 0.2 0.2 0.2 0.2 0.2
Core Material Tg °C 180 180 180 210 210 210 210 210
Core Material CTE (X-Y) ppm/°C 14 14 14 13 13 11 11 11
Core Material CTE (Z) ppm/°C 40 35 35 30 30 30 30 30
Core Material Dk@1GHz - 4.2 4.2 4.2 4.2 4.2 4.0 4.0 4.0
Core Material Df@1GHz - 0.013 0.013 0.013 0.013 0.013 0.010 0.010 0.010
Core Materials Young's Modulus Gpa 24 24 24 24 24 24 24 24
Core Material Water Absorption % 0.10 0.07 0.07 0.07 0.07 0.07 0.07 0.07
Buildup Material Tg °C 156 156 156 166 166 166 166 177
Buildup Material CTE (X-Y) ppm/°C 13 13 13 12 12 12 12 12
Buildup Material CTE (Z) ppm/°C 46 40 40 40 40 40 40 30
Buildup Material Dk@1GHz - 3.4 3.4 3.4 3.0 3.0 3.0 3.0 3.0
Buildup Material Df@1GHz - 0.012 0.012 0.012 0.010 0.010 0.010 0.010 0.010
Buildup Materials Young's Modulus Gpa 4 5 5 5 5 5 5 5
Buildup Material Water Absorption % 0.2 0.2 0.2 0.2 0.2 0.2 0.2 0.2
Min. Line width/Space µm 20/20 18/18 18/18 15/15 15/15 12/12 12/12 10/10
Min. Conductor Thickness µm 25 25 25 20 20 15 15 15
Min. Through Via Diameter µm 100 100 100 80 80 80 80 80
Min. Through Via Land Diameter µm 250 250 250 200 200 200 200 200
Min. Micro Via Diameter µm 80 70 70 60 60 60 60 50
Min. Micron Via Land Diameter µm 150 130 130 120 120 120 120 110
Min. Through Via Pitch µm 300 300 300 275 275 275 275 275
Min. Solder Mask Openning µm 80 80 80 60 60 60 60 50
Min. Solder Mask Openning Tolerance µm 20 20 20 18 18 18 18 15
Package Substrates (High End)
34
Package Substrates: High Performance (High End)
Year of Production 2009 2010 2011 2012 2013 2014 2015 2016
Parameter unit
Package Type - P-BGA S-BGA S-BGA S-BGA S-BGA S-BGA S-BGA S-BGA
Interconnect Method - Flip Chip Flip Chip Flip Chip Flip Chip Flip Chip Flip Chip FC+TSV FC+TSV
Chip to Substrate Interconnect Land Pitch µm 160 150 150 130 130 120 120 120
Max. Pin Counts # 2200 2500 2500 2900 2900 3600 3600 4000
Typical Pin Counts # 2200 2500 2500 2900 2900 3600 3600 4000
Min. External I/O Pitch mm 0.80 0.80 0.80 0.65 0.65 0.50 0.50 0.50
Typical External I/O Pitch mm 1.00 1.00 1.00 0.80 0.80 0.80 0.65 0.65
Typical Materials - High Tg FR-4 Silicon Silicon Silicon Silicon Silicon Silicon Silicon
Typical Buildup Materials - Epoxy Polyimide Polyimide Polyimide Polyimide Polyimide SiO2 SiO2
Max. Layer Counts # 6+6+6 6+2 6+2 6+2 4+2 4+2 4+2 4+2
Typical Layer Count # 6+6+6 6+2 6+2 6+2 4+2 4+2 4+2 4+2
Min. Finished Substrate Thickness mm 1.0 1.0 1.0 1.0 0.6 0.6 0.5 0.5
Typical Finished Substrate Thickness mm 1.0 1.0 1.0 1.0 0.6 0.6 0.5 0.5
Core Material Tg °C 180 1410 1410 1410 1410 1410 1410 1410
Core Material CTE (X-Y) ppm/°C 8 3.0 3.0 3.0 3.0 3.0 3.0 3.0
Core Material CTE (Z) ppm/°C 10 3.0 3.0 3.0 3.0 3.0 3.0 3.0
Core Material Dk@1GHz - 2.8 12 12 12 12 12 12 12
Core Material Df@1GHz - 0.002 0.0005 0.0005 0.0005 0.0005 0.0005 0.0005 0.0005
Core Materials Young's Modulus Gpa 5.5 185 185 185 185 185 185 185
Core Material Water Absorption % 1.40 0 0 0 0 0 0 0
Buildup/RDL Material Tg °C 200 300 300 300 300 300 700 700
Buildup/RDL Material CTE (X-Y) ppm/°C 16 16 16 16 16 16 3 3
Buildup/RDL Material CTE (Z) ppm/°C 20 20 20 20 20 20 16 16
Buildup/RDL Material Dk@1GHz - 3.3 3.3 3.3 3.3 3.3 3.3 2.0 2.0
Buildup/RDL Material Df@1GHz - 0.038 0.038 0.038 0.038 0.038 0.038 0.003 0.003
Buildup/RDL Materials Young's Modulus GPa 4 5 5 5 5 5 10 10
Buildup/RDL Material Water Absorption % 0.2 0.2 0.2 0.2 0.2 0.2 0.2 0.2
Min. Line width/Space µm 12/10 8/8 8/8 8/8 5/5 5/5 5/5 5/5
Min. Conductor Thickness µm 15 10 10 10 8 8 8 5
Min. Through Via Diameter µm 180 180 180 150 150 100 100 80
Min. Through Via Land Diameter µm 350 300 300 250 250 200 200 150
Min. Micro Via Diameter µm 60 60 60 50 50 50 30 30
Min. Micron Via Land Diameter µm 100 100 100 90 90 90 60 60
Min. Through Via Pitch µm 350 300 300 275 275 275 275 275
Min. Solder Mask Opening µm 85 N/A N/A N/A N/A N/A N/A N/A
Min. Solder Mask Opening Tolerance µm 10 N/A N/A N/A N/A N/A N/A N/A
Manufacturable solutions exist, and are being optimized
Manufacturable solutions are known
Interim solutions are known ¿
Manufacturable solutions are NOT known
Changing package dimensions, increased pin count
resulting in smaller ball size and higher reflow
temperature are resulting in warpage becoming a
primary limiting factor for ball pitch and ball size in
BGA packages
Coplanarity acceptance limits for package terminals
are specified but at room temperature.
At SMT reflow temperatures ( 215 to 245 deg C) the
substrates may exhibit significantly lower and higher
warpage than at room temperature, resulting in
reduced yield
This is a major issue in High Volume Manufacturing
Warpage
Warpage at peak temperature
36
Year of
Production2009 2010 2011 2012 2013 2014 2015 2016 2017
-0.14, +0.23 -0.14, +0.23 -0.14, +0.23 -0.14, +0.23 -0.13, +0.21 -0.13, +0.21 -0.13, +0.21 -0.13, +0.21 -0.13, +0.21
-0.14, +0.23 -0.14, +0.23 -0.14, +0.23 -0.14, +0.23 -0.13, +0.21 -0.13, +0.21 -0.13, +0.21 -0.13, +0.21 -0.13, +0.21
-0.14, +0.23 -0.14, +0.23 -0.14, +0.23 -0.14, +0.23 -0.13, +0.21 -0.13, +0.21 -0.13, +0.21 -0.13, +0.21 -0.13, +0.21
-0.14, +0.23 -0.14, +0.23 -0.14, +0.23 -0.14, +0.23 -0.13, +0.21 -0.13, +0.21 -0.13, +0.21 -0.13, +0.21 -0.13, +0.21
-0.14, +0.22 -0.14, +0.22 -0.14, +0.22 -0.14, +0.22 -0.13, +0.20 -0.13, +0.20 -0.13, +0.20 -0.13, +0.20 -0.13, +0.20
-0.14, +0.22 -0.14, +0.22 -0.14, +0.22 -0.14, +0.22 -0.13, +0.20 -0.13, +0.20 -0.13, +0.20 -0.13, +0.20 -0.13, +0.20
-0.14, +0.23 -0.14, +0.23 -0.14, +0.23 -0.14, +0.23 -0.13, +0.21 -0.13, +0.21 -0.13, +0.21 -0.13, +0.21 -0.13, +0.21
-0.14, +0.23 -0.14, +0.23 -0.14, +0.23 -0.14, +0.23 -0.13, +0.21 -0.13, +0.21 -0.13, +0.21 -0.13, +0.21 -0.13, +0.21
-0.10, +0.10 -0.10, +0.10 -0.10, +0.10 -0.10, +0.10 -0.09, +0.09 -0.09, +0.09 -0.09, +0.09 -0.09, +0.09 -0.09, +0.09
-0.10, +0.10 -0.10, +0.10 -0.10, +0.10 -0.10, +0.10 -0.09, +0.09 -0.09, +0.09 -0.09, +0.09 -0.09, +0.09 -0.09, +0.09
-0.12, +0.12 -0.12, +0.12 -0.12, +0.12 -0.12, +0.12 -0.11, +0.11 -0.11, +0.11 -0.11, +0.11 -0.11, +0.11 -0.11, +0.11
-0.12, +0.12 -0.12, +0.12 -0.12, +0.12 -0.12, +0.12 -0.11, +0.11 -0.11, +0.11 -0.11, +0.11 -0.11, +0.11 -0.11, +0.11
-0.10, +0.10 -0.10, +0.10 -0.10, +0.10 -0.10, +0.10 -0.09, +0.09 -0.09, +0.09 -0.09, +0.09 -0.09, +0.09 -0.09, +0.09
-0.10, +0.10 -0.10, +0.10 -0.10, +0.10 -0.10, +0.10 -0.09, +0.09 -0.09, +0.09 -0.09, +0.09 -0.09, +0.09 -0.09, +0.09
0.35 -0.10, +0.10 -0.10, +0.10 -0.10, +0.10 -0.10, +0.10 -0.09, +0.09 -0.09, +0.09 -0.09, +0.09 -0.09, +0.09 -0.09, +0.09
0.25 -0.075, +0.075 -0.075, +0.075 -0.075, +0.075 -0.075, +0.075 -0.065, +0.065 -0.065, +0.065 -0.065, +0.065 -0.065, +0.065 -0.065, +0.065
0.3 -0.075, +0.075 -0.075, +0.075 -0.075, +0.075 -0.075, +0.075 -0.065, +0.065 -0.065, +0.065 -0.065, +0.065 -0.065, +0.065 -0.065, +0.065
0.2 -0.05, +0.05 -0.05, +0.05 -0.05, +0.05 -0.05, +0.05 -0.045, +0.045 -0.045, +0.045 -0.045, +0.045 -0.045, +0.045 -0.045, +0.045
0.25 -0.05, +0.05 -0.05, +0.05 -0.05, +0.05 -0.05, +0.05 -0.045, +0.045 -0.045, +0.045 -0.045, +0.045 -0.045, +0.045 -0.045, +0.045
0.15 -0.05, +0.05 -0.05, +0.05 -0.05, +0.05 -0.05, +0.05 -0.045, +0.045 -0.045, +0.045 -0.045, +0.045 -0.045, +0.045 -0.045, +0.045
0.9
0.4
0.6
0.6
Ball Dia.
(mm)
Pitch
(mm)
1.27
0.45
0.25
1.0
0.8
0.55
0.25
0.4
0.3
0.65
0.5
Warpage at peak temperature (2)
37
Manufacturable solutions exist, and are being optimized
Manufacturable solutions are known
Interim solutions are known ¿
Manufacturable solutions are NOT known
5. PoP packages are not addressed in this table since the requirements will be dependent upon each specific package design.
6. Package warpage (deviation from flatness caused by internal stress) may cause unacceptable SMT quality (solder ball bridging, or non-wet opens).
This table projects increased pin count vs. time for all applications, increasing maximum package size at any given pitch. It also projects decreased package thickness vs. time for all applications.
Increased package size and decreased package thickness increase the difficulty of the component supplier to meet the package warpage limits, but do not change the limits, themselves.
Since PWB warpage increases with increased package size, however, the package warpage limits do need to reduce vs. time to insure acceptable SMT quality.
Package warpage limits must also reduce vs. time to widen the SMT process window and insure acceptable SMT quality.
Reduced package warpage will be achieved through optimization of materials, construction and component assembly processing.
PCB warpage improvement is also needed to share the burden imposed by SMT process demands for larger body sizes, at any given BGA pitch.
Convex (+) Concave (-)
4. Flip chip BGA is consistent with the table entries. These parameters may be tighter than can be achieved for PBGA for large die.
- The component does not meet The corresponding, registration, standard, or Design Guide coplanarity requirements, but passes SMT yield and quality
- The component meets the corresponding Design Guide coplanarity requirements, but SMT yield fails customer expectations, attributable to package
warpage (solder ball bridging, or non-wet opens).
In these cases, characterization of the component warpage at an elevated temperature may provide a more accurate measure of SMT reflow compatibility. JEITA and JEDEC have established acceptance.
2. The values above do not reflect package-on-package topside warpage reqts which may be lower.
3. Solder ball coplanarity results measured at room temperature may have little relation to package warpage at SMT reflow temperatures.
These coplanarity values, however, are based upon room temperature measurements. At SMT reflow temperatures (215-245C, typ.), the substrates of CSP/BGA style packages may exhibit significantly
lower or higher warpage than at room temperature.
Consequently, the following situations may occur:
1. Coplanarity acceptance limits for package terminals (solder balls, pads, leads) are specified for any industry-standard device in the applicable JEDEC, JEITA, IEC, etc., outline drawing.
Strategy Issues Graphics
Project Lead:
Project Co-Lead:
Tactics Milestones and/or Deliverables Plan Actual
Focus Area:
Jun-11TIG:
Goal:
Strategy Issues Graphics
Project Lead:
Project Co-Lead:
Tactics Milestones and/or Deliverables Plan Actual
Develop set of primary parameters for materials, design and process and the working window to control component warpage through supply chain
• Identify the important contributing factors based on component user and manufacturers’ experience and on observations from manufacturing operations, field engineering, and repair facilities.
• Develop recommendations for package structural design and material property selection to minimize warpage
• No clear understanding of the key contributors to warpage at the 1st and 2nd level assembly.
• Existing evaluation criteria for component warpage is not sufficient to prevent defects seen on High Volume SMT lines and in field.
• Component designers & manufacturers are not always aware of the severity of warpage induced defects, and more feedback is needed for these components.
Peng Su, Cisco Systems
Richard Coyle (Alcatel-Lucent)
• Phase 1– Establish baseline of specific substrate
warpage factors– Plan industry survey to identify factors in
both manufacturing and field operations.– Collect and analyze results– Determine categories e.g. design, material
properties, no. of layers, core vs. coreless etc.
Miniaturization
Organic Pack. Substrates
Primary Factors in Component Warpage
Project
Project Launch Date
Plan and conduct survey
Analyse results
Develop categories
Investigate development of test board coupon
Plan and conduct survey
4Q11
3Q11
2Q11
1Q11
1Q111Q11
38
Critical Long Term Research NeedsDifficult Challenges ≤ 16 nm Summary of Issues
-Increased wireability at low cost
-Improved impedance control and lower dielectric loss to support higher frequency
applications
-Improved planarity and low warpage at higher process temperatures
-Low-moisture absorption
-Increased via density in substrate core
-Alternative plating finish to improve reliability
-Solutions for operation temp up to C5-interconnect density scaled to silicon (silicon I/O
density increasing faster than the package substrate technology
-Production techniques will require silicon-like production and process technologies after
2007
-Tg compatible with Pb free solder processing (including rework at260°C)
-Electromigration will become a more limiting factor. It must be addressed through
materials changes together with thermal/mechanical reliability modeling.
-Whisker growth
-Thermal dissipation
-Conformal low cost organic substrates
-Small and thin die assembly
-Handling in low cost operation
-Thermal management
-Design and simulation tools
-Wafer to wafer bonding
-Through wafer via structure and via fill process
-Singulation of TSV wafers/die
- Test access for individual wafer/die
-Bumpless interconnect architecture
Close gap between chip and
substrate, Improved Organinc
substrates
High current density packages
Flexible system packaging
3D packaging
Thank you
www.inemi.org
Email contacts:
Bill Bader - CEO
Grace O’Malley - Europe
Haley Fu - Asia