9-13 Sept. 2002 LECC2002

1 Christine HU-GUO

Test and Evaluation of HAL25 The ALICE SSD Front-End Chip

C. Hu-Guo, D. Bonnet, J.P. Coffin, G. Deptuch, C. Gojak, J.R. Lutz, I. ValinIReS (IN2P3-ULP), Strasbourg, France

 J.D. Berst, G. Claus, C. Colledani

LEPSI (IN2P3-ULP), Strasbourg, France

9-13 Sept. 2002 LECC2002

2 Christine HU-GUO

HAL25 History

1st generation chip: ALICE128C (1997)Designed on a CMOS 1.2 m processGood performance up to 50 Krad of the ionising dose

• Used for the SSD front-end of the STAR tracker

HAL25Designed on a deep submicron 0.25 m process

• For safety margins in radiation environment

• Version 1 (MPW4-March-2001)

• Version 2 (MPW6-November-2001)

9-13 Sept. 2002 LECC2002

3 Christine HU-GUO

HAL25 Block Diagram

AN_

OUT

BIAS PULSE

PULSE

GEN

ANA

MUX

127

PULSE

REG

0

127

|

|

|

ANALOGUE CHANNELS|

|

|

0

127

POWERON

0

TEMPO<1:0>

PULSEDAC<7:0>

OUTBUF

127

READOUT

0

JTAG CONTROLER

BIAS DAC<71:0>

BYPASS<0> BSR<5:0> ID<7:0> STATUS<7:0> POWER_ENA<0> TOKEN_ENA<0>

AIN<127>

AIN<0> OUTBUFCTRL<1:0>

BIAS GENERATORS

PU

LS

E

ID<

3:0

>

TR

ST

B

PW

RS

TB

TC

K

TD

I

TM

S

TD

O

HO

LD

FS

TR

B

TK

_IN

RC

LK

TK

_O

UT

GN

DR

EF

Analogue Sig.

LVDS Sig.

CMOS Sig.

+

-

- 128 Analogue Channels: Preamplifier Shaper Storage capacitor- Analogue Multiplexer- Differential Current Output- 128 Test Pulse Generators

- Set Bias Generator- Set Transparent Mode- Set Test Pulse Generator- Perform Boundary Scan

JTAG remote control

9-13 Sept. 2002 LECC2002

4 Christine HU-GUO

Design Features in HAL25

Single power supply 0-2.5 V 14 MIP dynamic range front-end amplifierDifferential current outputRegisters with majority vote logic

Prevent Single Event Upset (SEU)

Adjustable internal current source (15%)Compensate process variation

9-13 Sept. 2002 LECC2002

5 Christine HU-GUO

Front-end Amplifier

Shaper feedback resistor source degenerated differential pair No “switch+inverter” circuitryVout = Vdc (DC level)

Maximum dynamic range ( 14 MIP ) for GV = 50 mV/MIP

Linearity < 4%Tuneable transconductance

• Tuneable peaking time 1.4s < t < 2.2 s

Vdc P

Vdc N

OUT

Cf2

V dc

INCc

Cload

Hold

Cf1

VPRE

9-13 Sept. 2002 LECC2002

6 Christine HU-GUO

HAL25 Layout

Chip dimension: 3.65 x 11.90 mm2

TAB compatible I/O pads Size & pitche

ESD protected I/O Pads

CMOS for slow controlLVDS for readout

9-13 Sept. 2002 LECC2002

7 Christine HU-GUO

Pedestal Distribution

For 1 chip (128 channels ) I 34 A

1 MIP signal After pedestal subtraction

Output diff (A)

250

-250

9-13 Sept. 2002 LECC2002

8 Christine HU-GUO

Gain & linearity

Agree with simulation Measured pulse fit ideal CRRC curve GI = 200-250 A / MIP (22000 e-) Dynamic range ± 14 MIP Linearity < 2.5% ( ± 10 MIP) & Linearity < 4% ( ± 14 MIP)

Current!

0.0

50.0

100.0

150.0

200.0

250.0

0 2 4 6 8 10 12

1MIP signal

Ideal CRRC

uA

uS

Output Pulse Shape (transparent mode)

9-13 Sept. 2002 LECC2002

9 Christine HU-GUO

Output Pulse Uniformity (MPW6 run)

With the internal test pulse generator 8 MIP signal62 chips x 128 ch (on 2 wafers)Average output pulse amplitude 1875 A 63 A Good uniformity

Analogue channel + test pulse generator

9-13 Sept. 2002 LECC2002

10 Christine HU-GUO

Noise

Noise distribution (128 ch) ENC @ 0pF = 215 e-

= 5 e-

ENC = 215 + 25 e-/pF For peaking time 1.4 s

Bonded channel (1.5 pF)

9-13 Sept. 2002 LECC2002

11 Christine HU-GUO

Nominal readout frequency: 10 MHz Readout up to 20 MHz with degradation of

Linearity & Gain

Maximum readout frequency

FRd = 1 MHzInput = 10 MIP

Ch. 10 Ch. 11 Ch.12 Ch. 10 Ch. 11 Ch.12

Ch. 10 Ch. 11 Ch.12 Ch. 10 Ch. 11 Ch.12

FRd = 10 MHzInput = 10 MIP

FRd = 20 MHzInput = 10 MIP

FRd = 30 MHzInput = 10 MIP

9-13 Sept. 2002 LECC2002

12 Christine HU-GUO

New Request for High Input Rate

Pile-up depends on Input signal time intervals Input signal amplitudes Decay times

Preamplifier decay time Nominal: a few ms ( hundreds Hz) Can be decreased by changing VPRE Rf = f(VPRE)

• Noise increased • Gain reduced

Shaper decay time 8*peaking time ( few tens KHz)

VPRE

Ref. “Pile-up phenomena in HAL25” ftp://lepsi.in2p3.fr/pub/HAL25/Pile_up.pdf

9-13 Sept. 2002 LECC2002

13 Christine HU-GUO

Yield

340 circuits tested from 2 MPW 50% OK

Problem seems to be related to 128 channels architecture for deep sub-micron process

• Long lines for common biases and slow signals

• No errors detected by Design Rule Checkers

0.25m community investigates the problemNew version of HAL25

intended to understand yield issue

9-13 Sept. 2002 LECC2002

14 Christine HU-GUO

ConclusionHAL25 meets specifications Irradiation test with X-ray up to 500 Krad

No performance degradation

Version 3 (MPW8 – September 2002)Focused on yield improvementESD I/O PadsLow power LVDS PadsFuse programmable chip serial number (24 bit)

Future workTest HAL25 + Detector