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Texas Instruments LMG520080V GaN Power StagePower Semiconductor report by Elena Barbarini February 2018 – sample


SUMMARY

Overview / Introduction 3

o Executive Summary

o Reverse Costing Methodology

Company Profile 8

o Texas Instruments

Physical Analysis 15

o Synthesis of the Physical Analysis

o Package analysis

Package opening

Package Cross-Section

o FET Die

FET Die View & Dimensions

FET Die Process

FET Die Cross-Section

FET Die Process Characteristic

o IC Die

IC Die View & Dimensions

IC Die Process

IC Die Cross-Section

IC Die Process Characteristic

Power Stage Manufacturing Process 63

o FET Die Front-End Process

o FET Die Fabrication Unit

o IC Die Front-End Process

o IC Die Fabrication Unit

o Final Test & Packaging Fabrication unit

Cost Analysis 85

o Synthesis of the cost analysis

o Yields Explanation & Hypotheses

o FET die

FET Front-End Cost

FET Die Probe Test, Thinning & Dicing

FET Wafer Cost

FET Die Cost

o IC die

IC Front-End Cost

IC Die Probe Test, Thinning & Dicing

IC Wafer Cost

IC Die Cost

o Complete Power Stage

Packaging Cost

Final Test Cost

Component Cost

Price Analysis 105

o Estimation of selling price

Comparison 108

o Comparison between Panasonic, Transphorm and

GaN Systems HEMT

Feedback 110

System Plus services 112


Overview / Introductiono Executive Summaryo Marketo Reverse Costing

Methodology

Company Profile & Supply Chain

Physical Analysis

Manufacturing Process Flow

Cost Analysis

Selling Price Analysis

Comparison

Feedback

About System Plus

Executive Summary

To minimize the parasites linked to high frequency operations and to propose a driver integrated solution, Texas Instrumentshas introduced the first 80V Half bridge GaN FET power stage device in advanced QFM package.

In this report System Plus Consulting unveils TI’s technical choices; from the device design up to the packaging. It is the firsttime that we can find a Half bridge design GaN FET with its driver, all assembled in an advanced multichip packaging.

The new LMG3410 from TI features a GaN FET with a breakdown voltage of 80V for a current of 10A (25°C). The transistor isdriven by a National Semiconductors silicon IC Gate driver with 1 µm technology node.

The epitaxy structure is composed of different GaN and AlGaN layers and multiple heterojunction structure of AlGaN betweenGaN and the AlN layer. A complex buffer and template layers’ structure is used to reduce the stress and the dislocation.

Based on a complete teardown analysis, the report also provides an estimation of the production cost of the IC Gate driver, theFET and the package.

Moreover, the report proposes a comparison with the GaN Systems, Transphorm and Panasonic packaging and epitaxy. Thiscomparison highlights the differences in design and manufacturing process and their impact on device size and productioncost.


Overview / Introduction

Company Profile & SupplyChain

Physical Analysis o Synthesiso Packageo GaN FETo IC


Cost Analysis


Comparison

Feedback

About System Plus

Synthesis of the Physical Analysis

Package QFM:

o Advanced multichip packaging

o Dimensions: 6mm x 8mm x2mm

o Number of Pins: x pin

FET:

o Dimension: xxxmm x xxxmm = xxx mm²

o Electrical Connection: xxx

o Placement in the package: xxx on copper leadframe.

Package

IC

Package opening – Optical View

IC:

o Dimension: xxx mm² (xxxmm x xxmm)

o Electrical Connection: xxx

o Placement in the package: xxx.

GaN FET






Cost Analysis


Comparison

Feedback

About System Plus

Package Opening – From back side

Package Opening – Cu layer #3

Package Opening – Cu layer #4

Package Opening – Vias #2

• Micro vias: xxx






Cost Analysis


Comparison

Feedback

About System Plus

Device design

Package Opening






Cost Analysis


Comparison

Feedback

About System Plus


Package cross section FET– Cross section #1 - Optical View

Package cross section FET– Cross section #1 - Optical View Package cross section FET– Cross section #1 - SEM View

HEMT

Solder balls

Solder balls

HEMT HEMT






Cost Analysis


Comparison

Feedback

About System Plus


Package cross section IC– Cross section #3 - SEM View






Cost Analysis


Comparison

Feedback

About System Plus

Package Cross-Section – Laminate Substrate

• The package laminate is a xxx layers PCB.

PCB thickness: xxx µm

Copper layers thickness: xxxµm

Microvia diameter: xxxxµm

Substrate Cross-Section – SEM View©2017 by System Plus Consulting






Cost Analysis


Comparison

Feedback

About System Plus

xxx

mm

FET die Dimensions

FET Die – Optical view

o Die dimensions: xxx mm² (xxxmm x xxxmm)

o There is this no marking on the die

xxx mm

sourcesource

DrainDrain

Gate






Cost Analysis


Comparison

Feedback

About System Plus

Die process

Transistor process after delayering – SEM View

Transistor process after delayering – SEM View






Cost Analysis


Comparison

Feedback

About System Plus

Die cross section

Die cross section – SEM View

o Substrate thickness: xxx µm

xxx µmSi Substrate






Cost Analysis


Comparison

Feedback

About System Plus

Die cross section







Cost Analysis


Comparison

Feedback

About System Plus

Die cross section – Gate & source

xxx µm

xxx µm

xxxµm







Cost Analysis


Comparison

Feedback

About System Plus

Die cross section -Gate







Cost Analysis


Comparison

Feedback

About System Plus

EDX epitaxy






Cost Analysis


Comparison

Feedback

About System Plus

xxx

mm

IC die Dimensions

IC Die Overview

o Die dimensions: xxx mm² (xxxmm x xxxmm)

o Connected pads: 12

xxx mm






Cost Analysis


Comparison

Feedback

About System Plus

Die Process

LDMOS transistors are present on the circuit.

Die process– SEM View

Die process– SEM View






Cost Analysis


Comparison

Feedback

About System Plus

Die cross section


o Substrate thickness: xxx µm

xxx µm






Cost Analysis


Comparison

Feedback

About System Plus

Die cross section

The process uses 3 metal layers in Aluminum with planarizationThere are tungsten plugs between the metal layers.

M2 (Al)

M1 (Al)

M3 (Al)





Physical Analysis

Manufacturing Process Flowo FET Fab Unito FET Process Flowo IC Fab Unito Packaging Fab Unit

Cost Analysis


Comparison

Feedback

About System Plus

GaN Transistor - Process Flow (2/4)

Implantation

• Implantation in the AlGaN layer

• Implantation in the gate GaN layer

Gate

•Pattern and GaNetching

Gate

•TiN deposition

•Pattern Gate Metal

Drawing not to Scale

TiN




Physical Analysis

Manufacturing Process Flowo FET Fab Unito FET Process Flowo IC Fab Unito Packaging Fab Unit

Cost Analysis


Comparison

Feedback

About System Plus

GaN Transistor - Solder Bumps

Solder Bumps

•Probe test

•Polyimide deposition and pattern

•UBM

Solder Bumps

• Solder bumps electroplating

• Solder reflow

Dicing

• Dicing

Drawing not to Scale

presaw

Solder bumps

UBM

Solder bumps




Physical Analysis


Cost Analysiso Synthesiso Die Costo Packaging Costo Component Cost


Comparison

Feedback

About System Plus

FET - Yields Hypotheses

In our simulation, we assume a development and a production ramp up without important technical problem.




Physical Analysis




Comparison

Feedback

About System Plus

Wafer Front-End Cost

The front-end cost ranges from $xxx to $xxx according toyield variations.

The main part of the wafer cost is due to the xxxx withxxx%. The epitaxy steps represent a large part ofconsumable and equipment cost (see details in thefollowing pages).




Physical Analysis




Comparison

Feedback

About System Plus

FET Wafer Cost per process steps




Physical Analysis




Comparison

Feedback

About System Plus

FET Die Cost

The FET Component cost ranges from $xxx to $xxxaccording to yield variations.

The Front-end manufacturing represents xxx% of thecomponent cost (medium yield estimation).

Probe test, dicing and scrap account for xxxx% of thecomponent cost.

61%

6%

6%

0%

27%

Die Cost Breakdown (Medium Yield)

Front-End Cost BE : Solder Bumps Cost

BE : Probe Test BE : Dicing Cost

BE : Yield losses

Cost Breakdown Cost Breakdown Cost Breakdown

Front-End Cost $1 272.78 82.7% $1 256.79 83.1% $1 234.24 83.5%

BE : Solder bumps Cost $129.73 8.4% $118.21 7.8% $106.79 7.2%

BE : Probe Test Cost $129.73 8.4% $129.73 8.6% $129.73 8.8%

BE : Dicing Cost $7.41 0.5% $7.41 0.5% $7.41 0.5%

Total Wafer Cost $1 539.64 100% $1 512.13 100% $1 478.17 100%

Nb of potential dies per wafer 3 884 3 884 3 884

Nb of good dies per wafer 2 650 2 854 3 060

Front-End Cost $0.328 56.4% $0.324 61.1% $0.318 65.8%

BE : Solder Bumps Cost $0.033 5.7% $0.030 5.7% $0.027 5.7%

BE : Probe Test $0.033 5.7% $0.033 6.3% $0.033 6.9%

BE : Dicing Cost $0.002 0.3% $0.002 0.4% $0.002 0.4%

BE : Yield losses $0.185 31.8% $0.141 26.5% $0.102 21.2%

Die Cost $0.581 100% $0.530 100% $0.483 100%

Low Yield Medium Yield High Yield




Physical Analysis




Comparison

Feedback

About System Plus

68%

4%1%

12%

2%

13%

Die Cost Breakdown (Medium Yield)

Front-End Cost BE : Probe Test BE : Backgrinding Cost

BE : Bumping Cost BE : Dicing Cost BE : Yield losses

IC Die Cost

The die cost is estimated between $xxx and $xxx according to the yield.

Silicon cost accounts for xxx% of the cost.

The probe test, backgrinding and dicing represent xxx% of the cost.

The scrap cost (xxx%) is the total of all the losses during the back-end process.


Front-End Cost $225.61 79.1% $223.23 79.0% $220.91 78.8%

BE : Probe Test Cost $11.54 4.0% $11.54 4.1% $11.54 4.1%

BE : Backgrinding Cost $2.11 0.7% $2.11 0.7% $2.11 0.8%

BE : Bumping Cost $40.47 14.2% $40.47 14.3% $40.47 14.4%

BE : Dicing Cost $5.38 1.9% $5.38 1.9% $5.38 1.9%

Total Wafer Cost $285.11 100% $282.73 100% $280.41 100%

Nb of potential dies per wafer 4 460 4 460 4 460

Nb of good dies per wafer 3 774 3 863 3 952

Front-End Cost $0.051 67.0% $0.050 68.4% $0.050 69.8%

BE : Probe Test $0.003 3.4% $0.003 3.5% $0.003 3.6%

BE : Backgrinding Cost $0.000 0.6% $0.000 0.6% $0.000 0.7%

BE : Bumping Cost $0.009 12.0% $0.009 12.4% $0.009 12.8%

BE : Dicing Cost $0.001 1.6% $0.001 1.6% $0.001 1.7%

BE : Yield losses $0.012 15.4% $0.010 13.4% $0.008 11.4%

Die Cost $0.076 100% $0.073 100% $0.071 100%





Physical Analysis




Comparison

Feedback

About System Plus


Unpacking PCB + dies $0.0000 0.0% $0.0000 0.0% $0.0000 0.0%

Cleaning PCB $0.0600 7.6% $0.0600 7.8% $0.0600 8.0%

Dispense $0.1400 17.8% $0.1400 18.2% $0.1400 18.6%

Flip chip FET $0.0100 1.3% $0.0100 1.3% $0.0100 1.3%

Flip chip ASIC $0.0100 1.3% $0.0100 1.3% $0.0100 1.3%

Placing Capa $0.0000 0.0% $0.0000 0.0% $0.0000 0.0%

Reflow of die on PCB $0.0500 6.4% $0.0500 6.5% $0.0500 6.7%

Void test (X-Ray inspection ) $0.0200 2.5% $0.0200 2.6% $0.0200 2.7%

Underfill $0.2000 25.5% $0.2000 26.1% $0.2000 26.6%

Curing $0.0900 11.5% $0.0900 11.7% $0.0900 12.0%

DBC+die Cleaning + rinsing + drying $0.0800 10.2% $0.0800 10.4% $0.0800 10.6%

Encapsulation molding $0.0200 2.5% $0.0200 2.6% $0.0200 2.7%

Post-mold Curing $0.0100 1.3% $0.0100 1.3% $0.0100 1.3%

Yield losses Cost $0.0946 12.1% $0.0774 10.1% $0.0617 8.2%

Package Manufacturing Cost $0.785 100% $0.767 100% $0.752 100%

Package ManufacturingLow Yield Medium Yield High Yield

Packaging Cost


FET Die Cost $1.162 $1.060 $0.966

ASIC Die Cost $0.0755 $0.0732 $0.0710

PCB Cost $0.6800 $0.6800 $0.6800




Physical Analysis




Comparison

Feedback

About System Plus

Component Cost

The component cost ranges from $xxx to $xxx accordingto yield variations.

The FET die manufacturing represents xxx% of thecomponent cost.

The IC die manufacturing represents xxx% of thecomponent cost.

The packaging represents xxx% of the component cost.

Final test and yield losses account for xxx% of thecomponent cost.


FET Die cost $1.162 54.4% $1.060 53.0% $0.966 51.5%

ASIC Die Cost $0.076 3.5% $0.073 3.7% $0.071 3.8%

Packaging cost $0.785 36.7% $0.767 38.4% $0.752 40.1%

Final test & Calibration cost $0.060 2.8% $0.060 3.0% $0.060 3.2%

Yield losses cost $0.053 2.5% $0.040 2.0% $0.028 1.5%

Component Cost $2.135 100% $2.000 100% $1.877 100%


53%

4%

38%

3% 2%

Component Cost Breakdown (Medium Yield)

FET Die cost ASIC Die Cost

Packaging cost Final test & Calibration cost

Yield losses cost




Physical Analysis


Cost Analysis


Comparison

Feedback

About System Plus

Estimated Manufacturer Price

The component manufacturing cost rangesfrom $xxx to $xxx according to yield variations.

The component selling price ranges from $xxto $xxxx according to yield variations.

Gross Margin 61.7%

TI


Component cost $2.135 $2.000 $1.877

Manufacturer Gross Profit $3.440 +62% $3.222 +62% $3.024 +62%

Component price $5.576 $5.223 $4.901


$ 0.000

$ 1.000

$ 2.000

$ 3.000

$ 4.000

$ 5.000

$ 6.000


$ 2.135 $ 2.000 $ 1.877

$ 5.576$ 5.223

$ 4.901

Cost & Price According to Yield Variation

Component cost Component price




Physical Analysis


Cost Analysis


Comparisono Transphorm, GaN System

and Panasonic 600V GaN FET

Feedback

About System Plus

Comparison between Transphorm, GaN Systems,Panasonic and TI GaN FET package

FET Packaging Size Pakage Cost

PGA26E19BA DFN 8 8x8x1.25 $xx

GS66504B GaNpx embedded 8.7x10x0.47 $xx

TPH3206PS TO220D cascode 14x10x4.5 $xx

LMG5200 QFM 8x6x0.9 $xx

PGA26E19BA

TPH3206PS

GS66504B

The packaging has an high impact on thefinal cost and performances of thedevices.

The device of TI, even if it has anintegrated driver, the cost competitive.

TI LMG5200




Physical Analysis


Cost Analysis


Comparison

Feedback

About System Pluso Company serviceso Related reportso Contacto Legal

REVERSE COSTING ANALYSES - SYSTEM PLUS CONSULTING

Power Semiconductors & Compound• Panasonic PGA26C09DV 600V GaN HEMT• Transphorm TPH3002PS 600V GaN on Silicon HEMT• GaN Systems – 650V GaN on Silicon HEMT AT&S ECP®

Embedded Power Die Package

Related Reports

MARKET AND TECHNOLOGY REPORTS - YOLE DÉVELOPPEMENT

POWER ELECTRONICS• Power GaN 2017: Epitaxy, Devices, Applications, and Technology

Trends• Gate Driver Market and Technology Trends 2017

PATENT ANALYSIS - KNOWMADE

POWER ELECTRONICS• GaN Devices for Power Electronics Patent Investigation

http://www.systemplus.fr/reverse-costing-reports/panasonic-pga26c09dv-600v-gan-hemt/

http://www.systemplus.fr/reverse-costing-reports/transphorm-tph3002ps/

http://www.systemplus.fr/reverse-costing-reports/transphorm-tph3002ps/

http://www.systemplus.fr/reverse-costing-reports/gan-systems-gs66508p-650v-hemt-3/

https://www.i-micronews.com/category-listing/product/igbt-market-and-technology-trends-2017.html

https://www.i-micronews.com/category-listing/product/power-module-packaging-material-market-and-technology-trends-2017.html

http://www.knowmade.com/downloads/gan-devices-for-power-electronics-patent-investigation/


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Physical Analysis


Cost Analysis


Comparison

Feedback


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Reports(>40 reports per year)

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Physical Analysis


Cost Analysis


Comparison

Feedback


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