CERN PS/CO/Note 2001-014 (Tech.) European Lab for Particle Physics

Pascal Fernier Javier Serrano

December 10, 2001

The CTF3 delay card

An 8-channel VME module to delay TTL pulses in 200 ps steps

P. Fernier, J. Serrano

Abstract

A new VME module has been developed in the PS Division to allow fine synchronization of pulses used for the CTF3 timing system. The module features one clock input which can be delayed by 0 to 255 steps of a variable size, currently 200 ps. This step delay is actually calibrated with 8 variable resistors (one per channel) and can range from 17 to 370 ps. The 200 ps value has been chosen in our first application to give a full range of 50 ns corresponding to the RF period in the CTF3. Each channel has an independent gate input and its output is the delayed version of the tick of the clock coming immediately after the gate is enabled. This allows the user to delay TG8 pulses by using them as gates, therefore relying on the jitter-free clock signal and not on the TG8's output which can have a jitter of as much as 1 ns. There is also a transparent mode in which gates are not taken into account. The main limitation is that the clock input is common to all delay channels but this is exactly what was needed in the CTF3.

Although the module uses EGL logic internally, its interface to the external world is TTL for the clock

input and the delayed outputs. The gate inputs are TTL but they can be changed to TTL by reprogramming the on-board FPGA. A separate TTL input is used to globally enable/disable the module. When not used, the module is permanently enabled.

The present document gives a brief explanation of the CTF3 timing system followed by a detailed description of the new module both from a structural and a functional perspective.

Table of contents

The CTF3 Delay module: a functional overview ............................................ 3

A detailed look at the CTF3 Delay module internals ...................................... 5

The ECL core logic ................................................................................... 5

Measured performance ............................................................................ 6

Conclusion ...................................................................................................... 7

Acknowledgements ........................................................................................ 7

Appendix B. The FPGA design's source code in AHDL. .............................. 8

2

The CTF3 Delay module: a functional overview

For reasons of klystron output stability, the CTF3 timing must be synchronized to the zero crossings of the 50 Hz network. This means that all pulses used to synchronize equipment are the result of counting 19 MHz RF ticks from a zero crossing. This counting is done with the PS standard timing receiver and counter module: the TG8.

The exact layout proposed1 actually includes the generation of the 19 MHz from a 3 GHz synthesizer through a chain of dividers. However, some parts of the CTF3, namely the gun timing, require a precision and granularity which are out of reach for a TG8. A different layout had to be proposed for this subpart. Figure 1 outlines the strategy to deliver pulses with a precision of 200 ps.

Clock

TG8 output

Delayed output (falling edge used)

Delayed output (rising edge used)

--~~~~~~~~~-+-~~~~---'

time

• Figure 1. The first active edge of the clock after the TGB pulse is delayed. The rising/falling edge setting is jumper selectable in the delay module.

The TG8 output is open-collector and this fact is used for wire-oring different outputs in many applications. However, the open collector driver has a jitter of 1 ns at its output with respect to the clock being counted. To avoid this jitter, the delay card actually uses the TG8 pulse as a gate and delays the next edge of the clock. This edge can be rising or falling but the setting is done once for all channels through an on-board jumper.

1 "Proposal for CTF3 Timing System" J.C. Bau, J.M. Bouche, J. H. Lewis, J. Serrano, J.P. H. Sladen. Available at http://cern.web.cern.ch/CERN/Divisions/PS/CTF3/Notes/ctf3-021.pdf

3

From the VME side, the card is an A 16/016 slave with 16 registers. Eight of them are used to program an 8-bit delay value for each channel and the other eight correspond to the channel modes. Four modes are currently available:

• In ALWAYS ON mode, every tick at the module's clock input is delayed and produces a pulse.

• ALWAYS OFF is the most trivial mode ever. The channel just sits at zero volts.

• ONCE mode is the one used for the CTF3. The first tick of the clock after the falling edge of the corresponding gate input is delayed.

• In GATE mode, all pulses coming to the clock input while the corresponding gate is low are delayed.

• Figure 2. Front and component views of the card. Lerno connectors from top to bottom: global enable, clock input, eight pairs of gate input and delayed output plus a sigma output containing the sum of all delayed outputs.

4

' A detailed look at the CTF3 Delay module internals

The original specifications of the card called for a range of 51 ns to be split into 255 steps. This range corresponds to the period of the CTF3 radio frequency waveform, so that we are able to position a pulse anywhere within the cycle by counting 19 MHz ticks with a TG8 and feeding the output to our fine delay module. Because the TGB's output is used

as the gate, the electrical standard chosen is TTL . The global enable input (TTL active high) defaults to a high state when left floating, so the user must drive it low to disable the module.

The clock input is terminated to 50Q internally to avoid reflections. This setup works nicely with the new clock fan-out card2. If the clock is to be daisy chained from one module to another, then too much load is imposed on the clock signal and resistor R5 should be unsoldered so that the clock signal is only terminated at the end of the daisy chain. The active edge of the clock to be delayed is defined through jumper ST1 . No jumper means negative edge, and this is the standard setting chosen for the CTF3.

All delayed outputs and the sigma output are produced by 50Q drivers (7 4F3037D by Philips) and should be therefore properly terminated at the receiving end of the cable.

Powering is an issue that deserves attention, since ECL logic is quite a big consumer of the -5.2V supply voltage. In our card, this supply is taken from a special third connector in the VME backplane. This means that this card will only work in one of the special crates where the extra -5.2V supply is available in the center connector.

An Altera EPM7128 FPGA is used for the VME interface, with an on-board 10-pin connector which allows downloading of new designs. An 8-bit DIP switch is used to set bits A 15 through AB of the VME address of the module3. The EPM7128 is powered with a LM3940 3.3V regulator.

The ECL core logic

The heart of the card is a set of eight Analog Devices AD9500 chips. These devices generate a voltage ramp and compare it to the output of an internal DAC. The ramp being triggered by the chips trigger input, the output of the comparator is a delayed version of that input. The delay is set digitally by the FPGA via a write operation to one of the AD9500 internal registers (actually the input to the DAC).

2 Details of any of these cards can be found in the PS/CO hardware EDMS pages: http://edmsoraweb.cern.ch:8001/cedar/navigation.tree?top=1480116946&open=1480116946 3 Beware! Bit AB is on the left hand side and bit A 15 on the right. It's written on the board but still worth remembering.

5

The eight chips share a data bus and are differentiated through chip select signals. One critical part of the design was controlling the slew rate of the signals on the data lines because too high a rate can perturb chips even when their chip selects are inactive. This was achieved through a combination of series resistors and parallel capacitors on the data lines.

The slope of the internal voltage ramp is set by an external combination of one capacitor and one resistor. This in turn determines the full range delay of the channel. We chose to use eight variable 5K resistors (one per channel) to provide the most versatile solution. For CTF3 they are all set at a value of 2.7K.

The interface to the outside world is handled by On Semiconductor's ECL-to-TTL and TTL-to-ECL translators.

Measured perfonnance

Figure 3 shows a screen shot of a jitter measurement using Lecroy's LC564DL digitizing oscilloscope.

13-0ec-81 10:55: 15

B Reeding Floppy Disk Drive

B :::::::::::~::::::::::::::::::::of~

~Hdeley(3) 2 ns .88 kl! /.h8/. in 381584

28 ns 1 trig only

1 V DC 3 1 V 50Q

trig only

delayC3J evg(A) l sigMeCAl l FwhMCA) l rengeCAl l

58. 18 ns 58. 8575 ns

71.5 ps 153.8 ps 555.8 ps

2 DC I. 52 V

A

D

4 GS/s

STOPPED

• Figure 3. Trace 2 shows the negative edge at the clock input of the module. Trace 3 is the delayed pulse and trace A is a histogram of the distributions of delays of 3 with respect to 2. It's made of 301504 acquisitions and displayed on a time base of 0.2 ns per division.

Sigma( A) is the standard deviation as defined in ~ L ~ - Xi J where ~ is the average

of the distribution and X; are each of the samples. We take this sigma of 71.6 ps as an

indicator of performance and the range of 656 ps as a worst-case figure.

6

Conclusion

A digitally controlled delay card has been designed in the VME format to produce time­critical pulses for the control of the CTF3. This card can delay any TTL pulse by a variable number (O to 255) of steps, which are themselves of variable size. This step size is set with external variable resistors and is currently set at 200 ps for the CTF3 timing.

A laboratory test under realistic conditions shows a jitter with respect to the clock input of 71.6 ps in average and 656 ps worst-case.

Although the card has been tailored to the needs of the CTF3 machine, versatility has been emphasized both in software (different operating modes) and hardware, thus making it a candidate for use in any situation where a TG8 counts RF ticks and its output must be delayed.

Acknowledgements

Many thanks to:

• Wolfgang Heinze, for help in debugging the on-board data bus issue and many others.

• Julian Lewis and Jean-Marc Bouche, the clients for this card, for relentless testing of the card and commitment to the CTF3 timing.

• Jonathan Sladen, for his RF expertise, especially in ECL issues.

• Gabriel Metral for sharing his wonderful oscilloscope with us.

7

Appendix B. The FPGA design's source code in AHDL.

TITLE "A VME interface for the VME fine delay card";

INCLUDE "lpm_mux.inc";

SUBDESIGN vmeintrf (

/vlword, /viack, /vwrite, /vdsO, vsysclk, /vsysreset : INPUT; vaddress[15 .. 1], vam[5 .. 0], board_address[15 .. 8] : INPUT; vdata[15 .. O]

: BIDIR; ad_delay[7 .. 0], ad_cs[7 .. 0] : OUTPUT; vdtack, vme_access, sigma_led : OUTPUT; gates[7 .. 0], ad_out[7 .. 0], glob_enable

INPUT; ad_reset[7 .. 0]

: OUTPUT; dir, /enable

: OUTPUT;

VARIABLE

ss: MACHINE WITH STATES (idle, s1, s2, s3); write[7 .. 0] : NODE; reset, thatsme, oe : NODE; mem[7 .. 0][2 .. 0] : OFF; data_bus[15 .. 0] : TRI; clock_d, glob_go : NODE; delay[7 .. 0] go_edge[7 .. 0]

: DFF; :NODE;

ff1 [7 .. 0] ff2[7 .. 0]

BEGIN

glob_go = glob_enable; vme_access = vdtack;

: OFF; : OFF;

sigma_led = (ad_out[7] # ad_out[6] # ad_out[5] # ad_out[4) # ad_out[3] # ad_out[2] # ad_out[1] # ad_out[O]);

data_bus[2 .. 0].in = lpm_mux(mem[J[).q, vaddress[3 .. 1], , , )

LPM_WIDTHS=3); data_bus[15 .. 3].in = GND; data_busO.oe = oe; vdataD = data_busO;

delay[].d = vdata[7 .. 0]; delay[].clk = clock_d;

WITH (LPM_WIDTH=3, LPM_SIZE=8,

8

ad_delayO = delay[].q;

ad_csO = !writeO;

mem[][].clrn = GLOBAL(/vsysreset); mem[][2 .. 0].d = vdata[10 .. 8];

mem[O][].clk = write[O]; mem[1][].clk = write[1]; mem[2][].clk = write[2]; mem[3][].clk = write[3]; mem[4JO.clk = write[4]; mem[5][].clk = write[5]; mem[6][].clk = write[6]; mem[7][].clk = write[?];

ad_reset[7] = !(((mem[7][0] & !ad_out[7]) # (mem[7][1] & !gates[?] & !ad_out[7]) # (mem[7][2] & go_edge[7])) & glob_go);

ad_reset[6] = !(((mem[6][0] & !ad_out[6]) # (mem[6][1] & !gates[6] & !ad_out[6]) # (mem[6][2] & go_edge[6])) & glob_go);

ad_reset[5] = !(((mem[5][0] & !ad_out[5]) # (mem[5][1] & !gates[5] & !ad_out[5]) # (mem[5][2] & go_edge[5])) & glob_go);

ad_reset[4] = !(((mem[4][0] & !ad_out[4]) # (mem[4][1] & !gates[4] & !ad_out[4]) # (mem[4][2] & go_edge[4])) & glob_go);

ad_reset[3] = !(((mem[3][0] & !ad_out[3]) # (mem[3][1] & !gates[3] & !ad_out[3]) # (mem[3][2] & go_edge[3])) & glob_go);

ad_reset[2] = !(((mem[2][0] & !ad_out[2]) # (mem[2][1] & !gates[2] & !ad_out[2]) # (mem[2][2] & go_edge[2])) & glob_go);

ad_reset[1] = !(((mem[1][0] & !ad_out[1]) # (mem[1][1] & !gates[1] & !ad_out[1]) # (mem[1][2] & go_edge[1])) & glob_go);

ad_reset[O] = !(((mem[O][O] & !ad_out[O]) # (mem[0][1] & !gates[O] & !ad_out[O]) # (mem[0][2] & go_edge[O])) & glob_go);

ff1 O.d = VCC; ff1 [].elk= !gatesO; go_ edge[] = ff1 [].q; ff1 [].clrn = (!ff20.q) & glob_go;

ff20.d = VCC; ff20.clk = ad_outO; ff2[].clrn = go_edge[] & glob_go;

reset = /vdsO # !/vsysreset; thatsme = /vlword & ((vamO==H"29") # (vam[]==H"2D")) &

(vaddress[15 .. 8]==board_address[]) & /viack;

dir = /vwrite;

SS.elk= GLOBAL(vsysclk); ss.reset =reset;

9

% This is a Mealy state machine, that is, the current output depends on both the current state and the current input (vwrite) %

TABLE

% current current current next %

% state inputs outputs

%

ss, thatsme, /vwrite, vaddress[3 .. 1] => write[7 .. 0], clock_d, ss;

idle,O, x,x => 0, 0, 1, 0, 0, idle; idle,1, X,X

s1,x,x,x s2, x,0,0 s2, x,O, 1 S2, X, 0, 2 S2, X, 0, 3 s2, x, 0, 4 s2, X, 0, 5 S2, X, 0, 6 s2, X, 0, 7 s2, x, 1,x S3, X, 0, 0 s3, x,O, 1 S3, X, 0, 2 S3, X, 0, 3 S3, X, 0, 4 s3, x,O, 5 s3, x, 0, 6 S3, X, 0, 7 s3, x, 1,x

END TABLE;

END;

=> 0, 0, 1, 0, 0, s1; => 0, 0, 0, 0, 0, s2; => 0, 0, 0, 1 , 1, s3; => 0, O, O, 2, 1, s3; => 0, 0, 0, 4, 1, s3; => 0, 0, 0, 8, 1, s3; => 0, 0, 0, 16, 1, s3; => 0, 0, 0, 32, 1, s3; => 0, 0, 0, 64, 1, s3; => 0, 0, 0, 128, 1,s3; => 1, 0, 0, 0, 0, s3; => 0, 1, 0, 1 , 0, s3; => 0, 1, 0, 2, 0, s3; => 0, 1, 0, 4, 0, s3; => 0, 1, 0, 8, 0, s3; => 0, 1, 0, 16, 0, s3; => 0, 1, 0, 32, 0, s3; => 0, 1, 0, 64, 0, s3; => 0, 1, 0, 128, 0, s3; => 1, 1, 0, 0, 0, s3;

10

state

oe, vdtack, /enable,