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ECL& INSTRUMENTATIONINTEGRATEDCIRCUITHANDBOOK

PLESSEYW SemiconductorsyJtvww)

ECL& INSTRUMENTATIONINTEGRATEDCIRCUITHANDBOOK

Designed and produced by Peter Wigens Consultants

©The Plessey Company Limited

July 1981

Publication No. P.S.1912

This publication is issued to provide outline information only and (unless specifically

agreed to the contrary by the Company in writing) is not to form part of any order or

contract or be regarded as a representation relating to the products or services

concerned. We reserve the right to alter without notice the specification, design, price

or conditions of supply of any product or service.

Contents

Product index

Page5

SP8000 reference data 7

Quality data

Semi-custom design

Technical data

11

14

17

Package outlines

Ordering information

Plessey World-Wide

105

108

109

Product IndexTYPE NO. DESCRIPTION EQUIVALENT PAGI

SP705B 1 to 10MHz TTL crystal oscillator 19

SP761B 5 relay drivers (12V) 21

SP762B 5 relay drivers (5V) 21

ECL III

8P1648 Voltage controlled oscillator MC1648 25

SP1650 Dual A-D comparator (Hi Z) MC1650 31

SP1651 Dual A-D comparator (Lo Z) MC1651 31

SP1658 Voltage controlled multivibrator MC1658 41

SP1660 Dual 4-l/P, OR/NOR gate MC1660 45

SP1662 Quad 2-l/P NOR gate MC1662 47

SP1664 Quad 2-l/P OR gate MC1664 49

SP1666 Dual clocked R-S flip-flop MC1666 51

SP1668 Dual clocked latch MC1668 55

SP1670 Master-slave D-type flip-flop MC1670 59

SP1672 Triple 2-l/P exclusive OR gate MC1672 65

SP1674 Triple 2-l/P exclusive NOR gate MC1674 67

SP1692 Quad line receiver MC1692 69

Fast ECLSP16F60 550ps dual 4-l/P OR/NOR gate MC1660* 71

SP16F70 350MHz D-type flip-flop MC1670* 73

SP9131 550MHz dual D-type master-slave

flip-flop

MC10131* 75

Data ConversionSP9680 Unlatched high speed comparator 79

SP9685 Latched high speed comparator AM685* 81

SP9687 Dual latched high speed comparator AM687* 85

SP9750 Decoded high speed comparator /ADC/DAC 89

SP9752 2-bit ADC 93

SP9754 4-bit ADC 97

SP9768 8-bit DAC 101

*TheSP16F60, SP16F70, SP9131, SP9685 and SP9687 are pin-compatible higher performance

versions of the equivalents shown.

SP8000 series high speed dividersEssential data for the SP8000 series high speed dividers is given below. Full

technical data for these products is published separately in Plessey SemiconductorsSP8000 series High Speed Dividers Handbook.

Plessey Semiconductors' SP8000 series leads the world in technical performance.

One of the most comprehensive ranges of dividers available, the SP8000 series has

been developed and extended to cater for the exacting requirements of the

instrumentation and communications markets. The range includes prescalers from

divide-by-2 up to divide-by-256, operating from 1Hz to 1.5GHz.

Suffix A Military -55°C to +125°CSuffix M Intermediate -40°C to +85°CSuffix B Commercial -30°C to +70 JC

(0°C to +70°C in some cases)

FIXED MODULUS PRESCALERS

>>

•o>5

Type

remperature

XZ>.ocCO3

lXCB

S

Supply

<E

c83O>•

aa3</>

Output Package

cegu"3

•2

isO

un

a.

-55

+ 125

-40

+85

-30

+ 70 + 70 5.0 5.2 6.8 7.4 i-oUJ

2

SP8604A

SP8604B

SP8602A

SP8602B

SP8607A

SP8607B

SP8605A

SP8605B

SP8606A

SP8606B

•

•

•

•

•

•

•

•

•

•

300

300

500

500

600

600

1000

1000

1300

1300

12

12

12

12

14

14

70

70

70

70

••••

4

SP8790A

SP8790B

SP8601A

SP8601B

SP8600A

SP8600B

SP8610A

SP8610B

SP8617MSP8617B

SP8611A

SP8611B

SP8619MSP8619B

•

•

•

•

•

•

•

•

•

•

•

•

•

•

60

60

150

150

250

250

1000

100Q

1300

1300

1300

1500

1500

1500

••

••

••

8

8

18

18

16

16

70

70

80

80

70

70

80

80

••••••

5SP8620A

SP8620B•

•400

400

••

55

55

FIXED MODULUS PRESCALERS (CONTINUED)

>ae'>

5

Type

Temperature

XS>iuc•3ST

X«2

Supply

<

cs3U><

a.a.3CO

Output Package

cISua•2

oE5•

o

aa

-55

+ 125

-40+ 85

-30+70 + 70 5.0 5.2 6.8 7.4 i-

_io111

SP8794A • 120 • 10 • •SP8794B • 120 • 10 • •SP8670A • 600 45

8 SP8670B

SP8735B

SP8675B

SP8678B

••••

600

600

1000

1500

••

45

70

70

70

®

10

SP8660A

SP8660B

SP8660

SP8632B

SP8637B

SP8630A

SP8630B

SP8635B

SP8634B

SP8665B

SP8668B

•

•

•••

•

•

••••

150

150

150

400

400

600

600

600

700

1000

1500

•••

••

10

10

10

70

75

70

70

75

75

80

80

•••

®

®®

••

••

•

16

SP8659A

SP8659B

SP8650A

SP86S0B

•

••

•

200

200

600

600

••

10

10

45

45

••

••

••

20SP8657A

SP8657B

SP8658

•••

200

200

200

•••

10

10

20

••• •

32SP8655A

SP8655B

••

200

200

••

10

10

••

SP87S5A • 1200 • 45 • •64 SP8755B

SP8757

••

1200

1200

••

45

45

••

••

100SP8628

SP8629

••

150

150

••••

33

33

••

••

256 SP8775 • 1200 • 70 • •

B) = Binary outputs

VARIABLE-MODULUS PRESCALERS

The two-modulus dividers will divide by either of two ratios according to the state of

a control input compatible with ECL, TTL or CMOS as shown. Further division ratios

can be obtained by means of extra prescalers. For example, by using the SP8790 (+4)

or SP8794 (*8) — which are specially designed for extending the ratio of two-modulusdividers and have TTL compatible control inputs — it is possible to extend a -MO/1 1 to

40/41 or 80/81 respectively.

Use of variable modulus dividers to obtain fixed division ratios.

Any of the variable modulus dividers can be simply connected to divide

permanently by either modulus. For example the SP8691 +8/9 can become a fixed -8

or +9 by hardwiring the appropriate programming pins. This technique (described in

the datasheets) extends the range of fixed prescalers to include division ratios of 3, 6,

7,9, 11,22, 40, 41, 80 and 81.

>•

O•a>5

Type

Temperature

NXs>>ueo3

1Xcs

2

Supply

<

cS3O>>

a.a.3(A

Control OutputPackage

cao

•

oES•

»as

CL

-55

+ 125

-40+85

-30+70 + 70 5.0 5.2 6.8 7.4

_i _iuUJ

_i _ioIU

% SP8720A

SP8720B• 300

300

40

40

% SP8740A

SP8740B

• 300

300

45

45

H SP8741A

SP8741B• 300

300

45

45

%SP8691A

SP8691B

SP8743A

SP8743B

•

•

200

200

500

500

••

14

14

45

45

••

10.

4i

SP8690A

SP8690B

SP8647A

SP8647B

SP8643A

SP8685A

SP8685B

SP8680A

SP8680B

•

•

••

••

200

200

250

250

350

500

500

600

600

•••••

••

14

14

50

50

50

45

45

90

90

••••

••

•

i2

SP8785A

SP8785BSP8786A

SP8786B

•

••

•

1000

1000

1300

1300

85

85

85

85

VARIABLE-MODULUS PRESCALERS (CONTINUED)

><JB•

>5

Type

Temperature

zz>^oS3

IX

Z

Supply

<

c

3U>.

aa3

Control

inputOutput Package

c•o

•Z

uEa•O

o

•cl

-ss+ 125

-40

+ 85

-30+ 70 + 70 5.0 5.2 6.8 7.4

-ioui

-joUJ

4Q SP8793A

SP8793•

•200

225

••

4

4

••

••

••

SP8792A

SP8792•

•200

225

••

4

4

••

••

••

10

Quality dataPlessey Semiconductors have an active BS9300 and BS9400 qualification approval

programme on a number of products.

Additionally, Plessey Semiconductors are keen to co-operate in pursuing BS9000approval on any of the products which it manufactures.For further information contact the Military Marketing Group at Swindon.

Plessey Semiconductors QA offers:

a) Factory Approval to

BS9300 for semiconductor devices of Assessed Quality (BSI

Certificate 1053/M)BS9400 for integrated circuits of Assessed Quality (BSI Certificate

1053/M)CECC 50000 Inspection Organisation to document level 1 (BS9300)M0020/CECC refers

DEF STAN 05—21 QC System requirements for Industry (Equivalent to

AQAP— 1) Certificate 65752/1/01 refers

b) Additional Release Conditions to

6/49 Defence Quality Assurance Board Certificate (DQAB 38020)MOD (N) Navy Department Inspection Authority

or

Private Sales Plessey's own Certificate of Conformance

Devices are also manufactured, tested and supplied to MIL-STD-833, the USMilitary Standard; Test Methods and Procedures for Microcircuits, and MIL-M-38510, US Military Specification, Micro-electronics; General Specifications for.

11

Screening to BS9400PRODUCTION BATCH

CATEGORY S2 CATEGORY S3 CATEGORY S4 FULL ASSESSMENTSCREENING LEVEL SCREENING LEVEL SCREENING LEVEL LEVELBCD

I

(1) Internal visual

examination

(2) High temper-ature storage

(3) Rapid changeof temperature- air

(5) Acceleration

(6) Leak test

(7) Electrical tests

(8) Burn-in screen

(11) Final

electrical tests

10% maximum de-fectives allowedbetween electrical

tests (7) and (11).

(1) Internal visual

examination

(2) High temper-ature storage

(3) Rapid changeof temperature- air

(5) Acceleration

(6) Leak test

(7) Electrical tests

(8) Burn-in screen

(11) Final

electrical tests

(11) Final

electrical tests

10% maximum de-fectives allowedbetween electrical

tests (7) and (11).

Inspection lot formed

(11) Final

electrical tests

Sample test to group A,B,C and D as appropriate

DESPATCH

12

Screening to MIL-STD-883

The following Screening Procedures are available from Plessey Semiconductors

CLASSS

PRE CAPVISUAL

I

STABILIZATIONBAKE

THERMALSHOCK

l ~TEMPERATURE

CYCLINGI

~CENTRIFUGE

VISUALINSPECTION

HERMETICITY

P.I.N.D.

SERIALIZATION

RADIOGRAPHIC

INTERIMELECTRICAL TEST

BURN-IN

FINALELECTRICAL TEST

CLASSB

CLASSC

PRE CAPVISUAL

PRE CAPVISUAL

STABILIZATIONBAKE

STABILIZATIONBAKE

TEMPERATURECYCLING

TEMPERATURECYCLING

CENTRIFUGE

ICENTRIFUGE

VISUALINSPECTION

VISUALINSPECTION

HERMETICITY HERMETICITY

INTERIMELECTRICAL TEST

BURN-IN



STANDARDPRODUCTS

PRE CAPVISUAL

STABILIZATIONBAKE

CENTRIFUGE

VISUALINSPECTION

HERMETICITY


QUALIFICATIONOR CONFORMANCE

TESTING AS REQUIRED

'Plessey Semiconductors reserve the right to change the Screening Procedure for Standard

Products.

13

Semi-custom designSemi-custom design techniques give users the advantages of integrated circuits

dedicated to their applications without incurring the costs associated with full customdesign. The techniques are particularly attractive to users with a low-to-moderateannual production potential of 1000 to 100,000 pieces, although these limits areflexible and may depend on the individual circuit.The economics of 'when to choosesemi-custom' are illustrated in Fig.1.

Plessey Semiconductors offer semi-custom facilities in N-Channel MOS, CMOSand Bipolar technologies, using the techniques of Microcell, Gate Arrays andAnalogue Arrays, the essential characteristics of which are detailed in Table 1.

PRODUCTION PRICEPER CIRCUIT

(INCAMORTISEDDEVELOPMENT)ABITRARY UNITS

STANDARD ICs

TYPICALTARGET PRICE

CURVE

FULL CUSTOM DESIGN

SEMI-CUSTOMDESIGN

CIRCUIT USEAGE (PER ANNUM)

Fig 1 Areas of application of different categories of integrated circuits

MICROCELLMicrocell is a combination of standard cells with a formalised gate and

interconnection procedure. It uses a computer library of gates and other cells whichthe designer calls up as required, leaving as much or as little space for

interconnection as the design necessitates. Each circuit is exactly the right size for its

14

function, and layout for the interconnection pattern is both straightforward and fast

because of the error-correcting digitising technique employed.

The main features of Microcell can be summarised as follows: • From logic

diagram to first samples in less than four months • Very high design integrity • Acircuit can be produced by any competent logic designer • Minimal extra

engineering effort is required • Clock rates of up to at least 2MHz are

achievable • Advances in semiconductor technology and circuit design ideas can

easily be absorbed into Microcell.

GATE ARRAYSIn the Gate Array, logic elements are pre-positioned and the customer's task is to

design the interconnection of those elements (within the space allocated) to achieve

the required functions. The cells are not necessarily committed to logic functions, but

may in some cases be connected to form simple linear functions. Layout aids andsoftware routines are normally used extensively to assist in the design, verification

and testing of these structured devices.

Plessey Semiconductors offer Gate Array techniques in CMOS and ECL. CMOSGate Arrays offer the following features: • High Speed ISO-CMOS Silicon Gate

technology, giving a typical propagation delay of 6ns for a 2-input NAND gate (at 5Vand 25°C) • Short turn round time • Inputs and outputs TTL and CMOScompatible and provided with static protection • On-chip power on reset option

available • Available to commercial, industrial and military standards.

ECL Gate Arrays - also possessing the advantages of low development charge,

increased reliability and fast delivery of samples - would be chosen mainly for the very

high speed operating capability.

ANALOGUE ARRAYSPlessey Semiconductors' Analogue Array brings Semi-Custom techniques to the

designer of linear and other analogue circuits, for applications such as signal

processing, amplification, waveform generation and function generation.

Manufactured on Bipolar Process I the analogue array features: • 159 NPNtransistors (4 high current) • 58 PNP transistors • 385 resistors • 20V breakdownvoltage • Functional compatibility with Exar and Interdesign • Single layer

customisation on a grid system • Device library and simulation facilities.

Comprehensive technical literature on all Plessey Semiconductors' Semi-CustomFacilities is available on request.

SEMI-CUSTOMOPTION

TECHNOLOGY SPEED POWERCONSUMPTION

SCALE OFINTEGRATION

TYP. LEAD TIMETO 1ST SAMPLES

NMOSMicrooHl

NMOSMetal Gate

2MHz 300mW/1000 gates 500-2500 gates 16 weeks

Low Power NMOSMicrocoN

NMOSMetal Gate

0.5MHz 50mW/1000 gates 500-2000 gates 16 weeks

CMOSMicrocell

ISO-CMOS 10MHz 0-150mW/1000 gates* 500-2000 gates 16 weeks

CMOSGate Anay

ISO-CMOS 8MHz 0-150mW/1000 gates* 560.960.1440and 2014 gates

13 weeks

ECLGate Array

BipolarProcess III

200MHz 75 gates: 900mW max300 gates: 3.5W max

75 to 600 gates 14 weeks

BipolarAnalogue Array

Bipolar

Process I

fr = 500MHz 100mW to 1W** 217 transistors 16 weeks

Depending on speedDepending on application

Table 1

15

Technical Data

17

SP705

^& Semiconductors

SP705BCRYSTAL CONTROLLED

INTEGRATED CIRCUIT

OSCILLATOR

The SP705B is a square wave oscillator circuit designed

to operate in conjunction with an AT cut quartz crystal of

effective series resistance less than 300 ohms. Four TTLoutputs are provided, related in frequency to the crystal

frequency / as follows: //2, I/A, 1/2 and I/A. The SP705B is

therefore ideally suited to either single or multi-phase TTLclock applications

FEATURES

Operating Frequency up to 10 MHzill and I/A outputs

4 TTL Level outputs

Operates from +5V TTL Supply

NC[

NC

NC

COMPENSATION

CRYSTAL <

EARTH

" ] VCC

13 ] ftt OUTPUT

12 ] t/t OUTPUT

.1 ]NC

io ] Tn output

9 ] f/2 OUTPUT

8 ] NC

DG14

Fig. 1 Pin connections

ELECTRICAL CHARACTERISTICS

Test conditions (unless otherwise stated):

VCC = +5V

Characteristic SymbolValue

Units ConditionsMin. Max.

High state output voltage

Low state output voltage

Supply current

Output rise time (10% to 90%)

Output fall time (90% to 10%)

Operating frequency (f

)

Operating temp range

V H

Vol

ice

tR

tF

2.6

0.4

35

20

20

10

70

V

V

mAns

ns

MHz°C

VCC = 4.75V

l H = 0.2 mAVCC = 5.25V

Iql = 8 mAVC c = 5VVCC = 5VVC c = 5V

19

SP705

TOTEM '<>

.TLT

"» ~LTL

TOIEM »

Fig. 2 SP70SB block diagram

CIRCUIT DESCRIPTION

The crystal maintaining circuit consists of an

emitter-coupled oscillator, with the emitter resistors

replaced by constant-current generators. The crystal is

connected, usually in series with a 20pF capacitor, between

pins 5 and 6. The 20pF capacitor can be replaced with a

mechanical trimmer to allow small changes in frequency to

be made, as shown in Fig. 3.

The circuit is designed to provide low crystal drive levels

— typically, less than 0.15mW at 5MHz. This is well within

crystal manufacturers' limit of 0.5mW.

The compensation point, pin 4 is made available so that

the compensation capacitance can be increased if necessary.

However the 14pF capacitor included on the chip is usually

sufficient to prevent spurious oscillation at high

frequencies.

Fig. 3 Circuit diagram of SP705B oscillator

'0

""''*' * *LCj'jI •* * M»/,

-10

-20

^^ i i I ^^^^ f 8 9 C

6-30 -

i -50 tvpical circuit coefficients

'temperature coefficient of circuit 0- ppm ptf°Ca lOHHi

WRTAGE COEFFICIENT OF ClRCUiT 1-4 pptr per VOL1 «»'-t MH2

-60

Fig. 4 Deviation from nominal crystal frequency

20

SP761/2

Semiconductors

,

SP761B-I2V POWER INTERFACE CIRCUIT

SP762B 5V POWER INTERFACE CIRCUIT

The SP761B and SP762B are bipolar integrated circuits,

each incorporating five current amplifiers for interfacing

between MOS/TTL devices and loads requiring high drive

currents. The SP761B is designed to operate from a +12V

supply rail and the SP762B from +5V.

Both types are provided with a strobe input which drives

two of the amplifiers so that their outputs may be

connected in parallel for higher output current capability.

The circuits operate over a temperature range of 0°C to

+70°C and are mounted in 14-lead ceramic DIL package.

Although primarily designed to drive printing solenoids

in calculators, these circuits can be used in a variety of

applications requiring high drive currents. Fig. 1 Pin connections (top)

FEATURES

Input - MOS/TTL Capability

Output - 200 mA Capability

Five Channels per Package

Open Collector Output

APPLICATIONS

Driving Solenoids

Driving Relays

Driving LEDs

Driving Filament Lamps

Driving Cores

TTL-to-MOS Translator

ABSOLUTE MAXIMUM RATINGS

Fig. 2 Functional diagram (one driver)

Output collector voltage

Supply voltage, SP761

B

Supply voltage ,SP762B

Storage temp.

Chip operating temp.

Ambient operating temp.

26V+15V+7V-55^0+125^+125tOt to +70°C

21

SP761/2


Characteristic TypeValue (note 1)

Units ConditionsMin. Typ. Max.

Supply voltage VC c SP761B 11 12 13 V See note 2

SP762B 4.5 5 5.5 V See note 2Quiescent supply current SP761B 8 mA All inputs low

On state supply current,

SP762B 10 mA All inputs low

per element Both 12 mA l| H = 1mAInput current l| H SP761B 1 4 mA l ou t

= 150mAInput voltage Vm SP761B 4 V llH = 1mAInput current l| L SP761B 50 A(A

Input voltage V| H SP762B 2.7 5.5 V l out = 200mAInput current l| H SP762B 1 mA V IH = 2.7VInput voltage V| L SP762B 1 V

Output current l out SP761B 150 mA l|H = 1mASP762B 200 mA V| H = 2.7V

Output voltage Vql SP761B 1.0 1.2 V lout = 150mASP762B 1.3 1.6 V lout = 200mA

Output voltage Vqh Both 26 VOutput breakdown voltage Both 26 V See note 3

Duty cycle SP761B

SP762B40

33

%%

All outputs at

On time 2 s

l ou tmax

NOTES1. Both 0V supply pins 1 and 7 must be connected at all times.

2. Min and max. limits apply to the temperature range 0°C to +70°C. All typical values are quoted for \/qq = Typical and Tarn t,= +25°C.

3. External clamping diodes must be used when driving inductive loads.

/SP762B,

'

/SP SIB

^^^O'C

Fig. 3 Input characteristic (including strobe) Tgmi)» +25°

C

V SAT (v)

Fig. 4 Output characteristic

I

i\

SP762b\

\SP761B

22Fig. S Operating characteristics

SP761/2

^P762B

SP761BS.^

SP762B /

/ SP76IB

Fig. 6 Operating characteristics at +7CfC SUPPLY VOLTAGE I V '

Fig. 7 On state supply current drain per element

OPERATING NOTES

Interfacing

The SP761B is designed to interface directly with MOS

devices, accepting free drain input currents in the range

1mA to 4 mA. Current limiting input resistors are

incorporated on-chip to reduce power dissipation in the

MOS circuit. The resistor is approximately 2 kJ2, giving an

input voltage of 4V at 1 mA.

Fig. 8 shows (i) a direct interface to MOS and (ii) an

interface using an external resistor to further limit input

current when driven from a high voltage source.

The SP762B will interface directly with standard TTL

over the temperature range 0°C to +70°C, a TTL logic '1'

making current available at the SP762B output. Although

TTL is not specified to source more than 400 |/A at logic

'V level, the majority of gates will in fact supply

approximately 5 mA and still maintain a logic '1' level in

excess of 2.7V. Since the input resistors of the SP762B are

approximately 600ft, then one TTL output is capable of

driving up to 5 SP762B inputs. When driving only one input

of an SP762B, the input current will limit at approximately

2 mA at 3.4V. Open-collector TTL gates can also be used to

drive the SP762B, provided that each TTL output has an

external load resistor, the value of which will depend on the

fanout required.

The characteristics of the strobe input are the same as

for the individual inputs and therefore the above comments

also apply to this input.

Unused Inputs

When using the strobe input, inputs 1 and 2 must be left

floating. However, inputs 1 and 2 can be used completely

independently in the same way as the other inputs. Any

other unused inputs can either be left floating or tied to the

negative supply rail.

Output Capability

The output capability of each channel is 150 mA for the

SP761B and 200 mA for the SP762B. With all five drivers

operating at these current levels, a duty cycle of 40% for

the SP761B and 33% for the SP762B will allow operation

over the temperature range 0°C to +70 C.

If the device is to be operated at a lower ambient

temperature, or at a lower output current, then the duty

cycle may be increased as shown in Fig. 6 and 7. Likewise,

if some of the outputs are unused the duty cycle of the

remaining outputs may be proportionally increased

provided that the drivers are used symmetrically within the

package.

The package has a thermal time constant such that the

chip temperature will rise above the permitted maximum of

+125°C if all the drivers are allowed to remain on at

maximum output current for more than 2 seconds.

The drivers will operate at up to 1 MHz but at such

frequencies the input mark/space ratio will have to be

modified because the effective output duty cycle is higher

than that at the inputs due to stored charge in the output

transistors.

(ii)

23

SP761/2

24

SP1648

Semiconductors

SP1648VOLTAGE-CONTROLLED OSCILLATOR

The SP1648 is an emitter-coupled oscillator, constructed

on a single monolithic silicon chip. Output levels are

compatible with ECL III logic levels. The oscillator

requires an external parallel tank circuit consisting of the

inductor (L) and capacitor (C).

A varactor diode may be incorporated into the tank

circuit to provide a voltage variable input for the oscillator

(VCO). The device may also be used in phase locked loops

and many other applications requiring a fixed or variable

frequency clock source of high spectral purity.

The SP1648 may be operated from a +5.0 Vdc supply or

a -5.2 Vdc supply, depending upon system requirements.

SUPPLY VOLTAGE GNDPINS SUPPLY PINS

+5.0 Vdc 7,8 1, 14

-5.2 Vdc 1, 14 7,8

•^VrInput Capacitance = 6pF typ

Maximum Series Resistance for L (External Inductance) = 50 £1 typ.

Power Dissipation = 150mW typ/pkg (+5.0 Vdc Supply)

Maximum Output Frequency = 225 Mhz typ

DG14

Fig. 1 Block diagram of SP 1648

TR3 T 7R2 ">

y EEl BIASPOINT

Fig. 2 Circuit diagram of SP1648

25

SP1648


Supply Voltage « +5.0 volts

'

-30«C

»25,>C

9»*c

TiST VOLTAGE/CUPmSNT VALUfS

VesICMI

(Vainl »A4c

v,M-w V|i»i. Vcc l L

• 1.940 • 1.410 5.0 5.0

• 1.800 • 1.300 5* 5.0

• 1.660 •I.1M 5.0 5.0

OUfWMflMiC Sy-kpl Tan

SP184S Tat Limiu TEST VOLTAOf/CUNPJCNT APPLIED TOPINS LISTED BE LOW:-30»C •2S«C •»»c

Mkt Mw Mb. Mm Mb. M«n ««n. Vil m- v« 'L

Nw» tupply Otim Cw»ant '£ 8 — — — 40 — — mAdc — — M4 — 2.8

loajc -l"

Output Vottapt

V M 3 3.94 4.H 4.04 4.25 4.11 4.36 Vo* - 12 '. '4 3 7.8

lo»«"0-Outeut Vottafa

v0t. 9 3.« 3.40 3.30 3.43 3.13 3.46 V* 12 - 1,14 3 7.8

•wji VoHapa »«••• .0 LSI I.M 1.40 1.70 1.3* I.M V* - - 1.14 - 7,8

*aafc-to-*aafc Tank Voltaaa VP-P ,,

Ml. Typ Mw Mi. T«R MM Ml. '»P Mmf«V &.•'*».» _ l.'4 3 7,8

Output Outv Cyda voc 3 % S«'i>«* — '. 14 3 7,8

OMltlttfen * raquancy «».. - ~ - - 200 325 - " " - MHk S.tFi,u.«4 - 1.14 3 7, »

i 9u«*anttm the c»c pottntiw * t for purpottri of ii


Supply Voltage - —5.2 volts

'

-30*C

•»»C6S°C

TEST VOLT IT VALUES

ICMI

IValttl MUt

V,h „.„ Vil .1. VEE l L

- 3 240 -3 790 -5.2 -SO-3 400 -3900 -5.1 -5.0

-3 520 -4 020 -5.2 -5.0

CfcWMMrrUfc $•/**•• Taat

SP1 649 Taat limila TEST VOL TACE/CUP.P.ENT APPL'INS LISTEO BELOW:

IE0 TO-30»C »«C 6S«C

U...MW. Mai Ml. Ma. Ml. Ma> VlHm.. Vila*. VES >L

**••*•« Supply Oaift Current 'l;

9 - — - 41 — — ".Adt — _ 7,8 — 1. 14

LOfK "t"

Owtpwi Voli«f»V0M

W3 1.045 -0 315 -0.980 -0.7S0 •0.890 -0.950 V»c - 12 7,6 3 '. 1«

Lofk "0"

Output Vonafav0t 3 -i.no -1.850 -1.890 -1.620 -'.830 -1.575 Vac 12 ~ 7.6 3 1,14

.« V«l«f« *•'.*.• 10 -3.890 -3.340 -3.800 -3.500 -3.920 -3.620 V4e - ~ 7,8 - ','4

•Safe-te^Mti Tank VeUtf* »«, 12

Mia Typ Mm Mi. 'yp Ma> Mi. Typ Maa

., Sat Fifu'y* _ 7 , , 1,14— - — - 500 - -3 — —OwWwt Owty CycM voc 3 - — - — 50 - — — — X Sa.«.av.«4 — 7.6 3 '.'•

Oltil|M«fi|9ii|Ky -J. ~ - - ~ 200 325 - ~ - - MMi Say '<9ur84 - 7, 9 3 '.'«

t tmyawl—i ***• «» pottwulM attheetw 00**** ••** porpoatto* t^or0c*a*6rtf a

26

SPI 648

B.W. = 10kHz Scan Width = 50kHz/div

Center Frequency = 100MHz Vertical Scale = 10db/div

_0<|i ^io,<

* The 1200 ohm resistor and the scope termination

impedance constitute a 25:1 attenuator probe.

Fig. 3 Spectral purity of signal at output

* Use high impedance probe (>1.0 Megohm must be

used).

* *The 1200 -ohm resistor and the scope termination

impedance constitute a 25:1 attenuator probe.

* * Bypass only that supply opposite ground.

rT~\PRF = 10 MHz ,

DUTY CYCLE (Vqc' =tf

Fig. 4 Test circuit and waveforms

27

SP1648

OPERATING CHARACTERISTICS

Figure 1 illustrates the circuit schematic for the SP1648.

The oscillator incorporates positive feedback by coupling

the base of transistor TR7 to the collector of TR8. Anautomatic gain control (AGO is incorporated to limit the

current through the emitter-coupled pair of transistors

(TR7 and TR8) and allow optimum frequency response of

the oscillator.

In order to maintain the high Q of the oscillator, and

provide high spectral purity at the output, a cascode

transistor (TR4) is used to translate from the emitter

follower (TR5) to the output differential pair TR2 and

TR3. TR2 and TR3, in conjunction with output transistor

TR1, provide a highly buffered output which produces a

square wave. Transistors TR10 thru TR14 provide this bias

drive for the oscillator and output buffer. Figure 3 indicates

the high spectral purity of the oscillator output (pin 3).

When operating the oscillator in the voltage controlled

mode (Figure 5), it should be noted that the cathode of the

varactor diode (D) should be biased at least 2 VBE above

Vee («= 1.4 V for positive supply operation).

Fig. 5 The SP1648 operating in the voltage-controlled mode

When the SP1648 is used with a constant dc voltage to

the varactor diode, the output frequency will vary slightly

because of internal noise. This variation is plotted versus

operating frequency in Figure 6.

F=F3

f. OPERATING FREQUENCY IMHzl

20 kHz ABOVE SP1648 FREQUENCY

SP1648

UNDER TEST ATTENUATOR

OSCILLATOR TANK COMPONENTS(CIRCUIT OF FIGURE 5 )

f

MHz DL

pH

10 - 10

10-60

60-100

MV2115

MV2115

MV2106

100

23

0-15

SIGNAL GENERATOR

HP 608

OR EQUIV

PRODUCT

OETECTOR

BW = 10kHzFREQUENCYMETER HP3400A

OR EQUIV

VOLTMASTER

RMSHP3400A OR EQUIV

FREQUENCY DEVIATION ='"P»10A OUTPUT VOLTAGE) IFULL SCALE FREQUENCY I

V0 VOLT

Note'.Any frequency deviation caused by the signal generator and SP1648 powersupply should be determined and minimised prior to testing.

fig. 6 Frequency deviation test circuit

28

SP1648

X2

zUJ

oIT

0.

5o

64

60

56

52

48

44

40

36

32

28

24

20

16

12

80

VCC ,= VCC2 = +5Vdc T

VEE1 = VEE2= Gnd X

10

4 1 1 l°l! ~i ni

i2°°

U J-.(! Mi°'1pI c JJ

s^ i JL f

3

1

MV1401 '2 S(

= 5>i = 01ji

] H> 20 30

'in

40

INPUT

j.,, s.g 7.g g gg | fl" The 1200 ohm resistor and the scope termination

VOLTAGE (VOLTS)impedance constitute a 25:1 attenuator probe.

Fig. 7

1*

_ IT

Xz If

%n

s <*oK 13

5 "

I "

3 10

"~90

t-0(

OVm 9

VEE1 = vEE2 - Gnd XC = SOOp U

"

' Ikl 1 <

|1

1 <2001 i,,!

:c~j~|^

—

I*S»' oit!

3

i

1

L-1 LIIVI

Jj

= Sli ==<H|'

X ' 5 '

HI 20 3-

V

40 SO 60 70 80 90 1

,n INPUT VOLTAGE (VOLTS)

) * The

imp

1200 ohmedance consiti

resistor and the scope termination

jte a 25: 1 attenuator probe.

Fig. 8

190

WO- 170

j£ 1*0~"

ISO

u UO

£ 130

ul 120

£ 110

5 100a.

S 90o

•0

J 70

60

SO

-F|

'" VCC1 = VCC2=+SVdc J

J"

I

VEE1 = »EE2 = Gnd X

io T511,1s«h ^I_JTsC L Tl^V-T 1 T

±iP Ms^yAJ

3

* 1 l!

= 0-1)1

) M) 20 3-0

Vin

40 SO 60 70 SO 90 K

INPUT VOLTAGE (VOLTS)

* The

imp

1200 c

edance c

mm resistor and the set

onstitute a 25:1 attenuat

ipe termination

or probe.

Fig. 9

29

SPI 648

Typical transfer characteristics for the oscillator in the

voltage controlled mode are shown in Figures 7, 8, and 9.

Figures 7 and 9 show transfer characteristics employing

only the capacitance of the varactor diode (plus the input

capacitance of of the oscillator, 6pF typical). Figure 8

illustrates the oscillator operating in a voltage controlled

mode with the output frequency range limited. This is

achieved by adding a capacitor in parallel with the tank

circuit as shown. The 1 kfi resistor in Figures 7 and 8 is

used to protect the varactor diode during testing. It is not

necessary as long as the dc input voltage does not cause the

diode to become forward biased. The larger-valued resistor

(51 k£2) in Figure 9 is required to provide isolation for the

high-impedance junctions of the two varactor diodes.

The tuning range of the oscillator in the voltage

controlled mode may be calculated as:

fmax "\/C (max)+Cs

where fn

fmin VCd (min) + Cs

1

2nVUCD (max) + Cs )

Cs = shunt capacitance (input plus external

capacitance).

Crj = varactor capacitance as a function of

bias voltage.

Good RF and low-frequency by-passing is necessary on

the power supply pins (see Figure 3).

Capacitors (C1 and C2 of Figure 5) should be used to

bypass the AGC point and the VCO input (varactor diode),

guaranteeing only dc levels at these points.

For output frequency operation between 1 MHz and

50 MHz a 0.1juF capacitor is sufficient for C1 and C2. At

higher frequencies, smaller values of capacitance should be

used; at lower frequencies, larger values of capacitance. At

higher frequencies the value of bypass capacitors depends

directly upon the physical layout of the system. All

bypassing should be as close to the package pins as possible

to minimize unwanted lead inductance.

The peak-to-peak swing of the tank circuit is set

internally by the AGC circuitry. Since voltage swing of the

tank circuit provides the drive for the output buffer, the

AGC potential directly affects the output waveform. If it is

desired to have a sine wave at the output of the SP1648, a

series resistor is tied from the AGC point to the most

negative power potential (ground if +5.0 volt supply is

used, —5.2 volts if a negative supply is used).

At frequencies above 100 MHz typ, it may be necessary

to increase the tank circuit peak-to-peak voltage in order to

maintain a square wave at the output of the SP1 648. This is

accomplished by tying a series resistor (1 kfl minimum)

from the AGC to the most positive power potential (+5.0

volts if a +5.0 volt supply is used, ground if a —5.2 volt

supply is used).

30

m^PLESSE^^ Semiconductors

.

SP1 650/51

SP1650 (HK3HZ)

SP1651 (lowz)

DUAL A/D COMPARATOR

POSITIVE LOGIC

»2I> '1

rb ,3

Zl^

—

D °

C Q

ZT^— ° °

c 5

VCC* +5.0 V- Pin 7,10

-5.2 V - Pin 8 Gnd - Pin 1,16 DG16

Fig. 1 Logic diagram

FEATURESPd =330mWtyp/pkg (No load)

tPd =3.5nstyp. (SP1650)

=3.0nstyp. (SP1651)

Input Slew Rate=350 V/|*s (SP1 650)

=500V/us(SP1651)Differential Input Voltage:

-5.0V to +5.0V (~30°Cto +85°C)

Common Mode Range:

-3.0V to +2.5V(-30°Cto +85°C) (SP1650)

-2.5V to +3.0V(-30°Cto +85°C) (SP1651

)

Resolution : s$ 20mV (-30°C to +85°C)

Drives 50Q lines

The SP1650 and the SP1651 are very high speedcomparators utilizing differential amplifier inputs to

sense analog signals above or below a reference level.

An output latch provides a unique sample-hold

feature. The SP1650 provides high impedance Dar-

lington inputs, while the SP1 651 is a lower impedanceoption, with higher input slew rate and higher speedcapability.

Complementary outputs permit maximum utility for

applications in high speed test equipment, frequency

measurement, sample and hold, peak voltage detection,

transmitters, receivers, memory translation, sense ampli-

fiers and more.

The clock inputs (C~a and CT) operate from ECL III

or ECL 10,000 digital levels. When Cl is at a logic high

level, Q a will be at a logic high level provided that

Vi>V2 (Vi is more positive than V2). 07 is the logic

complement of Qa . When the clock input goes to a

low logic level, the outputs are latched in their present

state.

Assessment of the performance differences betweenthe SP1650 and the SP1651 may be based upon the

relative behaviour shown in Figs. 5 and 8.

TRUTH TABLE

c" V,. V2 Qn+1 Qn +1H V1>V 2 H L

H V1<V 2 L H

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33

SP1 650/51

VIN TO CHANNEL t

5}-

^ ^

W42H

»EEI

I**

50-ohm termination to

ground located in each

scope channel input

All input and output cables to the

scope are equal lengths of 50-ohmcoaxial cable.

tRefer to Fig. 4 for input pulse definitions.

* Complement of output under test should

always be loaded with 50ohms to ground

Fig. 3 Switching time test circuit at +2^t

34

SP1 650/51

V - Input to Output

t*. t_- 1.5 ±0.2 «• (10% to

f - 5.0 MHZ50% Duty Cycto _V|u napplM to C during t

TEST PULSE LEVELS

PulMl Pulse 2 Pulse 3

SPI650 SPI651 SPI650 SPI651 SPI 650 SPI 651

VlH + 2.100V + 2.100V + 5.000V + 4.500V -0.300V -0.800V

Vr + 2.000V f 2.000V + 4.900V r 4.400V -0.400V -0.900V

Vil + 1.900V + 1.900V -r 4.800V i- 4.300V -0.500V -1.000V

™ ->H40i»h«- _ L

V,H •2 100 V

-T^-TK^-xM: t«.t. - 1.S10.2I

f/ff. 4 Switching and propagation waveforms@ 25°C

35

SP1 650/51

r 1

-rr^- o a

Vl DEVICE

C 5

-\,s 1

J"-

y4rr L7

1

Posrtiva Pulsa Diagram

Positive

Nagativa Pulse Oiagrarr

>

—r—v o«*.«

v,; h \ ,

-J'pd[— »

.—^c

Proportion Dak y vorus Puis* AmplniMHl

1 1 1 1 Mil! 1|

1 1 1 1 1 Mil 1

— —— PaMwt Gonj Pa i

SP1650.

i

| Ill )j

1SPH*i,v/

"^

i

[''''/

1

i

" ^ In P *. 1-LU.1__J

-'on on OK 010 OJI OKI

puist AMPLITUDE P*. P|| (V01TSI

f/0. 5 Propagation delay (tpd) v. input pulse amplitude and constant overdrive

36

SP1 650/51

Propagation Dolay varsut OvaroYtvi

e

<2

1 '

L

1 1 I Mil 1 IIIPA. Pb Constant @ 100 mV

\Positive Ow tdn.e IPaI

•tdrrve IPjl

VIpd ,snw»,,«at,omV„|

\ -SP16501

V1

-

SP165V

tpdis referenced to 2 5 V oveidm

1 1 U 1 Mill!01 0? 04 07 10 02 3 OS 1 10 2 5 10

OVERDRIVE (VOITSI

Fig. 5 (continued)

v,„ "UJU

-

1 \|

- :;jlat \i

i

ii

•i j\i

1

• '

i !/

3 1

ii

i i

i

i

TeM Number ^^ '

IS«« Test Table)

Fig. 6 Logic threshold tests (waveform sequence diagram)

37

SP1 650/51

Typical Transfer Curvas

TEST CONFIGURATION

3ENTIAL fol L!k.'PUr

1 -- - |T>~'IN \o 1 r-t^

o a

to DEVICE

I J

-2 5Vdc * VREF * »2'5V

1

1

f" *

H '

—

J

70 -IS -10 -5 i 5 10 15 20

Vitf

V„. DIFFERENTIAL INPUT VOLTAGE Im VOLTSI

Fig. 7 Transfer characteristics (Q v. Vin)

TEST CIRCUIT

^ n>f

i i

IB) Typical Output Logic Swing versus Frequency

850SP1651

5»

1

> 0650

;

S 250

<\50 1 7s\ ioo\ 200

1000

050

Inpu Vollagi

20 30 50 20 100

FREQUENCY IMHi)

200 300

850SP1650

640•v

s.

0«50

250* 75^ 100* 200^ mo

050mVPtk to Pert

1

200 300

FREQUENCY IMNll

38

Fig. 8 Output voltage swing v. frequency

TEST CIRCUIT

SP1 650/51

"^

r «cc vCc—

|

l_VEE Gnd _Gnd_ J

mi Irnt

Typical SP16S0 IComptenwnttry Input Grounded) Typical SP1661. ICompNmnnttfy Input Gnumtodl

•30»C, •2S»C>

..."

\ )>•;^» '"

..' ~-— \#' ~«ls»c

-*J**•*"

«•":?<"

I *2 '2.5 -2S -2

V,„ INPUT V01T»GE IV01TS)

V

1 2 25

Vm. INPUT VOLTAGE IVOLTSI

Fig. 9 Input current v. input voltage

39

SP1 650/51

7S,

t=ttHr__Ld__1

IU>f

^50-ohm termination to

ground located in eachscope channel input.

All input and output cables to thescope are equal lengths of 50-ohmcoaxial cable.

Analog Signal Positive and Negative Slew Case

V R * 100 mV = »2 100 V

U R - 2 000 V

100 mV = » 1.900 V

Vm - *0.310 V

"Clock enable time= minimum time between analog and clocksignal such that output switches, and tpd (analog to Q) is notdegraded by more than 200ps.Clock aperture time=time difference between clock enable timeand time that output does not switch and V is less than 1 50 mV.

Fig. 10 Clock enable and aperture time test circuit and waveforms @ 25°C

40

SP1658

Semiconductors

SP1658VOLTAGE-CONTROLLED MULTIVIBRATOR

The SP1658 is a voltage-controlled multivibrator which

provides appropriate level shifting to produce an output

compatible with ECL III and ECL 10,000 logic levels.

Frequency control is accomplished through the use of

voltage-variable current sources which control the slew rate

of a single external capacitor.

The bias filter may be used to help eliminate ripple on

the output voltage levels at high frequencies and the input

filter may be used to decouple noise from the analog input

signal.

The SP1658 is useful in phase-locked loops, frequency

synthesizer and clock signal generation applications

for instrumentation, communication, and computer

systems.

C X1 ,. CX2

"HI"?"

——06

DG16

vcx 20

BIAS FILTER 12O—INPUT FILTER 13 5

VCC1 =

VcC2 =

V EE =

Pin 1

Pin 5

Pin 8

Fig. 1 Block diagram of SP1658

n%

Fig. 2 Circuit diagram 41

SP1658

g Jibuti!!K 3 • C = TJ w -Si

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42

SP1658

vcc

VCCI VCC2

;o-i)i

-3 2 V 6VEE

SCOPE INPUT

CHANNEL "A"



scope channel input.


scope are equal lengths of 50-ohmcoaxial cable. Wire length should

be <1 inch from TPin to input pin

and TPout to output pin.

X—/ JjML

Fig. 3 Switching time test circuit and waveforms

43

S PI 658

1000

100

Xz

S tozUJ

o

10

z ^z

A"i'n cr

linnI-75MH2 (3 5 0pF #

35MHI (3) 5 0pF -

VCX = »v

IIJ 1 1

^U}f vex = -10 v ^=

vex = -20 V

sN

N10 10 100 1000 10,000

CxIpFI

Fig.4 Output frequency v capacitance for three values of inputvoltage

_ 10.000

X

z

z 1000o<

a

z1

100

OCE

|

II III BVcc = +S-2V

vcc =

s;

1 1 1 IIIII 1

1 10 10 10

f, OPERATING FREQUENCY (MHzl

Fig.5 RMS noise deviation v operating frequency

=

•CX-

FREQUENCY

CAPACITANCE

PRODUCT

(MHx-

S8SSSSSgSSSSS

1 1

CAL CURVE FOR O30pFTYP

-2 o -i-§ -is -it -i2 -io -ot -oe -ot -0 2 e

"CX INPUT VOLTAGE (VI

Fig.6 Frequency-capacitance product v control voltage Vex

44

SP1660

^ftPLESSE^^ Semiconductors .

SP1660DUAL 4-INPUT OR/NOR GATE

SP1660 provides simultaneous OR-NOR output functions

with the capability of driving 50/t lines. This device contains

an internal bias reference voltage, ensuring that the

threshold point is always in the centre of the transition region

over the temperature range (-30°C to +85CC). The input

pulldown resistors eliminate the need to tie unused inputs to

Vee.

FEATURES

Gate Switching Speed Ins Typ.

ECL 10000- Compatible

50$2 Line Driving Capability

Operation With Unused l/Ps Open Circuit

Low Supply Noise Generation

POSITIVE LOGIC

DC Input Loading Factor = 1

DC Output Loading Factor = 70

tpd = 03 ns typ (510-ohm load)

= 1 .1 ns typ (50-ohm load)

Pq = 120 mW typ/pkg (No load)

Full Load Current, li = —25 mAdx. max. DG16


APPLICATIONS

Data Communications

Instrumentation

PCM Transmission Systems

jJ>

rSSsHtKfiSSS6t 6s 6« 6?

tIHtllLUJ_l£xiion on 612 oia

Fig. 2 Circuit diagram

45

SP1660


This ECL III circuit has been designed to meet the

dc specifications shown in the test table, after thermal

equiblirium has been established. The package shouldbe housed in a suitable heat sink or a transverse air

flow greater than 500 linear fpm should be maintained

while the circuit is either in a test socket or mounted ona printed circuit board. Test procedures are shown for

selected inputs and selected outputs. The other inputs

and outputs are tested in a similar manner. Outputs are

tested with a 50-ohm resistor to —2.0 Vdc.

• TMTarflparatura

-30°C

»°Ce6°c

TEST VOLTAGE VALUES

VlHmw vILmin VlHAmiti ViLAnm

1.025 -1.440

SP1660 Test Limits

VlHmaa vILmio vIHAmin V|LAi

•owiar Supply Drain Currant

wAdc

MAdc

NOR Logic "1" Output Voltage

NOR Logic "0" Output Voltage

OR Logic "1" Output Vo!tage

OR Logic "0" Output Voltage

OR Logic "I" Threshold Voltage

OR Logic "0" Threshold Voltage

Snitching Timet ISO fl Load)

Propagation Delay '4*3-

<4-2-

'4*2.4-3*

"Individually last each input applying V(H c

Vout OR Vout NOR

@tO ©I CHANNEL I

B^i i

/

f-sm.

Input Pulse t + = t— = 1 .5 t 0.2ns

Fig. 3 Switching time test circuit

and wave forms at +21?

C

46

SP1662

^^P' Semiconductors

SP1662QUAD 2-INPUT NOR GATE

The SP1662 comprises four 2-input NOR gating functions

in a single package. An internal bias reference voltage

ensures that the threshold point remains in the centre of the

transition region over the temperature range -30°C to +85°C.Input pulldown resistors eliminate the need to tie unused

inputs to Vee.

FEATURES


ECL 10000—Compatible

5012 Line Driving Capability



APPLICATIONS

Data Communications

Instrumentation


POSITIVE LOGIC


DC Output Loading Factor = 70tpQ> - 0.9 ns typ. (510-ohm load)

= 1 Ins typ. (50-ohm load)


Full Load Current. I|_ = -25 mAd.c. max. QG1B



Power supply voltage |VCC -VeeI 8V

Base input veltage 0V to VE E

O/P source current < 40mAStorage temperature —55°C to +1 50°

C

Junction operating temp. < +1 25°

C

o-->

8->

(h(H »(l HJ (h "H -l)

Cm On

Fig. 2 Orcuit diagram

47

SP1662


This ECL III circuit has been designed to meet thedc specifications shown in the test table, after thermalequiblirium has been established. The package shouldbe housed in a suitable heat sink or a transverse air

flow greater than 500 linear fpm should be maintainedwhile the circuit is either in a test socket or mounted ona printed circuit board. Test procedures are shown for

selected inputs and selected outputs. The other inputsand outputs are tested in a similar manner. Outputs are


•I

COAXIAL CABLES|(EQUAL LENGTHS 500 I

TO SCOPE

;82

INPUT

©—CZD-PULSE GENERATOR

{"

DH- **!

2"

i i

UNUSED OUTPUTS CONNECTED TO A 50-OHMRESISTOR TO EARTH

*

c i-

H

Fig. 3 Switching lime test circuit

and wave forms at +2oC

48

SP1664

^APLESSE

Y

^^P' Semiconductors

.

SP1664QUAD 2-INPUT OR GATE

The SP1664 comprises four 2-input OR gating functions in

a single package. An internal bias reference voltage ensures

that the threshold point remains in the centre of the transition

region over the temperature range (-30°C to +85°C).

Input pulldown resistors eliminate the need to tie unusedinputs to Vee.

FEATURES


ECL 10000-Compatible

50S2 Line Driving Capability



APPLICATIONS

Data Communications

Instrumentation


POSITIVE LOGIC

3« >fcc2

38 VEE

DC Input Loading Factor » 1

DC Output Loading Factor = 70tpd = 0.9 ns typ (510-ohm load)

= 1 .1 ns typ (50-ohm load)


Full Load Current, l|_ - —25 mAd.c. max QG16


(no on on on


49

SP1664


This ECL III circuit has been designed to meet the

dc specifications shown in the test table, after thermalequiblirium has been established. The package shouldbe housed in a suitable heat sink or a transverse air

flow greater than 500 linear fpm should be maintainedwhile the circuit is either in a test socket or mounted ona printed circuit board. Test procedures are shown for

selected inputs and selected outputs. The other inputs

and outputs are tested in a similar manner. Outputs are


Ifaul TO CHANNEL ~B~

PULSE GENERATOR

INPUT PULSE

UNUSED OUTPUTS CONNECTED TO A SO-OHMRESISTOR TO EARTH


and wave forms at +2!>C

JIS

« w s s w « If IS» « > SS (0 JO

MVI3<>

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VI> ? ri 5

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50

SP1666

Semiconductors

SP1666

DUAL CLOCKED R-S FLIP-FLOP

Two Set-Reset flip-flops in a single package which

require a clock input to enable the set-reset inputs. Internal

input pull-down resistors eliminate the need to return

unused inputs to a negative voltage.

The device is useful as a high-speed dual storage element.

TRUTH TABLE

s R c Qn+1

• • On1 Qn

1 1

1

1

1

1

1 N.O.

POSITIVE LOGIC

S

7

4

S

C

R

QDC Input Loading Factor

S. R » 1 C - 0.6

S. R. C - 1

3DC Output Loading Factor = 70 (High Z)

7(LowZI

tpa • 1.6 ns tup (SlOohm load)

12

9

• 13

S

c

R Q

IS » 1.8 ns typ (50-ohm load!

PD - 220 mW typ/pkg (No load-High Zl

230 mW typ/pkg (No load Low Zl

0G16

• = Don't care

N.D. = Not Defined Fig. 1 Logic diagram of SP1666

C »CC2 S

09 O* OI2 OHQ R VCCl R O

ISO 013 Ol AO Q2

Fig. 2 Greuit diagram

51

SP1666

(£(C ID (0

« o u uX o o O

«. C O m in^ » n rsi oo

II 2 '5

lis*8? si

fitsO C "D

-a* §-o

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CO

C O « C « Q> w

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O <J " c ,_ g

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O "D "D< < <£ E

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o oio <f>

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ID '.O

88

CO 00 00 00

o o10 IC

I®©= **

®@ ©© ©e @0

oS oS oS oS

ISO o; >

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a o>

?lp 5

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si6 o

52

SP1666

Fig. S Switching time waveforms (set/reset to Q/Q, switch SI in

position shown in Fig. 4)

Fig. 6' Switching time waveforms (dock to Q/Q, switch SI in

opposite position to that shown in Fig.-4l

54

SP1668

Semiconductors

SP1668DUAL CLOCKED LATCH

This device is a Dual Clocked Latch/R-S Flip-Flop.

Whenever the Clock is low, the R-S inputs control the output

stage. Whenever the Clock is high, the output follows the

data (D) input.

TRUTH TABLE

s R D C CWiQn

1 1

1

1 1* *

1

1 1 1

' Output stage not defined

i Don't care

POSITIVE LOGIC

Vcc 1 = PIN 1

Vcc 2 = PIN 162 Vee = PIN 8

3 DC Input Loading Factor

Jl

6

7

DS

CR

S

ID,S,R = 1,C = 0.6

DC Output Loading Factor = 70,J

I

11

9

SQ

CR

Q

tpd = 1.6ns typ (510 ohm load)15

= 1.8ns typ (50 ohm load)

Pd = 220mW typ/pkg (No load)

I

DG16

Fig. 1 Logic diagram of SP1668

C VCC2 ° Q

09 ore on mi

~2

D03 06

^L^a_HTK_^3js^-

0

65 R;S0k

Fig.2 Circuit diagram

55

SP1668

(J c

II I

II I

I I

I I

I I I I

I II

I I

rI 8 S £

I II

*" E o a E -oa> ®£ «! <2 »«•£ °> » c cE - a> > (5 =

C ft — " E <7>

9> a> ^ q. a>

a> .c <o co "•- **

CA ._ CD 0> .E

* o c 2 2 ~

c </) <c re .tr

= -S5.e-37 H o E -o S SOC U C § S IS a,

O .2 &g o »£

en

3a% 3o ax: £ 3

o ore

en

Va>c

T3>CD c O3T3

ca

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Uoa

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K c (A

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'@®©@&®0® 0©

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j,^.

56

SP1668

© lg is measured with no output pulldown resistors. © Apply Vin1 to S (V| H to V| L ).

(2) Test voltage applied to pin under test. © Apply Sequentially: Vin , to R (V, H to V, L )W Vin2 toC(V| H V| L )

Vin3toD(V IH toV( L)

©Apply Vin1 toR(V| H toV| L )

©Apply Sequentially: Vin1 to S (Vm to V| L )

Vin2 toC(V|H V| L )

©Apply Sequentially: Vin1 to R (V tH to V| L )

Vin2 toC(V| H V| L )

J r 25

-j»„.

>Sns—A W—TEST

Fig. 3 Notes referred to in electrical cherecteristict

TO CHANNEL "A"




Input pulses

by 2 pulse

generators

|

CI

Q1

1/2

D 5l

S R1

1 1

D 52

S2 R2

1.JI

SO COAX

y-\.

TO CHANNEL*"

/""* ./"XI IIV

4031V


57

SP1668

jf^\

|*-'S+Q +

y^r\_

/^\*— *R +Q- —

•

. ir ,ot irt0 "

\ /iovl 3L . 90 ./.

\ /-'»•/. \ ">''•

V-90V. * 90V.

W/. /-10V.

•— <R+Q+ —J k-lQ- —J !•— '0+(•-tS+Q- -«l

Fig. 5 Switching time waveforms (setAsset to O/Q, switch SI in

position shown in Fig. 3)

Fig. 6 Switching time waveforms (dock to Q/Q, switch S1 in

position opposite to that shown in Fig. 3

58

SP1670

SP1670MASTER/SLAVE TYPE D FLIP-FLOP

The SP1670 is a D-type Master-Slave Rip-Flop designed

for use in high speed digital applications. Master-slave

construction renders the SP1670 relatively insensitive to the

shape of the clock waveform, since only the voltage levels at

the clock inputs control the transfer of information from data

input (D) to output.

When both clock inputs (C1 and C2) are in the low state,

the data input affects only the Master portion of the flip-flop.

The data present in the Master is transferred to the Slave

when clock inputs (C1 OR C2) are taken from a low to a high

level. In other words, the output state of the flip-flop changes

on the positive transition of the clock pulse.

While either C1 OR C2 is in the high state the Master (and

data input) is disabled.

Asynchronous Set (S) and Reset (R) override Clock (C)

and Data (D) inputs.

Input pulldown resistors eliminate the need to tie unused

inputs to Vee.

FEATURES

Toggle Frequency > 300 MHz

ECL 10000-Compatible

50Si Line Driving Capability



APPLICATIONS

Data Communications

Instrumentation


c '

\

/ \

' v~5 r N r~

POSITIVE LOGIC

|

;:;=D J

5 3

I

Vcci = P'N 1

VCC2 = PIN l«

V£ E = P,N •

DC Input Loading Factor = CI . C2 = 0.67 D - 0.75 R,S = 1 .5

DC Output Loading Factor = 70Power Dissipation = 220 mW typical (No Load)

ftog = 350 MHz typ DG16


TRUTH TABLER S D C Qn+l

L H <t>H

H L <t> <t>L

H H<t> <t>

N.D.

L L L L QnL L L J~ L

L L L H Qn

L L H L QnL L H J~ H

L L H H Qn

= Don't Care

ND = Not Defined

C = C1 +C2

Fig. 2 Timing diagram

59

SP1670


This ECL III circuit has been designed to meet the d.c. specifications shown in the characteristics table, after thermal

equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow

greater than 500 linear ft/min is maintained. Outputs are terminated through a 50ft resistor to —2.0 volts.

• Ten

TEST VOLTAGE VALUESIVoltil

•26°C

VlHma. VlLmin V,HA mil, VlLAmee VII

>7 >l

IVCC >

God

-0.875 -1.890 -1.180 -1.515 -5c2

-0.810 -1.850 -1.095 -1.485 -6.2

-0.700 -1.830 -1.025 -1.440 -5.2

CMnmnc Symbol

PinSP1670 Test Limits TEST VOLTAGE APPLIED TO PINS

LISTED IELOW.-x°c •2S C 85°CUnitTeet Min Man Min Ma> Min Max VlHma. VlLmtn VlHAm.n vILAma« Vf F

Power Supoly Drain u 8 - - - 48 - - mAdc ',9 - - _ 8 _ - _ 1,16

Input Current linH 4 - - - 550 - - uAac 4 - _ _ 8 _ _ _ 1,165 — — — 550 — —

I5 _ _ _ _ _ _

1

9 - - - 250 — - 9 _ _ _ _ _ _7 - — — 250 — — 7 _ _ _ _ _ _II - - - 270 — - 11 - - - - _ -

hn L - - 0.5 - - - »Adc 9 4 _ _ 8 _ _ _ 1.16— -

1

- — -I

9 5 — —1

-^ - -|- - - — - 7 9 — — - - -

7 - -|

- - -|

9 7 - - - - -9

logic "1"«0M 2 -1.045 -0.875 -0960 -0.810 -0.890 -0.700 vac _ 4,7,11 _ _ 8 9 5 _ 1,16

Output Vo„.g, 3

1 1

|I 1 1

J

" 5,9 - -1

' 4

9

7

*1

3 T * < T \ - 4.9,11 _ _ 5 _ 1

Log.C "0" VOL 2 -1.890 -1.650 -1.850 -1.620 -1.830 -1.575 Vdc 11 5,7 _ _ 8 9 4 _ 1,16Output voltage 3

2

3 1 1 1 1 1 1 1

'-4,9,11

4,7,11

5,9 : I 15

5

9

: 1

Logic "I" V MA 2 ..065 _ -0980 - -0.910 - VdC - 4,7,11 _ _ 8 9 _ 5 l,li

Threwoio Voltage 3

2

3

2

\\ \

!_<

5,9

5,7

4,9, 1

1

5,7 ^: 5

9

9

3 — — ^ — - «,9 _ 11 T 5 7 -Logic "0" V01A 2 _ -1.630 _ -1.G00 _ - 1 .555 Vdc ii .

5,7 _ 8 9 _ 4 1,16Threshold Voltage 3

2

3

2

; : I 1

4,9, 1

1

5.9 I -5

5 9

5

9

3 - - - T ~ 5.9 ii - 4 / -

Switching F-erametert

ClOCh lO-OUtpul Delay t9 + 2 + 9.2

Milt Ma. Min Mam Min Mai-32Vdc

•20

1.0 2.; 1.1 2.5 1.1 2.9 8 1 16

ISee Figure II 19 +2-19+3+19+3-

9.2

9.3

9,3 : 2: : 1

:-

Set lo Outo.il Delay '5»2» 5.2 _ _ _ _ _ _ _ISee Figure 21 'so- 5.3 _ _ _ _ _ _ _

Relet to Outoui Delay i*e2- 4.2 _ _ _ _ _ _ _ISee F.gure ?l t4«3» 4.3 — _ _ _ _ _ —

Oulout

Fliie Time '!*,<}* 2,3 0.9 2.7 1.0 25 t.O 2.9 - _ _ _ _ _ _fell T.me 2-.I3- 2,3 0.5 2.1 06 19 06 2.3 ~ — _ _ _ _ —

ISee Figure 21

Set Uo Time I>"1" 2 - _ _ 0.4 _ _ _ _ _ _ _ _ _ISee Figure 31 l,"0" 2 - - - 0.5 — - - - - - - - -

Mold T.me lM"t" 2 — - - 3 — - - - _ _ _ _ -ISee Figure 3> tM"0" 2 - — - - 0.5 — - ' - — — — - - -

Toggle Frequency 2 270 _ 300 _ 270 _ MHz _ _ _ _ _ _ _ _ISee Figure 41

*i n.-H e*-

60

SP1670

mnnnu.sc ^_

Fig. 3 Propagation delay test circuit

j—

v

Y 1C ¥

e. y-^r?v^r^

F/ff. 4 Cfocfr <fe/ay waveform at +25°C

•"^"CSE'J|

H

» I

E

J±L

nALL INPUT ANO OUTPUT CABLES TOTHE SCOPE AKE EQUAL LENGTHS OF50-OHM COAXIAL CABLE

Set-up and hold time test circuit

Set-up time waveforms at +26X>C

Fig. 5 Set/reset delay waveform at +21?

C

Fig. 6 Set-up and hold time test circuit

Set up time is the minimum time before the positive

transition of the clock pulse (C) that information must be

present at the data (D) input.

Hold time is the minimum time after the positive

transition of the dock (C) that information must remain

unchanged at the data (D) input.

61

SP1670

*j.v<.

I

T "*"rh

, tci *a

•'n /""— .

^"oui

- 5-

nam iDMUun«fcM

>T «E£

4-J

I"

" T

Ml «*UT MU OUTPUt CA0LCS IDn* scan mc EQMM lcngims of

Figures 9 and 1 illustrate minimum clock pulse width

recommended for reliable operation of the SP1 670

Fig. 7 Toggle frequency lest circuit

l/VWW::i

Fig. 8 Toggle frequency waveforms

The maximum toggle frequency of the SP1670has been exceeded when either

:

1. The output peak-to-peak voltage swing falls

below 600mVOR2. The device ceases to toggle (divide by two). Vb«sis defined by the test circuit Fig. 7 and by the waveformin Fig. 8.

[

rJtt-K

> .../ i/f. . .. tint \%\\tin lltl imi it ii nil. Ill nil/

£

OorQ

I

I

1 Ofts/OIV

Fig. 9 Minimum 'down time' to clock

{Output load = 50il)

Fig. 10 Minimum 'up time' to clock

[Output load = 50SI)

Ttmperatura —30-C +25°C +85°C

VB ,a, +0.660V +0.71 0V +0.765V

Tmble 1 Variation of Vgjias "»'»* temperature

62

SP1670

Operation of the Master-Slave Type D Flip-Flop

In the circuit of Figure 1 1 assume that initially Q, C, R,

S and D are at levels and that Q is at the 1 level. Since the

clock is low, transistors TR3 and TR22 are conducting. In

the slave section only transistors TR25 and TR26 are in

series with TR22. The output of the slave section is fed

back to these two transistors in order to form a latch. Thus,

when the clock is low, the output state of the slave is

maintained. In the master section, the current path is

through TR3 and TR9.

Now assume that the data input goes high. The

high-input signal on the base of TR4 causes it to conduct,

and TR9 to turn off. The voltage drop across resistor RC1

causes a low-state voltage on the base and therefore on the

emitter of TR11. Since there is essentially no current flow

through RC2, the base of transistor TRIO is in a high state.

This is reflected in the emitter, and in turn is transferred to

the base of TR6. TR6 is biased for conduction but, since

there is no current path, does not conduct.

Now allow the clock to go high. As the clock signal rises,

transistor TR2 turns on and transistor TR3 turns off. This

provides a current path for the common-emitter transistors

TR5, TR6, TR7, and TR8. Since the bases of all these

devices except TR6 are in the low state, current flow is

through TR6. This maintains the base and emitter of TR 1

1

low, and the base and emitter of TRIO high. The high state

on TR10 is transferred to TR23 of the slave section. As the

clock continues to rise TR21 begins to turn on and TR22

to turn off. (Reference voltages in the master and slave

units are slightly offset to ensure prior clocking of the

master section.) With transistor TR21 conducting and the

base of TR23 in a high state, the current path now includes

TR21, TR23, and resistor RC3. The voltage drop across the

resistor places a low state voltage on the base, and therefore

the emitter, of TR30. The lack of current flow through

RC4 causes a high state input to the base of TR29. These

states are fed back to the latch transistors, TR25 and TR26.

As the clock voltage falls, transistor TR21 turns off and

TR22 turns on. This provides a current path through the

latch transistors, locking-in the slave output.

In the master section the falling clock voltage turns on

transistor TR3 and turns off TR2. This enables the input

transistor TR4 so that the master section will again track

the D input.

The separation of thresholds between the master and

slave flip-flops is caused by R8. The current through this

resistor produces an offset between- the thresholds of the

transistor pairs TR2:TR3 and TR21:TR22. This offset

disables the D input of the master flip-flop prior to the

enabling of the information transfer from master to slave

via transistors TR23 and TR28. This disabling operation

prevents false information from being transferred directly

from master to slave during the dock transition,

particularly if the O input changes at this time (such as in a

counting operation where the Q output is tied back to D).

The offsetting resistor also allows a relatively slow-rising

clock waveform to be used without the danger of losing

information during the transition of the clock.

The set and reset inputs are symmetrically connected.

Therefore, their action is similar although results are

opposite. As a logic 1 level is applied to the S input

transistor, TR2 begins to conduct because its base is nowbeing driven through TR19 which is in turn connected to S.

Transistor TR5 is now on and the feedback devices TR6and TR7 latch this information into the master flip-flop. Asimilar action takes place in the slave with transistors TR21,

TR24, TR25, and TR26.

u

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Fig. 1 1 SP1670 Circuit diagram

63

SP1672

^ftPLESSEV^^ Semiconductors

.

SP1672TRIPLE 2 INPUT EXCLUSIVE-OR GATE

This three gate array is designed to provide the positive

logic Exclusive-OR function in high speed applications.

These devices contain a temperature compensated internal

bias which insures that the threshold point remains in the

centre of the transition region over the temperature range

(-30°C to +85°C). Input pulldown resistors eliminate the

need: to tie unused inputs to Vee.

POSITIVE LOGIC

3£>—

A • B + A -B

Full Load Current. I L • -25

1

DC Input Loading Factor

A- 1.0

B-0.75


DG16


scope are equal lengths of 50-ohm' coaxial cable.

»„ ID CHANNEL "A" V^t TO CHANNEL'S"

(1 ) Apply Vin to input Aand +0.31 V to input B

(2) Apply Vin to input Aand 1.11V to input B

PROPAGATION DELAY

Unused outputs connected to a 50-ohm resistor ground.

t +i in

' + 0-31.

Condition© Vout

Condition® V

^|r-— 90V.V 50 V.

jf90V.Jf-SOV.

jf-— 10 V.

/

YFig. 2 Switching tima test circuit and waveforms at +25°C 65

SP1672

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SP1674

flftPLESSE

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^^ Semiconductors

,

SP1674TRIPLE 2-NMPUT EXCLUSIVE-NOR GATE

This three gate array is designed to provide the positive

logic Exclusive-NOR function in high speed applications.

These devices contain a temperature compensated internal

bias which insures that the threshold point remains in the

centre of the transition region over the temperature range

(-30°C to +85°C). Input pulldown resistors eliminate the

need to tie unused inputs to Vgg.

POSITIVE LOGIC

3S>C = A • B + A •

B

Vcci = Pin 1

VcC2= Pin 16Vee= Pin 8

- 1.3nstvpe (50-ohm load)

220 mW tvp/Pkg [High Zl

DC Input Loading Factor

A= 1.0

B = 0.75

DG16





I TOCHANNEl/B'

INPUTPULSE GENERATOR

©

(1 ) Apply Vin to input Aand 1 .1 1 V to input B

(2) Apply Vin to input Aand +0.31 V to input B

PROPAGATION DELAY

Unused outputs connected to a 50-ohm resistor to ground

"^H^p--™Condition© V

Condition© V out

Fig. 2 Switching time test circuit and waveforms at +25°C

67

SP1674

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SPI 692

^& Semiconductors

.

SP1692QUAD LINE RECEIVER

Four differential amplifiers with emitter followers,

intended for use in sensing differential signals overlong lines.

Input pulldown resistors are not provided

A Vbb reference voltage is available on pin 9.

POSITIVE LOGIC


DC Output Loading Factor = 70

tpd = 0.9 ns typ (510-ohm load)

= 1.1 ns typ (50-ohm load)

PD = 220 mW typ/pkg (no load)

Full Load Current, l|_ = -25 mAdc max

DG16


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69

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70

SP16F60

^^^ Semlconcluctors

.

SP16F60DUAL 4-INPUT OR/NOR GATE

SP16F60 provides simultaneous OR-NOR output

functions with the capability of driving 50 Q lines. This

device contains an internal bias reference voltage, en-

suring that the threshold point is always in the centre of

the transition region over the temperature range (—30°Cto +85°C). Input pulldown resistors eliminate the needto tie unused inputs to Vee.

FEATURES

Gate Switching Speed 550ps Typ.

ECL III and ECL1 OK Compatible

50Q Line Driving Capability



Pin and Power Compatible with SP1660

POSITIVE LOGIC

DC input loading factor = 1

DC output loading factor = 70

tpd = 0.55ns typ. (50 0. load)

Pd = 120mW typ./pkg. (no load)

Full load current, II = —25mA DC (max). DG16


APPLICATIONS

Data Communications

Instrumentation


Nucleonics


Power supply voltage | Vcc - Vee | 8VBase input voltage OV to Vee

O/P source current <40mAStorage temperature —55°C to -150°CJunction operating temperature < ^125C

VCC2 *ci

mj]n>Lr<

04 05 66 67 I OIO Oil 012 013

HmmIh lit }-M"fi*p}-t


71

SP16F60


This ECL 111 circuit has been designed to meet thedc specifications shown in the test table, after thermalequiblirium has been established. The package shouldbe housed in a suitable heat sink or a transverse air

flow greater than 500 linear fpm should be maintainedwhile the circuit is either in a test socket or mounted ona printed circuit board, lest procedures are shown tor

selected inputs and selected outputs. The other inputs €

and outputs are tested in a similar manner. Outputs are twiTanparature

-30°C»2S°C

+85°C

TEST VOLTAGE VALUES (V)

V,H m.« V»L min V|HA min Vila ma. Vee

Vcc(Gnd)

tested with a 50-ohm resistor to —2.0 Vdc. -0.875 -1.890 -1.180 -1.515 -5.2

-0810 -1.8S0 -1.095 -1.485 -5.2

0.700 -1.830 -1.025 -1.440 -52

Characteristic Symbol

Pin

Under

Test

SP16F60 Test LimitsTEST VOLTAGE APPLIED TO PINS LISTED BELOW:

-30°C +25°C +85°CUnits V| H m.. VlL min V|HA min Vila m.« VeeMin Max Min Max Min Max

Power Supply Drain Current l E S - - - 28 - - mA - - - - 8 1.16

Input Current in H - - - 350 - - pA - - - 8 1.16

n L- - 0.5 - - - fA - - - 8 1.16

NOR Logic 1

Output Voltage

V H -1. 45 -0. 75 -0.960

I

-0.810

f

-1 890 -0.700 V1

4

5

6

7

1 18

1

6

NOR Logic

Output Voltage

Vol 3

1

-1 890

1

-1.650

I

-1. 50 -1.620

1

-1.830 -1 575

1

V

1

4

5

6

7

-

1 18

I

1.16

I

OR Logic 1

Output Voltage

V0H 2

1

-1.045 -0.875

1

-0.960

1

-0.810

1

-0! 90 -0.700

1

V

1

4

5

6 - -

18

1

16

OR Logic

Output Voltage

Vol 2

I

-1.890 •1.650

I

-1.850

I

- 1 .620

1

-1 830

1

-1.575

i

\

-

4

5

6

7

1 18

1

1.16

1

NOR Logic 1

Threshold Voltage

v ha 3

I

-1.065

1

-

-0.980

I

-

-0.910

I

-

V

I

1 1:

5

6

7

8

I

1.16

I

NOR Logic

Threshold Voltage

Vola 3

1

-

-1.630

1

1-1 600

I

:

-1.555

I

: -

4

5

6

7

-

8

1

1.16

I

OR Logic 1

Threshold Voltage

Voha 2

1

-1.066

I

-

-0.980

I

1-0.910

I

1V

I

-

14

5

6

7

-

8

1

1.16

1

OR Logic

Threshold Voltage

Vola 2

1

:-1.630

1

-

-1 600

1

-

-1.555

1

V

1

1 1-

4

5

6

7

8

I

1.16

1

Switching Timas iSOii Load!

Propagation Delay U.3-l«-2-

U.2.t«-3.

3

2

2

3

Typ Max Typ Max Typ Max

1

Pulse In Pulse Out

:

"-3.2V 2.0V

: \

0.55

I

0.8

1

1 13

2

2

3

3 1.16

1

20% to 80%<3.

'2.

3

2

0.4

0.35

0.6

0.6 z _ns 4

4

3

2 :" 8

8

1.1B

1.16

Fall Time20% to 80%

i3-

'2-

3

2

0.4

0.35

0.6

0.6

- ~ ns 4

4

3

2 _ :8

8

1.16

1,16

Jividually test each input applying Vih or V.|

ALL INPUT AND OUTPUT CABLES TO

THE SCOPE ARE EQUAL LENGTHSOF 50-OHM COAXIAL CABLE

V|N TO CHANNEL *

£PINPUT PULSE

t*st-=0-5(!(Hlns

(20V. IOS07.I

VOUT "OP "out 0R

@ TO @ICHANNEL £

72Fig. 3 Switching time test circuit and waveforms at +25°C

SP16F70

^^P' SemiconductoiY

Semiconductors

,

SP16F70MASTER/SLAVE D TYPE FLIP-FLOP

The SP16F70 is a D-type Master-Slave Flip-Flop designed

for use in high speed digital applications. Master-slave

construction renders the SP16F70 relatively insensitive to the

shape of the clock waveform, since only the voltage levels at

the clock inputs control the transfer of information from data

input (D) to output.

When both clock inputs (C1 and C2) are in the low state,

the data input affects only the Master portion of the flip-flop.

The data present in the Master is transferred to the Slave

when clock inputs (C1 OR C2) are taken from a low to a high

level. In other words, the output state of the flip-flop changes

on the positive transition of the clock pulse.

While either C1 OR C2 is in the high state the Master (and

data input) is disabled.

Asynchronous Set (S) and Reset (R) override Clock (C)

and Data (D) inputs.

Input pulldown resistors eliminate the need to tie unused

inputs to Vee.

FEATURES

Toggle Frequency >350MHz

ECL 1 0000 Compatible

50nLine Driving Capability



^PLICATIONS

Data Communications

Instrumentation


POSITIVE LOGIC

5 S 1

» C2 J S

1

Q I

1

Vcc 1 = PIN 1

Vcc 2 = PIN 16

Vee = PIN 8

DC Input Loading Factor = C1, C2 = 0.67 D = 0.75 R,S = 1.5

DC Output Loading Factor 70

Power Dissipation = 220mW typical (No Load)

ftog = 350MHz min DG16



TRUTH TABLER S D C Qn+1

L H * H

H L L

H H N.D.

L L L L QnL L L J~ L

L L L H QnL L H L Qn

L L H J" H

L L H H Qn

= Don't Care

ND = Not Defined

C = C1 +C2

73

SP16F70


This ECL III circuit has been designed to meet the d.c. specifications shown in the characteristics table, after thermal

equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow

greater than. 500 linear ft/min is maintained. Outputs are terminated through a 5012 resistor to —2.0 volts.

TEST VOLTAGE VALUES

P, *1 '1

IVolttl

(VCC I

God

f TWTemperature VlMma, VlLntin VlHAietin VlLAma. Vfl

30°C -0875 -1.890 -1.180 -1.515 -5. J

•»'C -0.810 -1.850 -1.095 -1 485 -5.2

••••c -0 700 -1.830 -1.025 -1.440 -5.3

CKwactemtic Symbol

•inTest Limits TEST VOLTAGE APPLIED TO PINS

LISTE0 IELOW:-J0°C •2»°C 8S°CUnitTm Min Ma. Min Ma> Min Mae VlHm., V.L m.n VlHAmin VILA ma. VEE

k - — - 48 - — mActc '.9 - - — 8 _ _ _ 1,16Input Current l.nH

- " "550

550

250

250

270

I

-«Adc

1

5

9

_ 1 :

8

i

;: \

1,16

1

lln L

1 -

0.5

1

" -

:

*.Adc

I

9

9

9

9

5

9 ^ =

8

I

; ; :

1,16

1

Logic 1'

"OM -1045

I

-0.875

1

-0.960

i

-0.810

1

-0.890

l

-0.700

! T »

".'.1!

5,9

5.7

4.9,11

\ -

8

1

9 5

9

'-_

1,16

1

Log.c "0-

OulOul »«,WVOL -1 890

1

-1.650

1

1.850

!

•1.620

1

1 830

1

-1.575

1

...

'-

5,7

4,9, 1

1

5,9

\ -

8

1

5

9 -

1,16

i

Logic "l~ »Oha •1. 165

~-0< 80

_-0 910

_

;

j

5,9

5.7

4.9, 1

1

5,1

4,9

'-

-8

1

I9

5

9

6

Threshold VouagevOLA

~1. 30

--l.i 00

:

555

-5.7

4,9, 1

1

5.9

5.9

_

~-

9

9

5

6

S».irhin, Parameter!

Clock to- Output Delay

Set to Outoi.i Oeiav

Retei toOutout Delay

Tomk Frequency

t9+2 +19 + 2-t9+3+19 +3-'5»2*

'50-

14+2-

'4«3e

t^,'>'?-.'3-

V'0"

'M"0"

'Tog

9.2

9.2

9.3

9.3

5.2

5.3

4.2

4,3

2.3

2,3

2

2

2

2

2

Min Mae Min Mae Min Mae

1

6

6

6

6

\

32Vdc

:

-

1

•2Vdc

a0.

35

9

S

O

2

2. 7 1.

0.

35

)

2.

2

0.

0.

0.

5

5

9

5

3

5

3.

6

2

2

2

9

3

M

6

aine-e- l»-

74

SP9131

ffl ft LEwwE w^^P' Semiconductors

.

SP9131520MHz DUAL TYPE D MASTER SLAVE FLIP-FLOP

R-S TRUTH TABLER S Qn + 1

L L Qn

L H H

H L L

H H N.D.

CLOCKED TRUTH TABLEC D Qn+1

L O Qn

H L L

H H H

The SP9131 is a dual master slave type D flip-flop which

is pin-for-pin compatible with therECLl0131, but with

improved dynamic performance and increased power

dissipation.

9— Don't CareC=C E +CC .

A clock H is a clock transition

from a low td a high state.

PD = 364mWfTog

= 520MHz (typ)

Si 5-

Di 7 .

CE1 6 •

Rl 4

Cc 9

R2 13

^E2 "

D2 10

S2 12

;0

331 02

02

VCC1 = Pin 1

VcC2= Pin 16Vee= Pin 8

fig. 1 Logic diagram

75

SP9131

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U

2 e

f 8 g

1 1 I

76

SP9131


ground located in eachscope channel input.



be <i inch from TPin to input pin

and TPoat to output pin.

Fig. 2 Toggle frequency test circuit

ClOCK

@-L„

Input Pulse

t + = t— = 1.0ns + 0.2ns

(20 to 80%)

^AJ CI.i.' 1

'-.,.



scope channel input

AH input and output cables to the


be <i inch from TPin to input pin

and TPout to output pin.

jF^-\J SaM »

/ft/

».^ r - ^i i—.

«!.—• »

NOTE.tutup is the minimum time before the positive

transition of the clock pulse (C) that information must

be present at the data input (D).

thoM is the minimum time after the positive transi-

tion of the clock pulse (C) that information must

remain unchanged at the data input (D).

Fig. 3 Switching time test circuit and waveforms at +25C

77

SP9680

SP9680ULTRA FAST COMPARATOR

The SP9680 is an ultra fast comparator manufactured

using a high performance bipolar process which makes

possible very short propagation delays (2.4ns typ.).

The circuit has differential inputs and complementary

ECL outputs, capable of driving 50 Q lines.

The device is manufactured in a low cost mini-dip

package and is intended as an alternative to the faster

SP9685 in applications where performance premium

and the latch facility are not required.

FEATURES

Propagation Delay 2.4ns Typ.

Complementary ECL Outputs

50 Q Line Driving Capability

Excellent Common Mode Rejection

8-Lead Plastic Package

QUICK REFERENCE DATA

Supply Voltages +5. -5.2V

Operating Temperature Range —30°C to

+70°C

DP8


—O O OUTPUT

—O Q OUTPUT

The outputs are open emitters, therefore external

pulldown resistors are required. These resistors

may be in the range of 50-200 Q connected to

-2.0V or 200-2000 O connected to -5.2V.

Fig. 2 Functional diagram

K—-s<

Fig. 3 SP9680 circuit diagram79

SP9680

ELECTRICAL CHARACTERISTICSTest conditions (unless otherwise stated) :

Tamb = 25°CVcc - 5.00V ± 0.25VVee = -5.2V ± 0.25VRl = 50QVt = -2.0V (See Fig. 2)

CharacteristicValue


Input offset voltage -6 +6 mV Rs <100QInput bias current 20 40 HAInput offset current 10 HASupply current Ice 18 25 mA

Iee 22 35 mATotal power dissipation 200 300 mWInput to Q output delay 2.4 4 ns

} 100mV pulse,10mV overdriveInput to output delay 2.4 4 nsCommon mode range -2 +2 VCommon mode rejection ratio 80 dBOutput logic levels

Output HIGH -0.96 -0.81 VOutput LOW -1.85 -1.65 V

Input capacitance 3.5 pFInput resistance 50 kQOperating temperature range -30 +70 °C


Positive supply voltage Vcc +6VNegative supply voltage Vee —6VOutput current 30mAInput voltage ±5VDifferential input voltage i5VStorage temperature —55°C to +125°C

80

SP9685

ffl BI^LEwwC

SP9685ULTRA FAST COMPARATOR

The SP9685 is an ultra-fast comparator manufacturedwith a high performance bipolar process which makespossible very short propagation delays (2.2ns typ.).

The circuit has differential inputs and complementaryoutputs fully compatible with ECL logic levels. Theoutput current capability is adequate for driving50 Q. terminated transmission lines. The high resolutionavailable makes the device ideally suited to analogue-to-digital signal processing applications.

A latch function is provided to allow the comparatorto be used in a sample-hold mode. When the latch

enable input is ECL high, the comparator functionsnormally. When the latch enable is driven low, theoutputs are forced to an unambiguous ECL logic state

dependent on the input conditions at the time of thelatch input transition. If the latch function is not used,the latch enable may be connected to ground.The device is pin compatible with the AM685 but

operates from conventional +5V and —5.2V rails.

FEATURES

Propagation Delay 2.2ns typ.

Latch Set-up Time 1 ns max.


50 Q Line Driving Capability


Pin Compatible with AM685 - But Faster


Supply voltages +5V, —5.2V

Operating temperature range

—30°C to +85°C


Positive supply voltage 6VNegative supply voltage -6VOutput current 30mAInput voltage ±5VDifferential input voltage ±5VPower dissipation 300mWStorage -55°Cto +150°CLead temperature (soldering 60 sec) 300°C

CM10/S

DG1S

On metal package, pin 5 is connected to case. On DIPpin 8 is connected to case


LATCH ENABLE

The outputs are open emitters, therefore external pulldownresistors are required. These resistors may be in the rangeof 5O-20OQ connected to -2.0Vor 200-20000. connectedto -5.2V


81

SP9685


Test conditions (unless otherwise stated) :

Tamb=25°CVcc = +5.0V ±.25VVee = -5.2V ±.25VRl = 50 Q

Characteristic

Value


Input offset voltage

Input bias current

Input offset current

Supply currents Ice

Iee

Total power dissipation

Min. latch set-up time(ts)

Input to Q output delay(tpd)

Input to output delay(tpd)

Latch to Q delay tpd(E)

Latch to (3 delay tpd(E)

Mm. latch pulse width tpw(E)

Min. hold time(th)

Common mode range

Input capacitance

Input resistance

Output logic levels

Output HighOutput Low

Common mode rejection ratio

Supply voltage rejection ratio

-5

-2.5

60

- .96

-1.858060

10

1923

2100.5

2.2

2.2

2.5

2.5

2

3

+52052334

3001

333331

+2.5

- .81

-1.65

mVmAmAmAmAmWnsnsnsnsnsnsnsVPFkQ

VVdBdB

Rs <100Q

( 1 00 mV pulse

| 1 mV overdrive

At nominal supply

voltages, see Fig. 4

LATCH

ENABLE

DIFFERENTIAL

INPUT T-

VOLTAGE

IPARE j \

2^/——\——


OPERATING NOTES

Timing diagram

The timing diagram. Figure 3, shows m graphic form

a sequence of events in the SP9685. It should not be

interpreted as 'typical' in that several parameters are

multi-valued and the worst case conditions are

illustrated. The top line shows two latch enable pulses,

high for 'compare', and low for latch. The first pulse

is used to highlight the 'compare' function, where part

of the input action takes place in the compare mode.

The leading edge of the input signal, here illustrated as

a large amplitude, small overdrive pulse switches

the comparator over after a time tpd. Output Q and

82

transitions are essentially similar in timing. The input

signal must occur at a time ts before the latch falling

edge, and must be maintained for a time th after the

latch falling edge, in order to be acquired. After th, the

output ignores the input status until the latch is again

strobed.A minimum latch pulse width tpW(E) is required

for the strobe operation, and the output transitions

occur after a time tpd(E).

Measurement of propagation and latch delays

A simple test circuit is shown in Figure 4. The

operating sequence is

:

1. Power up and apply input and latch signals.

Input =100mV square wave, latch ECL levels.

Connect monitoring scope(s).

2. Select 'offset null'.

SP9685

3. Adjust offset null potentiometer for an outputwhich switches evenly between states on clockpulses.

4. Measure input/output and latch/output delays at5mV offset, 10mV offset and 25mV offset.

~l I © 10 50n

JJ _ MEASURINGSYSTEM

ELECTRICAL LENGTHS

Fig. 4 SP9685 test circuit

%,+^5'C

^^+_25"C

-SS-T '

1 IS 20 25

OVERDRIVE (mV)

30 SO 100 200 300 i.00

FREQUENCY (MHz)

Fig. 5 Open loop gain as a function of frequency

1

1

"

r^

-1

i

i

15 20 2S

OVERDRIVE (mV)

Fig. 7 Propagation delay, input to output as a function overdrive

Fig. 6 Propagation delay, latch to output as a function of overdrive

5m

lOmV^N

"25mV -"O

;—

-

-55 35 -15 5 25 (.5 45 15 105 125

TEMPERATURE CO

Fig. 8 Set-up time as a function of temperature

_ t25'

OVERORIVE (mVI

Fig. 9 Set-up time as a function of input overdrive

83

SP9685

^ „,-•''

v.*^*_,-»*'"

10 ay,--'•''

25«

-55 -35 -15 5 25 45 65 »5 105 125

TEMPERATURE CO

Fig. 10 Propagation delay, input to output as a

function of temperature

V̂to"\ -

-55 -35 -15 5 25 45 65 »5 105 125

TEMPERATURE (°0

Fig. 11 Propagation delay, latch to output as a function of

temperature

—BIS

_-4--i

-55 -35 -15 15 65 85 105 125

TEMPERATURE CO

16

12

< 10

3

UPPER COMMON MOOE

ocac

3 *

LiftIER COMMON HOI

IT

3E

Fig. 12 Output rise and fall times as a function of temperature

-55 -35 -15 5 25 45 65 05 105 125

TEMPERATURE CO

Fig. 13 Input bias currents as a function of temperature

v< H

--''

^

~>\ :25>v^^

t\V

5aV

r\; V •V

J •25»VXv) \

-55 -35 -15 5 25 45 65 05 105 125

TEMPERATURE CO

Fig. 15 Response to various input signal levels

Fig. 14 Output levels as a function of temperature

84

SP9687

^^P' Semiconductors

.

SP9687ULTRA FAST DUAL COMPARATOR

The SP9687 is an ultra-fast, dual comparator

manufactured with a high performance bipolar process

which makes possible very short propagation delays

(2.2ns typ.). The circuit has differential inputs andcomplementary outputs fully compatible with ECLlogic levels. The output current capability is adequate

for driving 500. terminated transmission lines. The high

resolution available makes the device ideally suited to

analogue-to-digital signal processing applications.

A latch function is provided to allow the comparator

to operate in the follow-hold or sample-hold mode.The latch function inputs are intended to be driven from

the complementary outputs of a standard ECL gate. If

LE is highland LE is low, the comparator function is in

operation. When LE is driven low and LE high, the

outputs are locked into the logical states at the time of

arrival of the latch signal. If the latch function is not used,

LE must be connected to ground.The device is pin compatible with the AM687 and

operates from conventional +5V and —5.2V rails.

FEATURES

Propagation Delay 2.2ns Typ.

Latch Set-up Time 1 ns max.


500 Line Driving Capability


Pin Compatible with AM687- But Faster


Positive supply voltage 6VNegative supply voltage -6VOutput current 30mAInput voltage ±5VDifferential input voltage ±5VPower dissipation 590mWStorage -55°C to +125°C

ooutput[1 W

] OUTPUT

5 OUTPUT []0" OUTPUT

GROUND[ ] GROUND

leI * ]le

CE[

fl. /

Ft]L1

v-( ]v*

INVERTING l/P I_l i_

] INVERTING l/P

NON-INVERTING l/P(

1

j ] NON-INVERTING l/P

DG16


The outputs are open emitters, therefore external

pulldown resistors are required. These resistors

may be in the range of 50-200 il connected to

—2.0V or 200-2000 fi connected to -5.2V.



Lead temperature (soldering 60 sec) 300°CSupply voltages +5V, -5.2VOperating temperature range —30°C to +85°C

OPERATING NOTES

Timing diagram

The timing diagram, Figure 3, shows in graphic forma sequence of events in the SP9687. It should not beinterpreted as 'typical' in that several parameters are

multi-valued and the worst case conditions are

illustrated. The top line shows two latch enable pulses,

high for 'compare', and low for latch. The first pulse

is used to highlight the 'compare' function, where part

of the input action takes place in the compare mode.The leading edge of the input signal, here illustrated as

a large amplitude, small overdrive pulse, switches

the comparator over after a time tpd. Output Q andtransitions are essentially similar in timing. The input

signal must occur at a time ts before the latch falling

edge, and must be maintained for a time th after the

latch-falling edge, in order to be acquired. After th, the

output ignores the input status until the latch is again

strobed. A minimum latch pulse with tpW (E) is required

for the strobe operation, and__the output transitions

occur after a time tpd (E). The LE input is omitted for

clarity.

85

SP9687


Test conditions (unless otherwise stated)Tamb =25°CVcc = +5.00V ±.25VVee = -5.20 V ±.25VRl = 50 QVt= -2.0V

ValueCharacteristic Units Conditions

Min. Typ. Max.

Input offset voltage -5 + 5 mV Rs <100QInput bias current 5 20 mAInput offset current 1 5 mASupply currents Ice

Iee

3054

4668

mAmA \ Note 3

f Nominal conditionsTotal power dissipation 430 590 mWMin. latch set-up time (ts) 0.5 1 ns Notes 1,2Input to Q output delay (tpd) 2.2 3 ns

) 100 mV pulse („,,«, 1

> 10 mV overdrive •Input to output delay (tpd) 2.2 3 nsLatch to Q delay tpd(E) 2.5 3 nsLatch to Q delay tpd(E) 2.5 3 ns f

Notes 1,

2

Min. latch pulse width tpw(E) 2 3 nsMin. hold time(th) 1 nsCommon mode range -2.5 +2.5 VInput capacitance 3 pFInput resistance 60 kQOutput logic levels

Output High - .96 - .81 V At nominal supplyOutput Low -1.85 -1.65 V voltages

Operating temperature range -30° + 85° °CCommon mode rejection ratio 80 dBSupply voltage rejection ratio 60 dB

NOTES1. These measurements are defined under conditions of a +100mV pulse with —10mV overdrive. The relationship between overdriveand delay is illustrated in Figs. 6 to 8.

2. Switching measurements involving the latch are particularly difficult to perform and cannot be tested in production. Circuit analysisshows that at least 95% of devices will meet these specifications.

3. Refers to the entire package. Other data in this table applies to each half device.

LATCHENABLE

DIFFERENTIAL

INPUT

VOLTAGE

z/^^i

86

vos

^t^IZ^^^

SP9687

PERFORMANCE CURVES

Unless otherwise specified, standard conditions for all curves are Tamb = 25°C, Vcc = 5.0V,

VEE = -5.2V

m

z

2M 300 100

FREQUENCY (HHz)

Fig. 4 Open loop gain as a function of frequency

»^«^+t75"C 1

»__ <-25"C

-S5*T

OVERDRIVE (mV)

Fig. 5 Propagation delay, latch to output as a function of overdrive

+ 12 5'C

««»_ + 25'C

55 •c

OVERDRIVE (mV)

Fig. 6 Propagation delay, input to output as a function of overdrive

5a

WmV, ^*n» -^>

==i-^

-55 -35 -15 5 25 15 «5 85 WS 125

TEMPERATURE CO


_ + 25'

-55

OVERDRIVE (mV)

Fig. 7 Set-up time as a function of input overdrive

^.

Vo4'W+*"'

—"""

10»V,-"'

25»

-55 -35 -15 5 25 15 65 «5 105 125

TEMPERATURE (°C)

Fig. 9 Propagation delay, input to output as a function

of temperature87

SP9687

_ ^^^

o.0*\^

osSxt

u >

oQ.Oa.

t

"55 -35 -15 S 25 45 65 IS 105 125

TEMPERATURE COFig. 10 Propagation delay, latch to output as a function of

temperature

3Z 1

trcc

UP >£R COM ION MO0£

,

——-.

LOh ER COMHON MO

T

E

-55 -35 -15 5 25 « 65 85 105 125

TEMPERATURE CC)

Fig. 12 Input bias currents as a function of temperature

__.

RISE

—FAU

5 25 IS 6S 15 105 125

TEMPERATURE CO

Fig. 1 1 Output rise and fall times as a function of temperature

vc H

---

>

>

-20-SS -35 -15 5 25 15 65 65 105 125

TEMPERATURE CO

Fig. 13 Output levels as a function of temperature

\ !2S«\k,J

N"5»V

n" 5 .»

•25«V

OUTPUTIOOihV

PER/OIV

2 ns PER/DIV

Fig. 14 Response to various input signal levels.

88

^^P' Semiconductors

.

SP9750HIGH SPEED COMPARATOR

SP9750

The SP9750 is a high speed comparator with a latch

circuit and other facilities intended for use in the con-

struction of fast A-D converter systems. The speed

capability of the device is compatible with conversion

rates of up to 1 00 Mega-samples per second. Input and

output logic levels are ECL compatible.

FEATURES

Latch Set-up Time 2ns Max.

Max. Input Offset Voltage 5mVPropagation Delay 3ns (Typ.)

ECL Compatible

Comparator Output Gating

Wired OR Decoding for 4 Bits

Current Output Settling to 0.2% in 8ns


Positive supply voltage +5.5VNegative supply voltage —5.5VReference supply voltage —8.5VReference current output 1 5 mAInput voltage ±4VDifferential input voltage ±6VPower dissipation 500 mWOperating temperature range —30°C to +85°CStorage temperature range —65°C to +1 50°CLead temperature (soldering 30 sec)

300°CLogic input voltages to gate and latch Vee to


DG16

INPUT

REF

»EXT

ANALOGUE

^ OUTPUT

f\

SWITCHED

CURRENT

SOURCECURRENT

10

k>~s/

WIRED-0R

DEC00ING

LAINP

CHUT

ECL

IN

GATE

PUT

i°'lo4o4 '

DECODEDDIGITAL

OUTPUT

Fig. 2 Block diagram of SP9750

LATCH LATCH

INPUT

\lzJSIGNAL

INPUT

Q OUTPUT

10 OUTPUT

INPUT VlN \ /

TOVERDRIVE VoD

w-

tpd(Qo)

VOS

tpdllQ)

tpdlD

DEFINITION OF TERMS

ta Minimum set up time - the minimum time

before the latch positive edge that the input

must be in a given state for acquisition to take

place.

tk Minimum hold time - the minimum time after

the latch positive edge that the input mustremain in one state for acquisition to take

place

' 50% ti Minimum latch enable pulse width - the

minimum time for which the latch mustremain low for acquisition to take place

Fig. 3 Timing diagram SP975089

SP9750



Tamb = +25°CVcc = +5V ±0.25VVee = -5.2V ±0.25VVref = -8V

CharacteristicValue


Input offset voltage -5 +5 mVInput bias current 25 mAInput offset current 5 mASupply currents Vcc 16 20 mA

Vee 35 42 mAVref 14 18 mA

Total power dissipation 390 470 mWAnalogue 0/P current 'on' 5 mA See operating note 1

Analogue 0/P current 'off' 5 mA +5Von pin 8.Precision current stability 20 ppm/°C Also depends on RextMin. latch set-up time (ts ) 2 ns See operating note 2Input to Q O/P delay (tpd (QQ)) 3 4.5 ns

|Vm =100mV, 25 mV

[ over drive, 50Q loadInput to lo delay (tpd (l )) 3 4.5 ns ) on lo to volts (Note 3)Delay gate input to Qi-4 highDelay gate input to Q1-4 low

1.5

1.5

2.5

2.5

nsns | See operating note 4

Latch to lo (tpd (Ll ))between 50% points 3 4.5 ns

> See operating note 5to 1 % settling 4 8 nsto 0.2% settling 8 12 ns

Min. hold time th 1 nsMinrlatch pulse width (ti.) 2 nsCommon mode range -2.5V +2.5V VDiff. mode range 5 VNode capacitance l 3.5 PfNode capacitance analogue input 3 pfInput resistance 60 KQOutput logic levels

Logic '1

'

-.98 -0.78 V Vcc= +5V, Vee =-5.2VLogic '0' -1.85 -1.6 V Rl = 220Q to -2V

QO-t ALL SAME LENGTH SO*. TRACK -r<6) V|N r(5lGATE

Li = L 2 + L3

MON©

90Fig. 4 test circuit

GENERAL DESCRIPTION

The SP9750 is a fast comparator combined with alatch facility which allows the device to be operated in

the sample and hold mode.When the latch is 'low' the comparator is in the

'follow' mode, and when the latch is driven 'high' theoutput is locked in the existing state. The latch circuitry

will therefore always produce a decision on the inputstate. '

The comparator has a relatively low gain in the followmode, which assists in achieving an extremely fast

response. However, due to the positive feedback actionof the latch function, the gain approaches infinity

during the latch cycle, thereby ensuring high resolution.In addition to the basic comparator, the following

functions are provided on the chip to optimise theperformance of high speed parallel -series- parallel A toD converter systems.

1

.

An ECL compatible gating function for simplifiedmulti-comparator output logic.

2. Four emitter follower outputs from the gate toprovide wired OR decoding for four bits.

3. A precision current source, set by an externalresistor.

4. A high speed switch for the precision currentto provide a fast and convenient reconstruction of theanalogue input. Summing the currents in a multi-level

SP9750

comparator chain provides the D to A conversion

directly for the construction of converters of the parallel-

series-parallel type.

The philosophy adopted in the SP9750 makespossible the construction of ultra-fast, high accuracy

parallel-series-parallel converters by integrating a

significant portion of the system function on the samechip as the comparator. The result is not only to reduce

considerably the total hardware count but to reduce the

propagation delays where they are most critical, andeliminate redundant operations.

OPERATING NOTES

1 . The analogue output current (lo) is set by meansof an external setting resistor (Rext) and is equal to the

reference voltage on Pin 9 ( —8V nominal), divided by2 x Rext. The accuracy of this reference voltage mustbe consistent with the conversion accuracy required.

The output (Pin 8) compliance is —0.8V to +5.0 volts

for correct operation.

2. This parameter is defined with +100 mV input

and —1 mV overdrive, corrected to take account of the

comparator offset, i.e. the switching threshold effecti-

vely is at OV on the input waveform. The relationship

between setup time and overdrive is shown in Fig.7.

The test circuit diagram. Fig. 4 indicates a method of

performing this test.

3. Due to the relatively low gain of the comparator in

the unlatched state, propagation measurements are

defined with a 25 mV overdrive. The relationship

between overdrive and delay is shown in Figs.5 and 6.

4. The gate input accepts an ECL drive. The outputs

Qi to Q4 are active when the gate input is at an ECL'low' level, ( -1 .75V) and are switched by the internal

circuitry. A 'high' gate input ( - 0.9 V) switches the

outputs to 'low', allowing the bussing of multiple

devices onto the Qi - 0.4 rails.

5. Output settling times are measured at 10 mVoverdrive conditions ; larger overdrives produce shorter

delays.

6. The test arrangement shown in Fig. 4 provides for

a simple dynamic test of the SP9750 functions. Whenthe switch is in position 1 , the input offset voltage is

nulled with the potentiometer, a condition detected byobserving the output to be at the mid-point of its range

(lo or Qo). The latch must be 'low' for this measure-ment. The offset voltage can be measured with a high

impedance instrument. Positions 2, 3 and 4 provide

increasing amounts of bias to the reference input

corresponding to overdrives of 5mV, 10 mV, and25 mV. For convenience of operation, the input

analogue signal is referred to ground, and the reference

input is set above ground, so that an input waveformwhich is positive going and referred to ground is all that

is necessary. It should have an amplitude of (1 00 mV +overdrive voltage) and should have less than 5%overshoot. The risetime should be about 2 nS. Simplecircuit modifications and a negative going signal wouldprovide for inputs of opposite polarity. For accurate

timing, the path length Li should be equal to L2 + L3

properly terminated.

Static (DC) measurements can also be performed onthe same test arrangement.

Performance curves. Unless otherwise specified, standard conditions for all'curves are Tamb=25°C. Vcc= 5.0V. Vee=—5.2V.

Vref=—8.0V, loload= 50C1

10

dP 6

a.

s

OVERDRIVE (mV)

Fig.5 Input to /„ output delay v. overdrive

OVERDRIVE ImV)

Fig.6 Input to Q output delay v. overdrive

c

z

"i3

Z2

zzz

OVERDRIVE (mV)

Fig- 7 T, v. overdrive setup time

FREQUENCY (MHz)

Fig.8 Small signal gain v. frequency (to Q output). Latch input

91

SP9750

o

70 90

TEMPERATURE CO

Fig.9 Input to l output delay as a function of temperature

zD

O 3

D

TEMPERATURE CO

Fig. 1 1 Latch enable to l 'on ' delay as a function of temperature

—GA E OE AY Ifc PUT 02

GA E DE AY l» PUT Q; LOW

70 90

TEMPERATURE CO

Fig. 13 Gate input to Q, - Q,delay variation with temperature

<

g-2<X

25 IS 6S IS IDS

TEMPERATURE COFig. 15 Analogue output current variation with temperature

92

70 90

TEMPERATURE CO

Fig. 10 Input to Q„ output delay as a function of temperature

»- 1

O.

TEMPERATURE COFig. 12 Minimum set-up time as a function of temperature

IN, ' INRE

TEMPERATURE CO

Fig. 14 Input current variation with temperature

SP9752

^^P' SemiconductoiSemiconductors

.

SP9752TWO BIT EXPANDABLE A TO D CONVERTER

The SP9752 is a circuit block containing four compar-

ators with associated decoding logic intended for use in

the construction of A-D converter systems where the ulti-

mate in speed performance is required. Input and output

logic levels are ECL compatible.

FEATURES

Minimum Set-Up Time 2nS

Maximum Input Offset 5mV

Latch to Output Delay 4nS

Maximum Clock Frequency 1 25MHz

Four Comparators in 1 6-Lead Pack

54 [ i ^ „ ] GROUND!

B][ 13 ] COP

mhuhkm[ 12 ]?0F

«cct 11 Jl'OP

mil W ] UTCHIIP

m\[ 6 9 ] !•»

VH[7 8 ]GflOWOI

DG14

Fig 1 Pin connections

OrvChip Decoding with Carry and Carry


Test Conditions (unless otherwise stated):

Tamb = 20°cVcc = 5.00V ±0.25VVEE =-7.00±0.25VRL = 50Q (equivalent)

CharacteristicValue


Input offset voltage

Input bias current

-5

14

+5

40

mVMA

R^^OOOn

Reference input current

Supply current Ice

4

41

10

60

mAmA

Supply current lM 76 90 mA

Total power dissipation 750 mWMin. latch set-up time

Latch to output delay 4

2 nS

nS Input o/d>10mV

Min. hold time 4 nS

Min. latch pulse width

Max. clock frequency

4

125

nS

MHz

Input capacitance 6.2 PF

Latch input capacitance 2.6 pF

Common mode range -2.0 +2.0 V

Output logic levels

Output high

Output low

Operating temp, range

-.96-1.85

-30",

-.81

-1.65

+85°

VV

°C

Standard ECL

500 LFPM air flow

93

SP9752

GENERAL DESCRIPTION

Following the concept of the SP9750 and SP9685 highspeed latched comparators, the SP9752 contains four com-parator elements with master-slave latches in a configur-ation optimised for use in fast parallel, or combinationseries-parallel A-D converters. Each comparator has a rela-tively low gain in the track mode, followed by a latch stageconferring essentially infinite gain in the hold mode to pro-duce an unambiguous decision. On-chip decoding logicconverts the master latch outputs into binary coded format,then slave latches hold the information through the clockperiod for maximum system flexibility. The provision of acomplementary carry out (Co) eases the decode logicrequirement. It is anticipated that most system designsusing the SP9752 will be realised in ECL 10k logic for highspeed operation with a minimum package count. Logic in-inputs to, and outputs from, the device are fully ECL com-patible.

The basic comparator circuit is shown in Fig 3. Tran-sistors TR1A, TR1B, TR2A, TR2B provide high input imped-ance, low offset, modest gain in the track mode, but areswitched off in 'hold' when the cross-coupled pair TR5ATR5B provide the latch function.

The slave latches are essentially simplified versions of

the master latches. Master-slave action is determined byon-chip timing operations, and produces essentially glitch-free output conditions which are a pre-requisite of a suc-cessful multi-chip converter.

DYNAMIC TESTING

High speed testing of devices of this kind is necessarilya difficult undertaking and the suggested circuit shown inFig.4 should be carefully constructed if accurate results areto be obtained. The test arrangement is designed to selecta single comparator and to measure the response timesfrom the latch to the outputs. Input to output delay are diffi-cult to deal with due to the master/slave action; more rele-vant are the set-up and hold times.Operation is as follows:

1

.

Select the comparator to be tested by S3.

2. Select position 1 on S2.

3. Adjust for a middle state of the outputs using S1. Theoutput should be randomly triggered by noise into alter-nate states.

4. Set up offset (2mV, 5mV or 10mV) on S2 and measurethe appropriate delays.

5. Repeat 1-4 on next comparator.

ANALOGUE IN ' SLAVE LATCH

3>

o^oo

FUNCTION CO > D21. BD2° * A§ + CO

-O LATCH INPUT

Fig.2 SP9752 block diagram

—O LATCH INPUT

94

Fig.3 SP9752 basic comparator circuit diagram

SP9752

OFFSET NULL2 3 4 5 6 7

'^ l[t

] b 1!

^~vp S3* Vg*-.

Fig.4 Dynamic test box wiring

APPLICATIONS5-bit ADC 125 MHz

A five-bit ail-parallel ADC is shown in Fig.5. Operation at

125MHz is possible with no missing codes. Analogue andlatch inputs are distributed along transmission lines des-

igned to have matched propagation delays, to minimise

latch aperture error. In many applications this avoids the

need for a separate sample and hold function. The systeminput voltage range is ± 1.5volts at 50ohms. Encoding is byECL 10k logic which is the prime speed limitation.

The use of master/slave latching retimes the outputs

which are available for the whole clock period.

This converter concept can be extended in principle to

nine bits, but practical considerations limit the usefulness

in all-parallel systems to six or seven bits, as, for example,

seven bits require 32 SP9752s eight bits require 64, etc. In

addition, latch and input signal distribution of sufficient

accuracy becomes difficult, particularly in relation to

aperture error.

95

SP9752

QUANTISERS

Fig.5 Block diagram of 5-bit A-D converter

96

SP9754

Semiconductors <

SP9754FOUR BIT EXPANDABLE A TO D CONVERTER

The SP9754 is a fast 4 bit A-D converter, expandable up

to 8 bits without additional encoding circuitry.

It can convert at sample rates from DC to 110MHz, with

analogue inputs up to Nyquist frequencies. All output

levels are ECL compatible.

The latch function to the device provides on-chip sampl-

ing which allows the converter to operate without an ex-

ternal sample and hold. Data is clocked through the device

in master/slave fashion, ensuring that all outputs are syn-

chronous and valid for the complete clock period.

FEATURES

No External Components For 4-Bit Conversion.

| 110MHz Conversion Rate.

| OrvChip Encoding For Expansion To 8 Bits.

No External Sample And Hold Needed.

| OrtChip Resistor Reference Divider.

Bit Size 10-1 00mV.

ECL Compatible.

UHU«CHFUt [

+»cc[

CMmwurt

IATCHBHJT [

2'0UmiT[

J»0UIPUl[

raimn

vaimn

"C7-

[»

" J cwranw

n]*i

«] »E£

ts ]»«noumn

h ] onuwiovi

13 ]i

«]2

"]3

DC18



Positive supply voltage +5.5V

Negative supply voltage - 7.5VOperating temperature range -30°C to 85°C

Storage temperature -55°Cto+125°CLead temperature (soldering 60s) 300°C

W.SFVTC4 ,0 »7

( --"

\

— »

! YY

—

i

i

-"!

i

sew- - LATC

NG

OVEB"RANGE2/

jrtfV- Ar

HCFEFEMCtH-h

.^-LATCH MPUT

Fig.2 Functionaldiagram Fig.3 8-bit all-parallelsystem

97

SP9754



Tamb = 25°CVcc =+5VVee — 7VRL =100ohmsto-2V

Characteristic SymbolValue


Analogue input current l B 30 100 /iA vIN = ov

Analogue input capacitance C|N 10 PF

Common mode range VCM -2 +2 V

Maximum input slew rate 1000 V/fisec

Latch input capacitance C|N 2 PF

Positive supply current Ice 55 70 mA}SeeRg.11

Negative supply current "ee 85 100 mAReference resistor chain 25 Q

Reference bit size 10 100 mVComparator offset voltage Vos -5 +5 mVTotal power dissipation Pwss 950 1160 mW All outputs loaded

Output logic levels

Logic high VoH -0.930 -0.720 V (for 100ohm load

»to-2VLogic low Vol -1.90 -1.620 V

Min. latch set-up time ts 1.5 2 nsec 10mV overdrive

Latch to output propagation delay

:

Latch enable to output high tpd+(E) 6 8 nsec

Latch enable to output low tpd-(E) 5 8 nsec

Carry input to MSB delay tpd(C) 3 5 nsec

Max. sample rate *"cmax. 100 110 MHz

ANALOGUE SAMPLE« HOLD

r\HPUT pU^

1

,

4 BIT MSBCOMP STAGE

4 BIT DAC

ENCODER4BTLSB

COUP STAGE

1"

ENCODER

OUTPUT LATCHES

1 1 1 1 J I II8 BIT BMART OUTPUT

PERFORMANCE CURVES

s

7

•

I 5

-1 4

s3

2

1

I

1

.—

-55 -35 -15 «5 105 125

TEMPERATURE (°C)

Fig.5 Latch to outputpropagation delayas a function

of temperature

Fig.4 Parallel-series-parallel system

6

7

O ••

Is

1. -->VE «MNG -

1- |

-VEGOMG1

-15 5 25 45 as S5 105 125

TEMPERATURE (°C)

Fig.6 Output rise/fall times as a function of temperature

98

SP9754

KknV OVERORIVE

—

25mV OVERDRIVE

-55 -35 -15 45 65 85 105

TEMPERATURE (°C>


3

£ J —^jjj _^ :

S 1 ^x,—ui

****^, ___

z """" """" """"

"

Z O 1

M203040506070SOM100MPUT OVERDRIVE (mV)

Fig.8 Set-up time as a function of overdrive

-0-7

-09

>

OH

^,--

O2 -1-3

* -t-5

—-1-9

1"

-SS -35 -» 5 25 45 65

TEMPERATURE (°C)

Fig.9 Output logic levels asa function of temperature

-—\~-TV

»5 r

-55-35-15 5 25 45 65

TEMPERATURE (°C)

Fig. 11 Supply currentas a function of temperature

5 25 45 65 65

TEMPERATURE (°C)

Fig. 10 Carryinput to MSB outputdelayas a functionof temperature

80

~z •»

1- 502IU —s *°

° 3D

20

10

**•"

-55 -35 -IS 45 85 65 105 125

TEMPERATURE COFig. 12 Analogue input currentas a function of temperature

TEMPERATURE (°C>

Fig.13 Network resistance as a function of temperature

-55 -35 -15 5 25 45

TEMPERATURE (°C>

Fig. 14 MSB output edge speedsas a function of temperature

99

SP9754

23 OUTPUT @-

j2 OUTPUT @-

t> OUTPUT @—

20 OUTPUT @-

V REF«160mV

• CHIP CERAMIC

.CHIP CERAMIC

f CARRY OUTPUT

Fig. 15 Testand applications circuit forSP9754

100

SP9768

Semiconductors

,

SP97688 BIT DIGITAL TO ANALOGUE CONVERTER

The SP9768 is capable of converting an 8-bit digital sig-

nal into an analogue voltage at a rate of over 100 mega-

samples per second. An inherently low glitch design is

used and the complementary current outputs are suitable

for direct transmission line drive. Included on the chip are a

precision voltage reference and a reference amplifier.

FEATURES

5 ns Settling Time to |LSB

ECL Inputs, Current Output

B Voltage Reference Temp. Coeff . 20ppm/°C

1 00 MSPS Update Rate

APPLICATIONS

B Data Conversion

| Instrumentation

Video Speed Successive Approximation ADCs

'msbC 1 18 ]RSET

[2 « ] COMPENSATION

[ 3 16 "] REF INPUT

INPUTS <[

[;;

]«F OUTPUT

] OUTPUT

[ 6 13 ] OUTPUT

c 7 12 ] OV (ANALOGUE!

^ ISB [ 8 11 ] OV (DIGITAL!

veeC 9 10 ]vcc

DC18

DG18

F/g.T Pin connections


Supply voltages: +5V, -5.2VPower consumption: 400mW


Supply voltage: -6V, +6VStorage temperature: - 55°C to + 1 25°C

Fig.2 SP9768 block diagram

101

SP9768



T"amb 25 CVCC +5.00V±5%VEE-5.20V±5%R L

= 50fi

Rset = 220J2

Input voltage High -0.96V (min)-0.81 V (max)Low -1.85V(min)-1.65V(max)

CharacteristicsValue


Differential non-linearity 0.2 %Absolute non-linearity 0.2 %Settling time

Nominal bit size

5

784

ns

mV

See Operating Note 1

RL= 5on} Rse, = 22on

Positive output compliance +3 VNegative output compliance -1

-0.7VV

25°C+ 85°C

See ^^P^3*' n9 Note 2

Multiplying bandwidth 40 MHz Current mode, see Operating

Note 3

Maximum full scale output 30 mAMinimum full scale output 2 mAReference voltage -1.28 VTemp coeff of reference voltage 20 ppm/°C

Zero output 60 mAOutput current symmetry 100 mASupply current (lcc )

Oee)

12

662080

mAmA

CIRCUIT DESCRIPTION

The DAC has current outputs, with a nominal full scale

of 20mA, corresponding to a 1volt drop across a 50ohmload, or ±1volt across 100ohms returned to +1 volt. SeeOperating Note 2.

The actual output current is determined by the on-chip

reference voltage and an off-chip current setting resistor.

Output current, l0UT , is given by

Vref•out = 4x^2^ at full scale

"SET

A complementary lOUT is also provided. The setting

resistor, RSET , is typically 220ohms, and should have atemperature coefficient similar to that of the output load

resistor.

Where the load is an oscilloscope, with a 50ohm

nominal input, a good quality metal oxide resistor shouldbe used for RSET . it is important to realise that reflections

present in 50ohm load systems will often prove to be alimiting factor in the measurement of settling time.

The reference voltage source is nominally 1.280 voltsand is of a modified bandgap type, average temperature co-

efficient of 20ppm/°C over the range -55°C to +125°C,corresponding to approximately 1LSB change over this

temperature range.

To reduce the possibility of instability or noisegeneration, the reference supply (pin 15) can be decoupledusing a high quality ceramic chip capacitor. Stabilisation of

the loop amplifier is by a single capacitor from pin 17 to

ground. Minimum value is 3900pF, although a 10nF chipceramic is recommended.

: UNDER TEST>TPHT-;

TIMING SIGNAL

Fig.3 Test schematic (settling time)

102

^M7TTTTTT

Fig.4 Conventional DAC. Negative output wrt ground.

SP9768

to •—

I

I 1 "1 if

liril» Il7

oun>UTREF

SUWtV

TT |5 16 17 IS

Fig.5 Voltage output referred to positive supply Fig.6 Multiplying DAC (Voltage mode)

OPERATING NOTES

1 . Measurement of Settling TimeThe settling time of the SP9768 is measured for a worst

case transition of to full scale.

Oscilloscopes, whether real time or sampling, do not

have sufficiently low input VSWR or on-screen resolution

for precise settling time measurements. A measurement

technique has been designed, shown diagrammatically in

Fig.3, in which the DAC can settle into a nearly ideal

50ohm load, with minimal interconnection paths; this is

also very closely related to the practical use of the device.

Precision settling time measurements can be performed

with a high speed comparator, conveniently a dual device,

such as the SP9687, with a minimal delay time, in this case

about 2 ns. Two references are set up to detect the DACoutput settling within a window, conveniently defined as

the settling to ground of the output.

The lower comparator detects the DAC output coming

within JLSB of the final settling point, while the upper de-

vice checks that there is less than JLSB of over shoot.

2. Output ComplianceFig.5 shows the method of using the SP9768 with a load

resistor not referred to ground. This connection will be

used most often when a larger output voltage than that per-

mitted by the -0.7volt negative output voltage compliance

specification is required. The output resistor can be

referred to a positive supply in this case as long as Rset and

the analogue ground are also referred to this voltage. If lour

T »i

|i I* l> « * « 7 "

Fig. 7 Multiplying DAC (Current mode)

is also connected to this reference the decoupling will be

simplified.

3. Multiplication ModesMultiplying operation of the DAC is available in two

modes, either a voltage applied in place of the reference, or

a current supplied via the current source pin. In the former

case the 3dB bandwidth is 250kHz, while in the latter,

operational use exceeds 40 MHz. Suggested circuits are

shown in Figs. 6 and 7.

103

SP9768

104

Package Outlines

(0028/0034)

(0500)

0-25/102

(0165/0-185)

(0010/0040)

t775/8-51

(0305/0335)

1

t

'

'<•

I (0-335/0

I

oo

X1

1270 MINr

1

10 LEAD TO-100 (5.84 mm PCD) WITH STANDOFF CMIO/S

H-

L 2-41/2-67(0 095/0-105)NON ACCUMULATIVE

22 22/23-24

737MAX(0-290)

7 62(0-300)

NOMINAL CRS.

SEATING PLANE <")

(0 875/0915)

12-70MAX

(O- 500)

50EHBHfflES]

0-20/0-30

(0008/0012) O 41/051

(0016/0020)

18 LEAD DILMON DC18

105

r-i i-i n n n 1-1

(0-745/0-785)

617/6-6810-243/0-263)

10017/0021)

(0010/0012)

2-52/2 56 (0-099/0-101)

NON ACCUMULATIVE

14 LEAD CERAMIC DIL DG14

6-17/6-68

(0-243/0-263)

(0010/0012)

Jb

2-52/2-56 (0099/0-101)

NON ACCUMULATIVE


106

(0-883/0-897)

2-49/2-59 (0-098/0-102)

NON ACCUMULATIVE

JL

31


^uJ J—i-i i—i i—i n1

l_l l_l l_l l_J

.IDENTIFIES PIN Not

3 PITCHESNON ACCUMULATIVE

2-49/2-59

10098/0-102)

rS

8 LEAD PLASTIC DIL DP8

107

Ordering informationAll Plessey Semiconductors integrated circuits are allocated type numbers which

must be quoted when ordering.This number may or may not have a

suffix(A,B,C,etc.)which denotes the precise electrical specification or temperature

grade.When there is a choice of packages the two-digit Pro-Electron code is used to

identify the style required.according to the following table:

CM - Multilead TO-5DC - Ceramic Dual-in-Line(metal lid)

DG - Ceramic Dual-in-Line

Within the UK.orders for quantities up to 99 will be referred to your local

Distributor.Quantities of 1000 and over must be ordered from:

Plessey Semiconductors Limited

Kembrey Park

Swindon,Wiltshire SN2 6BAUnited Kingdom

Telephone : Swindon(0793)694994Telex : 449637

A reciprocal arrangement exists with all Distributors.but it will expedite delivery of

order if buyers can direct orders as indicated above.Outside the UK,irrespective of

quantity.you are invited to contact your nearest Plessey Semiconductors Sales

Outlet (see pp. 110-112).

108

PlesseySemiconductorsWorld Wide

109

Sales officesBELGIUM

BRAZIL

EASTERN EUROPE

FRANCE

ITALY

NETHERLANDS

NORTH AMERICA

SOUTH AFRICA

SPAIN

SWEDEN

SWITZERLAND

UNITED KINGDOM

WEST GERMANY

Plessey Semiconductors, Avenue de Tervuren 149, Box 2, Brussels 1150.

Tel: 02 733 9730 Tx: 22100Plessey Brazil, Rua Ferreira Viana 892 04761, Sao Paulo, Brazil.

Tel: 011 548 6570 Tx: 1123328 ATETBRPlessey Co. Ltd., Vicarage Lane, llford, Essex, England. Tel: 01 478 3040Tx: 23166Plessey France, 74-80, Rue Roque de Fillol, 92800 Puteaux.Tel: 776 41 06 Tx: 620789FPlessey Italia SpA, Corso Garibaldi 70, 20121 Milan. Tel: 3452081Tx: 331347Plessey Fabrieken NV, Van de Mortelstraat 6, P.O.Box 46, Noordwijk.

Tel: 01719 19207 Tx: 32088Plessey Semiconductors, 1641 Kaiser Avenue, Irvine, California 92714,

USA. Tel: 714 540 9979 Twx: 910 595 1930Plessey Semiconductors, 4849 N. Scott Street, Suite 121, Schiller Park,

Illinois 60176 USA. Tel: 321 678 3280/3281 Twx: 910 227 0794Plessey Semiconductors, 89 Marcus Blvd., Hauppauge, N.Y., 11787 USA.Tel: 516 273 3060 Twx: 96 1419Plessey Semiconductors, 7094 Peachtree Industrial Blvd., Suite 295,

Norcross, GA 30071 USA. Tel: 404 447 6910 Twx: 70 7309Plessey Semiconductors, 710 Lakeway, Suite 265, Sunnyvale, CA 94086USA. Tel: 408 245 9890Plessey South Africa Ltd., Forum Building, Struben Street, P.O. Box 2416,

Pretoria 0001, Transvaal. Tel: 34511 Tx: 53 0277The Plessey Company Ltd., Martires de Alcala 4-3, Madrid 8.

Tel: 248 12 18/248 38 82 Tx: 42701Svenska Plessey AB, Alstromergaten 39, Box 49023, 100 28 Stockholm.

Tel: 08 235540 Tx. 10558Plessey Verkaufs AG, Glattalstrasse 18, CH-8052 Zurich.

Tel: 50 36 55 Tx: 11963Plessey Semiconductors Ltd., Kembrey Park.Swindon,

Wiltshire SN2 6BA Tel: (0793)694994 Tx: 449637Plessey GmbH, Altheimer Eck 10, 8000 Munchen 2. Tel: 089 23 62 1

Tx: 215322

110

AgentsARGENTINA Electroimpex SA, Guatemala 5991, (1425)Buenos Aires.

Tel: 771-3773/772-9573

AUSTRALIA Plessey Australia Pty Ltd., P.O. Box 2, Christina Road, Villawood,

New South Wales 2163. Tel: Sydney 72 0133 Tx: AA20384AUSTRIA Plessey GesmbH, Rotenturmstrasse 25, A-101 1 Wien. Tel: 63 45 75

Tx: 75963CYPRUS Eltrom Electronics Ltd., Poly Electronic Services Ltd., P.O. Box 5393,

Nicosia. Tel: 61088GREECE Plessey Company Ltd., Hadjigianna Mexi 2, Athens. Tel: 21 724 3000

Tx: 219251Mammeas, Representations & Exportations, P.O. Box 181, Piraeus.

Tel: 4172597 Tx: 213835 LHGRINDIA Semiconductors Ltd., Ador House, 6, K. Dubash Marg., Bombay 400 023.

Tel: 245119 & 245170 Tx: 011-2781

Semiconductors Ltd., Unity Buildings, J.C. Road, Bangalore 560-001.

Tel: 52072 & 578739Semiconductors Ltd., 513, Ashoka Estate, 24, Barakhamba Road,

Nf w Delhi - 110001. Tel: 44879 Tx: 31 3369

JAPAN Comes & Company Ltd., Maruzen Building, 2 Chome Nihonbachi,

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Osaka 550. Tel: 532 1012 Tx: 525-4496

HONG KONG YES Products Ltd., Block E, 15/F Golden Bear Industrial Centre,

66-82 Chaiwan Kok Street, Tsuen Wan, NT., Hong Kong.Tel: 12-444241-6 Tx: 36590

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Tel: 2526621 Tx: CHAVALIT TH2747TURKEY Turkelek Elektronik Co. Ltd., Hatay Sokak 8, Ankara. Tel: 18 94 83

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Istanbul. Tel: 43 40 46

111

DistributorsBELGIUM

FRANCEIRELAND

INDIA

ITALYNETHERLANDS

NEW ZEALAND

SCANDINAVIADenmark

Matadex, Chausee de Bruxelles 214, Brussels 1190. Tel: 02 3450279

Tx: 24093Mateleco, 36 Rue Guy Moquet, 92240 Malakoff, Paris. Tel: 657 70 55

Electronic Manufacturing Co., 3B Avonbeg Industrial Estate,

Long Mile Road, Dublin 12. Tel: 001 521242 Tx: 31125

Semiconductors Ltd., Ador House, 6, K. Dubash Marg., Bombay 400 023.

Tel: 245119 & 245170 Tx: 011-2781

Melchioni, Via P. Colletta 39, 20135 Milan. Tel: 5794 Tx: 320321

Modelec BMVM, Postbus 181, 6710 BD EDE, Morsestraat 22 A 6716 AHEDE. Tel: 08380 - 36262 Tx: 37053Professional Electronics Ltd., P.O. Box 31-143, Auckland. Tel: 493 209

Tx: 21084

Scansupply, Nannasgade 18-20, DK-2200 Copenhagen. Tel: 45 1 835090Tx: 19037

Finland Oy Ferrado AB, P.O. Box 54, Valimontie 1, SF-00380 Helsinki 38.

Tel: 90 55 00 02 Tx: 122214

Norway Skandinavisk Elektronikk A/S, Ostre Aker Vei 99, Veitvet, Oslo 5.

Tel: 22 15 00 90 Tx: 11963

Sweden Fertronic AB, Box 56, 161 Bromma. Tel: 08-52 26 10

UNITED KINGDOM Celdis-SDS 37-39 Loverock Road, Reading, Berks RG3 1ED.

Tel: 0734 582211/585171 Tx: 848370

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Birmingham B19 3LP. Tel: 021 236 8541 Tx: 338731

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Semiconductor Specialists (UK) Ltd., Carroll House, 159 High Street,

West Drayton, Middlesex UB7 7QN. Tel: 08954 45522 Tx: 21958

*Best Electronics (Slough) Ltd., Fairbank House, Longwick Road,

Princes Risborough, Bucks HP17 9HE Tel: 084-44-7881

UNITED STATES OF AMERICACalifornia Plessey Semiconductors, Irvine. Tel: 714 540 9979

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New York Plainview Electronic Supply Corp., Plainview. Tel: 516 822 5357

Texas Patco Supply, Arlington. Tel: 817 649 8981

WEST GERMANY Nordelektronik GmbH KG, Harksheider Weg 238-240, 2085 Quickborn.

Tel: 04106/4031 Tx: 02 14299Halbleiter-Spezialvertrieb, Carroll & Co. GmbH, Burnitzstresse 34,

6000 Frankfurt/M-70. Tel: 0611/638041-42 Tx: 04 11650

Astronic GmbH & Co. KG, Winzererstrasse 47D, 8000 Munchen 40.

Tel: 089/304011 Tx: 05 216 187

Neumuller GmbH, Eschenstrasse 2, 8021 Taufkirchen b. Munchen.Tel: 089/61181 Tx: 05 22106Micronetics GmbH, Weilder Stadter Str. 55a, 7253 Renningen 1.

Tel: 07159/6019 Tx: 07-24708

*T.V. circuits only

112

'

PLESSEYPlesaey Semiconductors LimitedKembrey Park, Swindon, Wiltshire SIM2 SBATelephone: Swindon (0793) 694994 Telex: 449637Facsimile: Swindon (0793* 41969 Cables: Pleschen Swindon

crtfirf staff? (Cheney Manor Site: Telephone: Swindon (0793) 36251)

CUSTOMER SERVICE

with compliments

I\jifwww\ PLESSEYSemiconductorsPlessey Semiconductors Limited,Kembrey Park, Swindon,Wiltshire, SN26BA,United Kingdom.Tel: (0793) 694994 Telex:449637

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