the isro technical standard for manufacture, procurement ......isro-pax-304 issue-1, august 1990...

SAC/PCB-Team/06

March, 2018

SPACE APPLICATIONS CENTRE

AHMEDABAD

The ISRO Technical Standard

For

Manufacture, Procurement & Qualification

Of

Printed Circuit Boards

SAC/PCB-Team/06

March 2018

MANUFACTURE, PROCUREMENT AND QUALIFICATION

OF

PRINTED CIRCUIT BOARDS

Legal Disclaimer and Copy Right

All rights reserved with ISRO.

ISRO disclaims any liability or responsibility to any individuals or entity with respect to any loss or damage caused or alleged to be caused, directly or indirectly by the use and application of this ISRO

standard.

This standard shall not be copied or reproduced in any manner either in part or whole with or without alternation / modification.

Change Log/ Revision History

The next revision becomes due in February 2021…

Issue No./ Doc. No. Document Title Summary of Change/ Revision

First Issue /

ISRO-PAX-304 Issue-1,

August 1990

Test Specifications for Multi-layer


… drafted for 10-layer MLB …

Second Issue /


June 2014

Test Specifications and

Requirements for Multilayer


… upgraded to address 14-layer stack …

Includes double side (Merging ISRO-PAX-302

herein)

wider reference of ESA and IPC stds,

pictorial/ photographic (color) representation

of features,

Elaborate Qualification program covering

Evaluation and Facility audit followed by

Qualification Program

Handling and storage precautions included

Inspection/ Test Report Formats included

Data pack with deliverables covered

Pictorial Representation of defects covered in

Annexures

Third Issue /


February 2018

Specifications and Qualification

Requirements for Printed Circuit

Boards

Re-formatted and Re-written to cover

Procurement specifications and Qualification

requirements for different PCB technologies

like Rigid, Rigid-flex, HDI/sequential-build,

RF/mixed-dielectric boards.

Documemt & Control Data Sheet

1. Report No. SAC/PCB-Team/06, March 2018

2. Title & Subtitle The ISRO Technical Standard for Manfacture, Procurement & Qualification of Printed Circuit Boards

3. Type of Report Technical

4. No. of Pages & Figures 125 & 09

5. Prepared By PCB Task Team, Neeraj Mishra, SNPA R. Senthil Kumar, MRSA Aditya Sharma, ESAA Archana Bhatt, SRG Mukesh Patel, SRG R. K. Hegde, SRG

6. Reviewed By Shri R. M. Parmar, Shri R. K. Dave

7. Orignating Unit Space Apllications Centre, Ahmedabad

8. Abstract This standard gives details of PCB quality classifaction, supplier/facility data interface, line certifcation, qulification requirements for space use PCBs & quality conformance requirements.

9. Key Words Procurement, PCB-technology, Gerber-data, Facility-audit, Evaluation, Test-plan, Rapid Thermal-cycling, Batch-acceptance, Re-lifing

10. Security Classification Wintin ISRO

11. Distribution Within ISRO

INTRODUCTION PCBs are the basis of wired Electronic assemblies, required to support not only electrical interconnections for the circuitry, but also to function as a mechanical as well as thermal base on which the circuit is built. It is of prime importance that the PCB shall withstand all thermo-mechanical stresses of assembly process like handling, component-soldering, cleaning, rework & repairs, etc. without any functional deterioration. Additionally, these PCBs are required to perform in rocket launch and spacecraft environment that demands very high mechanical, compositional as well as constructional integrity. Hence, this standard specifies the requirements for qualification testing and quality assessment methodology, covering material, PCB technologies of interest, tests and acceptance criteria for ISRO use. The document also defines the procurement requirements as per quality classification of PCBs for ISRO use.

Contents 1.0 SCOPE AND APPLICABILITY .................................................................. 15

1.1 Scope .................................................................................................. 15

1.2 Applicability ........................................................................................ 15

2.0 APPLICABLE DOCUMENTS .................................................................... 16

2.1 Reference Standards/ Documents .................................................... 16

2.2 Order of Precedence .......................................................................... 17

3.0 TERMS, DEFINITIONS AND ABBREVIATIONS ....................................... 18

3.1 Terms and Definitions ........................................................................ 18

3.2 Abbreviations ..................................................................................... 23

4.0 GENERAL REQUIREMENTS .................................................................... 24

4.1 PCB Quality Classification ................................................................. 24

4.1.1 Class A PCBs ................................................................................ 24

4.1.2 Class B PCBs ................................................................................ 24

4.1.3 Class C PCBs ................................................................................ 24

4.1.4 Class M PCBs ................................................................................ 25

4.2 PCB Technology ................................................................................. 25

4.3 Line Certification Activity .................................................................. 25

4.4 Defect Classification & Non-conformance ....................................... 25

4.4.1 Defect Classification & Description ............................................. 25

4.4.2 Non-Conformance Management .................................................. 25

4.4.3 Success Criteria ............................................................................ 26

5.0 PROCUREMENT ....................................................................................... 27

5.1 General ................................................................................................ 27

5.2 Procurement Specifications .............................................................. 27

5.3 Performance Specification Generation ............................................. 27

5.4 Ordering Inputs .................................................................................. 27

5.4.1 PCB Ordering Information ............................................................ 27

5.4.2 Applicable formats ........................................................................ 28

6.0 LINE CERTIFICATION PROGRAM ........................................................... 30

6.1 Scope of Line Certification ................................................................ 30

6.2 Request for Qualification ................................................................... 30

6.2.1 Process Identification Document ................................................ 30

6.2.2 Vendor Process capability ........................................................... 30

6.3 Capability Evaluation ......................................................................... 30

6.4 Facility Audit ....................................................................................... 31

6.5 Qualification Program ........................................................................ 31

6.5.1 Commencement of Qualification ................................................. 31

6.5.2 Qualification Program Implementation ....................................... 32

6.5.3 Qualification Categories ............................................................... 32

6.6 Qualification Approval ....................................................................... 33

6.7 Process Change (PID modification) .................................................. 33

6.8 Qualification PCBs ............................................................................. 33

6.8.1 General Requirements .................................................................. 33

6.9 Qualification Test Vehicle Design ..................................................... 34

6.10 Qualification Test Plan ....................................................................... 34

6.11 Quality Specifications ........................................................................ 34

6.12 Maintenance of Qualification ............................................................. 34

7.0 Test Methods and Specifications ........................................................... 35

7.1 General ................................................................................................ 35

7.2 Cleaning .............................................................................................. 35

7.3 Bare Board Testing (BBT) .................................................................. 35

7.4 Visual Examination............................................................................. 35

7.5 Dimensional Verification .................................................................... 35

7.6 Dehumidification/Baking ................................................................... 36

7.7 Insulation Resistance ......................................................................... 36

7.8 Dielectric with standing voltage ........................................................ 36

7.9 Peel Strength ...................................................................................... 37

7.10 Coating Adhesion (Tape Testing) ...................................................... 37

7.11 Solderability ........................................................................................ 37

7.12 Metallographic Inspection using Microsectioning ........................... 38

7.13 Warp or Bow ....................................................................................... 38

7.14 Twist .................................................................................................... 39

7.15 Reflow Simulation (Convection Reflow) ........................................... 39

7.16 Solder-bath Float ................................................................................ 40

7.17 Solder-dip ........................................................................................... 41

7.18 Rework Simulation ............................................................................. 41

7.19 Bending Flexibility.............................................................................. 42

7.20 Flexible Endurance or Fatigue Test .................................................. 43

7.21 Temperature Storage ......................................................................... 44

7.22 Thermal Cycling Test ......................................................................... 44

7.22.1 Conventional Method ................................................................... 44

7.22.2 Rapid Thermal Cycling (Optional) ............................................... 45

7.23 Long Term Damp Heat (Humidity) Test ............................................ 46

7.24 Temperature Humidity Bias (THB) .................................................... 46

7.25 Conductive Anodic Filament (CAF) Resistant Test ......................... 46

7.26 Control Impedance ............................................................................. 46

7.27 Dielectric Constant and Dissipation Factor (Optional) .................... 47

7.28 Plated Copper Purity, Tensile Strength and Elongation .................. 47

7.29 Analysis of Sn-Pb Coating ................................................................. 47

7.30 Flammability ....................................................................................... 47

7.31 Outgassing (Optional) ........................................................................ 48

7.32 Offgassing .......................................................................................... 48

7.33 Thermal Analysis (Optional) .............................................................. 48

7.34 Compatibility of Gold Plating for wire/ribbon bondability ............... 48

7.35 Compatibility of Adhesive and Conformal Coating materials ......... 48

8.0 QA IN MANUFACTURING AND DELIVERY ............................................. 50

8.1 Overview ............................................................................................. 50

8.2 Product Quality Compliance .............................................................. 50

8.3 QA Requirements for PCB Batch Manufactured .............................. 50

8.4 Production Batch/ Lot ........................................................................ 50

8.5 Quality Records .................................................................................. 50

8.6 Control of Raw Materials & Chemistry .............................................. 51

8.7 Traceability ......................................................................................... 51

8.8 Calibration .......................................................................................... 52

8.9 Cleanliness in Processing ................................................................. 52

8.9.1 Clean environment ........................................................................ 52

8.9.2 Cleaning ........................................................................................ 52

8.9.3 Inspection ...................................................................................... 52

8.10 Operator and Inspector Training ....................................................... 52

8.11 Non-conformance Control Mechanism ............................................. 53

8.12 Packaging and Delivery ..................................................................... 53

9.0 PCB QUALIFCATION REQUIREMENTS .................................................. 54

9.1 General ................................................................................................ 54

9.2 Rigid PCB ............................................................................................ 54

9.2.1 General .......................................................................................... 54

9.2.2 PCB Build Up ................................................................................ 54

9.2.3 PCB Dimension ............................................................................. 56

9.2.4 Thickness of PCB ......................................................................... 56

9.2.5 PCB Acceptance Procedure ......................................................... 56

9.2.6 Qualification Test Vehicle Description ........................................ 56

9.2.7 Production of Qualification PCBs ................................................ 58

9.2.8 Qualification tests ......................................................................... 58

9.3 Requirements of Rigid-Flex PCBs ..................................................... 61

9.3.1 Material Selection ......................................................................... 61

9.3.2 PCB Surface finish ........................................................................ 61

9.3.3 PCB Build-up Design .................................................................... 61

9.3.4 PCB Dimension ............................................................................. 62

9.3.5 Thickness of the PCB ................................................................... 62

9.3.6 Bending Radius Requirements .................................................... 63



9.3.1 Qualification Tests ........................................................................ 63

9.3.2 Applicability of Qualification Testing .......................................... 65

9.4 Requirements for RF (High Frequency) and Hybrid PCBs .............. 65

9.4.1 Material Selection ......................................................................... 65


9.4.3 PCB Surface finish ........................................................................ 65

9.4.4 Thickness of RF PCB .................................................................... 66




9.4.8 Hybrid PCBs .................................................................................. 68

9.4.9 Applicability of Testing................................................................. 68

9.5 Requirements for HDI and Sequential Build-up PCBs ..................... 69

9.5.1 General .......................................................................................... 69


9.5.3 Dielectric Thickness ..................................................................... 69

9.5.4 HDI Types ...................................................................................... 69

9.5.5 Thickness of PCB ......................................................................... 71




9.5.9 Applicability of Testing................................................................. 73

10.0 PCB BATCH ACCEPTANCE ................................................................. 74

10.1 General ................................................................................................ 74

10.2 BAT/QCI Procedure ............................................................................ 74

10.2.1 Facility Outgoing QCI Test Flow .................................................. 74

10.2.2 BAT Tests ...................................................................................... 75

10.2.3 BAT Deliverables .......................................................................... 76

10.2.4 Incoming Acceptance by PCB procurement authority ............... 76

10.3 BAT Test Coupons ............................................................................. 77

10.3.1 Coupon Designations ................................................................... 77

10.3.2 Coupon Grouping in Panel ........................................................... 77

10.4 Placement of Batch Test Coupons .................................................... 78

10.5 Batch Workmanship ........................................................................... 79

10.6 Non-Conformance (NC) Management ............................................... 79

10.6.1 NC Control at Vendors’ End ......................................................... 79

10.6.2 NC Management by ISRO-QA....................................................... 79

11.0 ACCEPTANCE CRITERIA ..................................................................... 80

11.1 Overview ............................................................................................. 80

11.2 Verification of Marking ....................................................................... 80

11.3 Categories of PCB Inspection ........................................................... 80

11.3.1 Dimensional Measurements ......................................................... 80

11.3.2 External Visual .............................................................................. 82

11.3.3 Electrical ........................................................................................ 86

11.3.4 Physical ......................................................................................... 87

11.3.5 Mechanical .................................................................................... 88

11.3.6 Internal Visual & Micro sectioning ............................................... 90

11.3.7 Post Test Monitoring .................................................................... 98

12.0 HANDLING, STORAGE AND RE-LIFING ............................................ 100

12.1 Overview ........................................................................................... 100

12.2 Handling Precautions ....................................................................... 100

12.3 Packing and storage ........................................................................ 100

12.4 Shelf-life & Re-lifing of Stored PCBs .............................................. 101

13.0 OTHER TECHNOLOGIES NOT COVERED ......................................... 102

13.1 PCBs with Embedded Passives ......................................................... 102

13.2 Flexible PCBs ..................................................................................... 104

13.3 Lead-less finish .................................................................................. 105

LIST OF ANNEXURES Annexure 1: PCB Design Feature and Impact Trade off .............................................................................. 106

Annexure 2 Process Capability Format (for reference only) .............................................................................. 108

Annexure 3: Facility Audit format for PCB Manufacturing ................................................................................ 113

Annexure 4: Acceptance Tests......................................................................................................................... 115

Annexure 5: Mechanical Inspection Report Format ......................................................................................... 116

Annexure 6: Micro section and Report Format A ............................................................................................. 117

Annexure 7: Micro section and Report Format B ............................................................................................. 118

Annexure 8: Coupon Test Result Format .......................................................................................................... 119

Annexure 9: Final Inspection Report Format .................................................................................................... 121

Annexure 10: Non Conformance Report .......................................................................................................... 123

Annexure 11: Typical Micro Section Defects..................................................................................................... 124

LIST OF FLOW CHARTS Flowchart 9-1: Qualification Test Matrix for Rigid and Hybrid PCBs ............................................................ 59

Flowchart 9-2: Qualification Test Matrix for Rigid-flex PCBs ........................................................................ 64

Flowchart 9-3: Qualification Test Matrix for RF PCBs .................................................................................... 67

Flowchart 9-4: Qualification Test Matrix for Sequential Build-up and HDI PCBs ......................................... 72

Flowchart 10-1: Panel wise BAT Acceptance Procedure................................................................................ 75

LIST OF FIGURES Figure: 7-1: Bending Flexibility Test ................................................................................................................ 42

Figure: 9-1: Example of a build-up of a 6 layer symmetric rigid-flex ............................................................ 62

Figure: 10-1: Coupon grouping for Horizontal and Vertical Placement in Panel ......................................... 77

Figure: 10-2: BAT Coupon Placement Diagram ............................................................................................. 79

Figure: 13-1: Embedded R & C ...................................................................................................................... 102

Figure: 13-2: Distributed C plane .................................................................................................................. 102

Figure: 13-3: Flex card along with harness .................................................................................................. 104

Figure: 13-4: Example of Sculptured flex card ............................................................................................. 104

Figure: 13-5: Typical PCB Microsection Defects ............................................................................................... 124

LIST OF TABLES Table 2-1: List of Reference Documents 16

Table 5-1: PCB Ordering Information 27

Table 8-1: Specification for PCB finishes 51

Table 9-1: As-designed and As-manufactured copper foil thickness 54

Table 9-2: PCB Surface finish Requirements and Applicability 55

Table 9-3: Detail of Test Pattern Design, Frequency and its location 57

Table 9-4: Matrix for Applicability of Testing 60

Table 9-5: HDI Type/classification 70

Table 10-1: BAT Tests & Applicability 75

Table 10-2: Test Coupon Description 77

Table 11-1: PCB External Dimensional Requirements 80

Table 11-2: Warp Requirements 81

Table 11-3: Specific Dimensional Requirements 81

Table 11-4: Subsurface Visual Aspects 82

Table 11-5: Conductor Pattern Requirements 84

Table 11-6: PTH Requirements 85

Table 11-7: Solder mask Requirements 86

Table 11-8: Insulation Resistance Intralayer 87

Table 11-9: Insulation Resistance Interlayer 87

Table 11-10: DWV Requirements 87

Table 11-11: Water Absorption Requirements 87

Table 11-12: Outgassing Requirements 88

Table 11-13: Peel Strength Requirements 88

Table 11-14: Solderability Requirements 89

Table 11-15: Internal Visual Aspects 90

Table 11-16: Etch Profile Requirements 93

Table 11-17: PTH Aspects 93

Table 11-18: Post Thermal Stress and Environmental Test Requirements 98

Table 12-1: PCB Shelf Life and Re-lifing Requirements 101

1.0 SCOPE AND APPLICABILITY

1.1 Scope

This document defines the quality Requirements for Printed Circuit boards (PCB) under Procurement activity, Qualification activity and subsequent Maintenance of Qualification (or Verification of Qualification, viz. VOQ) activity. This document covers following PCB types

i. Rigid, DSB/MLB ii. Rigid Flex,

iii. RF (including Hybrid or Mixed Dielectric) iv. Sequential and HDI (including Rigid-Flex)

Additional details are as given in 9.0. The document does not enforce the PCB fabricating Agency/ facility to procure material from specific source, or to adopt specific chemistry for fabrication, or to limit the production as per this document. However, the product offered shall meet all the requirements for material quality, product quality and reliability for space use as required by ISRO, and also the chemistry in general be made known to ISRO for choice of use.

1.2 Applicability

Unless otherwise specified, this document is applicable to all PCBs used in ISRO Projects. This is applicable to PCBs fabricated In-house as well as Vendor’s Facility. This document is applicable to PCBs meant for operations up to temperature of 125 °C, while the current rating requirements shall be as per para 6 of ISRO-PAX-301.

DJBhatt

Highlight

2.0 APPLICABLE DOCUMENTS

The following documents form a part of this standard to the extent specified herein. The latest version as on the date of Request For Proposal (RFP) shall be followed unless otherwise stated.

2.1 Reference Standards/ Documents

Table 2-1: List of Reference Documents

Number Standard Name

ISRO Standards

ISRO-PAS-100 Non Conformance Control Requirements for ISRO Projects

ISRO-PAS-207 Storage, Handling & Transportation Requirements for ElectronicHardware

ISRO-PAX-300 Workmanship Standards for the Fabrication of Electronic Packages

ISRO-PAX-301 Design Requirements for Printed Circuit Board Layouts

ESA Standards and Specifications

ECSS-Q-ST-70-02C Thermal vacuum outgassing test for the screening of space materials

ECSS-Q-ST-70-08 Manual Soldering of High-reliability electrical connections

ECSS-Q-ST-70-12 Design Rules for Printed Circuit Boards

ECSS-Q-ST-70-38 High-Reliability soldering for surface-mount and mixed technology

ECSS-Q-ST-70-60C Qualification & Procurement of Printed Circuit Boards

MIL Standards and Test Specifications

MIL-STD-202 Test methods for electronic and electrical Components parts

MIL-PRF-31032B General Specification For Printed Circuit Board/Printed Wiring Board,

IPC Standards and Specifications

IPC-A-600J Acceptability of Printed Boards

IPC-TM-650 Test Methods Manual

IPC-SM-840 Qualification and Performance of Permanent Solder Mask

IPC-2221A Generic Standard on Printed Board Design

IPC-2222A Sectional Design Standard for Rigid Organic Printed Boards

IPC-2223D Sectional Design Standard for Flexible/ Rigid-Flexible Printed Board

IPC-2226A Sectional Design Standard for High Density Interconnect (HDI) Printed Boards

IPC-2252 Design Guide for RF/ Microwave Circuit Boards

IPC-4101E Specification for base materials for Rigid and Multilayer Printed Boards

IPC-4202/3A/4A Base Dielectrics/ Cover & Bonding Material/ Metal Cladding for Flexible Printed Circuitry

IPC-4104 Specification for High Density Interconnects & Microvia Materials

IPC-4103A Specification for Base Materials for High Speed/ High Frequency Applications

IPC-6012D Qualification& Performance Specification for Rigid Printed Boards

IPC-6013C Qualification & Performance Specification for Flexible Printed Boards

IPC-6016 Qualification & Performance Specification for High Density Interconnect Layer or Boards

IPC-9151D Process Capability, Quality and Relative Reliability, Benchmark Test Standard

IPC-9252 Guidelines and Requirements for Electrical Testing of Unpopulated Printed Boards

2.2 Order of Precedence

The PCB requirements, detailed in the RFP, shall be as specified herein. In the event of a conflict between the requirements provided in this specification and requirements of the detailed specification included in the RFP, the following order of precedence shall apply:

a. Detailed specifications included in RFP b. Requirements as per this document. c. Other standards/documents as per the order referred in Table 2-1.

3.0 TERMS, DEFINITIONS AND ABBREVIATIONS

3.1 Terms and Definitions

Annular Ring The portion of conductive material completely surrounding a hole. Assembly A number of pats or subassemblies or any combination thereof joined together. Batch A group of PCBs and coupons that are covered by the same CoC and the same process traveller, processed approximately at the same time (the terms “lot” and “work order” are synonymous). Blister A localized swelling and separation between any of the layers of a laminated base material or between base material and conductive foil. Board Thickness The thickness of the metal clad base material including conductive layer or layers (May include additional plating and coating depending upon when the measurement is made). Bow/Warp The deviation from flatness of a board characterized by a roughly cylindrical or spherical curvature such that, if the board is rectangular, its four corners are in the same plane. Conductor Spacing The distance between adjacent edges of isolated conductive patterns in a conductor layer. Conductor Width The width of a conductor at any point chosen at random on the printed board normally viewed from directly above. Contamination Foreign material embedded in dielectric material, can be organic, metallic, particulate or fibers, synonyms with inclusion, foreign material, debris, etc. Coverlay Thin dielectric material used to encapsulate circuitry, most commonly for flexible circuit applications (the terms ‘cover layer’ and ‘cover material’ are synonymous). Crazing, of PCB An internal condition that occurs in reinforced laminate base material, whereby glass fibers are separated from the resin at the weave intersections. (This condition manifests itself in the form of connected white spots or crosses that are below the surface of the base material). Crazing, of Solder-mask Network of fine cracks in the solder mask Delamination Separation between plies within a base material, between base material and a conductive foil, or any other planar separation within a PCB. Dewetting Condition that results when molten solder coats a surface and then recedes to leave irregularly‐shaped mounds of solder that are separated by areas that are covered with a thin film of solder and with the base metal not exposed. DSB Double‐sided PCB, printed circuit or printed wiring on both sides of a laminate using a rigid or a flexible base-materials.

ENEPIG A type of PCB finish with the top layer stack made of electroless-Nickel, followed by electroless-Palladium and a top finish of immersion-Gold that aids soldering as well as sire/ribbon bonding ENIG A type of PCB finish with top layer stack made of electroless-Nickel followed by immersion-Gold, conducive for PCBs requiring wire-bonding. Etch Back The controlled removal of non-metallic materials from the side walls of holes in order to remove resin smear and to expose additional internal conductor surfaces. Etch Factor The ratio of, the depth of etch to the amount of lateral etch, Or, the ratio of conductor thickness to the amount of total undercut (on both sides of etched pattern). Gerber (format/ Data) Gerber format is an image file format used to describe the PCB layer images for copper-layers, solder-mask, legend, etc. Glass Transition Temperature (Tg) The temperature at which an amorphous polymer, or the amorphous regions in a partially-crystalline polymer, changes from being in a hard and relatively-brittle condition to being in a viscous or rubbery condition. Haloing Mechanically induced fracturing or delamination, on or below the surface of a base material, that is usually exhibited by a light area around holes or other machined features. HDI PCB PCB incorporating sequential build methodology of PCB manufacture to achieve blind and buried vias with laser-drilling of fine-diameter (0.1mm) holes and thus achieve High density interconnect (HDI) with a higher extent of miniaturization High Frequency (HF) PCB PCB used for high frequency applications, that has specific requirements to the dielectric properties of the base laminates as well as special dimensional requirements to the layout for electrical purposes. Hybrid PCB A type of RF PCB where the laminate material is a mix of FR4 type and PTFE based or Hydrocarbon-based to suit the RF performance with suitable digital, analog and bias stimuli Inclusions Foreign particles, metallic or nonmetallic, that may be entrapped in an insulating material, Conductive layer, plating, base material or solder connection.

Insulation Resistance The electrical resistance of an insulating material that is determined under specific conditions between any pair of contacts, conductors or grounding devices in various combinations. Internal Layer A conductive pattern which is contained entirely within a multilayer printed board. IST or Interconnect Stress Testing A methodology by which laminate in the vicinity of each PTH goes through cyclic heating and cooling phases based on currents passed through closed circuits formed by all PCB PTH and the laminate thermal behavior is continuously sensed, for any change indicating PTH failure, through a shadow circuit of PTH, while a failure constitutes a sensed change of 10% from original value. Key Personnel Personnel with specialist knowledge responsible for defined production or product assurance areas.

Laminate A product made by bonding together two or more layers of material. Layout Layout is one of the design steps for fabrication of PCB. It is drawn on an inch / mm graph paper or directly using CAD software, identifying the conductor pattern, shape, width, length and spacing with other conductor or component. It also gives the orientation, mounting pads, clearance between components, heat sink mounting requirements photo plotting requirements, MLB layer alignment provisions etc. Measling Condition that occurs in laminated base material in which internal glass fibres are separated from therein at the weave intersection. This condition manifests itself in the form of discrete white spots “crosses” that are below the surface of the base material. It is usually related to thermally induced stress. Microsectioning The preparation of a specimen of a material or materials, that is to be used in a metallographic examination. (This usually consists of cutting out a cross-section, followed by encapsulation, polishing, etching, staining etc.) MLB, Multilayer PCB PCB that consist of rigid or flexible insulation materials and three or more alternate printed wiring and/or printed circuit layers that have been bonded together and electrically interconnected. Overhang The sum of outgrowth and undercut. (If undercut does not occur, the overhang is the same as the outgrowth.) Peel Strength The force per unit width required to peel a conductor or foil from the base material. Pin Holes A small hole occurring as an imperfection which penetrates entirely through a layer of material. Plated Through Hole (PTH) A hole in which electrical connection is made between internal or external conductive patterns or both, by the plating of metal on hole wall. Plating Metallic deposit on a surface, formed chemically or electrochemically. Prepreg/B-Stage Resin Sheet of material that has been impregnated with a resin and cured to an intermediate stage. Printed Circuit Board (PCB) A pattern of conductors printed on to the surface of an insulating base to provide interconnection of parts. PCB Manufacturer Entity that manufactures the PCB, Or, the entity supplying PCB to the procurement authority, also termed the Supplier/Facility. Procurement authority Entity that procures the PCB. It can be ISRO center or ISRO-vendor or Sub-vendor to an ISRO-vendor Qualification The confidence that capability/ skill/ expertise required to meet target requirements is available or an assessment methodology that will generate confidence that the capability/ skill/ expertise has the required potential to meet the target requirements Qualifying authority (ISRO-QA)

QA entity of the interacting ISRO centre, or also QA of the Concerned ISRO Centre Registration The degree of conformity of the position of a pattern (or portion thereof), a hole or other feature to its intended position on a product. Reflow Soldering A process for joining parts by tinning the mating surfaces, placing them together, heating until the solder fuses and allowing to cool in the joined position. Resin Recession The presence of voids between the plating of a plated-through hole and the wall of the hole as seen in microsection of plated-through holes that have been exposed to high temperatures Resin Smear Base material resin that covers the exposed edge of conductive material in the wall of a drilled hole. (This resin transfer is usually caused by the drilling operation). Rigid PCB PCB using rigid base materials only. Rigid-flex PCB PCB with both rigid and flexible base materials. Routing or Milling The term ‘routing’ or ‘milling’ indicates a mechanical method that removes a portion of the material outlining a PCB/ test-coupon, using a cutting bit. Solderability The ability of a metal to be wetted by molten solder. Soldering A process of metallurgically joining metal surfaces with solder or a eutectic alloy, without melting the base metal. Scratch Narrow groove in a surface of laminate. Sculptured flex Flexible PCB technology that uses profiled copper tracks Sequential Build PCB technology of ‘multilayer PCB type’, using more than one lamination or drilling step. The opposite is ‘non-sequential’ or common rigid MLB. Test Coupon A portion of the quality conformance test circuitry used for a specific acceptance test or group of related test. Test Point Special points of access to an electrical circuit, used for electrical testing purposes. Twist The deformation parallel to a diagonal of a rectangular sheet such that one of the corners is not in the plane containing the other three corners. Test Pattern Part of the PCB that refers to the copper pattern on and within the PCB laminate for a specific test. Traveler Documentation kept with the batch during the manufacturing processes in which the order of specific processes is recorded Undercut The distance, measured parallel to the surface of a printed board, from the outer edge of a conductor

(excluding over plating and coatings) to the maximum point of the indentation on the same edge of the conductor (refer overhang image). Vendor Agency or party procuring PCBs on behalf of ISRO or as a part of deliverable hardware to ISRO. Via or vertical interconnect access A PTH of fine diameter generally for the purpose of only providing interconnection between top and bottom or interlayer and not for assembly of through-hole component. A blind via is a via open at one surface, top or bottom, but plugged at an interlayer. A buried via is embedded within the layer stack-up of the MLB, existing vertically between two sublayers. Via-in-pad Type of via directly underneath a SMT pad VOQ Verification of Qualification, synonymous with Qualification Renewal, and sometimes also called maintenance of qualification, is an assessment of the manufacturing line for its conformance to the quality requirements of highest technological capability qualified. This may cover an internal assessment of prescribed PCB type, a submission of a PCB from the same batch internally assessed and an audit of facility by the QA entity of concerned ISRO centre.

3.2 Abbreviations

AOI Automated Optical Inspection BBT Bare Board Test BGA Ball Gridded Array CAD Computer Aided Design CCGA Ceramic Column Grid Array CVCM Collected Volatile Condensable Material DWV Dielectric Withstanding Voltage ENEPIG Electroless Nickel, Electroless Palladium, Immersion Gold ENIG Electroless Nickel, Immersion Gold HASL Hot Air Solder leveling HATS Highly Accelerated Thermal Shock FR4 Flame-Retardant, glass-reinforced epoxy resin PCBs HDI High Density Interconnect ICR Interconnection Resistance IST Interconnect Stress Test IR Insulation Resistance MRB Material Review Board / NCRB NA Not Applicable NCRB Non-Conformance Review Board PCB Printed Circuit Board PID Process Identification Document PTFE Poly Tetra Fluoro Ethylene PTH Plated-Through-Hole RFA Request for Approval RFP Request for Proposal RMS Root-Mean-Square SMD Surface Mount Devices HC Horizontal Coupon HV Vertical Coupon TML Total Mass Loss

4.0 GENERAL REQUIREMENTS

4.1 PCB Quality Classification

PCB procured in accordance with this standard shall be one of the four classes i.e M (highest), A, B and C (lowest). Requirements for these classes of PCB are defined in subsequent sections. All PCBs meant for launch vehicle and unmanned spacecraft application shall meet class-A requirements unless specifically mentioned otherwise in the approved Product Assurance plan of the mission/ project and in the Product Assurance section of Preliminary Design Review document. The PCBs meant for a manned spacecraft mission shall meet class-M requirements. For all other applications, quality level of PCBs shall be as specified in the project document/procurement specification.

4.1.1 Class A PCBs

A “Class A” PCB shall be realized on a production line certified as per section 6.0 and shall meet all the PCB acceptance requirements including Quality Conformance Inspection (QCI). Alternatively, a Class-A PCB shall be procured in accordance with the provisions of following standards (listed in order of preference) including requirements related to line/facility/supplier qualification with additional Incoming Acceptance tests by Procuring Authority in accrdance with para 10.2.4.

a. ESCC‐Q‐ST‐70‐60 b. MIL‐PRF-31032B

The PCB layout design of a Class-A PCB shall be in conformance with the requirements of the latest revision of ISRO‐PAX‐301.

4.1.2 Class B PCBs

A “Class-B” PCB shall be realized on a production line certified as per section 6.0 and shall meet all the PCB acceptance requirements except for the provisions of para 10.2.4 . Alternatively, A “Class-B” PCB can also be procured in accordance with requirements given in the following list (in order of preference)

a. Meeting provisions of ESCC‐Q‐ST‐70‐60/ MIL‐PRF-31032B including line/facility/supplier qualification.

b. Meeting provisions of this standard except for line certification requirements, meaning PCB acceptance as given in section 10.0.

c. Meeting provisions of ESA‐Q‐ST‐70‐60/ MIL‐PRF-31032B except for line certification requirements, meaning PCB acceptance as given in section 10.0.

d. Meeting provisions of IPC Class-3 and meeting PCB acceptance requirements as given in section 10.0.

The PCB layout design of a “Class-B” PCB shall be in conformance with the requirements of the latest revision of ISRO‐PAX‐301.

4.1.3 Class C PCBs

A “Class-C” PCB shall meet the material and manufacturing requirements of this standard and shall be compliant to IPC Class‐3. Line/facility/supplier certification is not mandatory for a Class-C PCB . However, it is manadatory that supplier/facility shall clear the PCB from visual inspection and BBT aspects.

DJBhatt

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It is not mandatory for a “Class-C” PCB to meet PCB layout design requirements of ISRO‐PAX‐301.

4.1.4 Class M PCBs

A “Class-M” PCB shall meet all the requirements of Class A. Additionally it shall meet offgassing requirements as per para 7.32 related to hazardous and toxic emissions. If a PCB is intended for more than one application classes, requirements for the highest class of applications shall apply.

4.2 PCB Technology

a. Rigid MLB, non-sequential build, 16-layers or more b. Rigid MLBs with epoxy-filled via, Via-in-pad and cap-plating c. Rigid MLBs with solder-mask on bare copper (SMOBC) d. Rigid MLBs with HASL finish and for wire-bond applications ENIG & ENEPIG finish e. Rigid-flex MLB, 2mil and 6mil double-sided flex and structured flex f. RF/High Frequency PCB with gold-finish g. Mixed Dielectric MLB h. Sequential build MLBs, employing blind via and buried via i. High density Interconnect MLBs, employing stacked via and staggered via

Specific PCB technologies, not covered in standard or formal qualification, can be used when procurement is under Request for Approval (RFA), where the RFP, along with manufacturing and quality specifications, shall request for a Project Qualification, while it can exclude the qualification of the vendor/facility. Any PCB technology covered under Project Qualification shall not automatically be deemed as Qualified for generic flight use.

4.3 Line Certification Activity

Involves facility evaluation, audit and qualification of PCB manufacturing processes. a. The line certification program shall cover the following stages:

i. Request for line certification from the Facility with details of manufacturing capability and a draft PID as per para 6.2.1.

ii. Evaluation of a sample from a specific process to be qualified by the Quality Assurance as per para 6.3 and PID revision if applicable

iii. Evaluation and Audit of the facility by the ISRO-QA 6.4. iv. Execution of Qualification Program as per para 6.5.

b. The Facility approval by ISRO-QA after successful completion of qualification as per this document and finalization of PID

c. Maintenance of Qualification (inclusive of QCI, NC management and VOQ)

4.4 Defect Classification & Non-conformance

4.4.1 Defect Classification & Description

All Defects and deviations leading to rejection are listed in Clause 11, Acceptance Criteria. The acceptance limits with applicable margins are elaborated therein

4.4.2 Non-Conformance Management

a. Major non-conformances leading to impact on reliability or out-right rejection shall be addressed at a non-conformance review board (NCRB) /Task Team established by the appropriate ISRO authority having a representative from the Supplier/facility

b. Minor non-conformances / deviations not impacting reliability shall be disposed off as follows:

i. Impact analysis by QA/QC of the ISRO-QA ii. Processed through an internal NCRB (In-house facility or Vendor/Manufacturer

facility) to determine the causes and consequences iii. Reported in the qualification test report

4.4.3 Success Criteria

Shall meet all the requirements of acceptance as per 0.

5.0 PROCUREMENT

5.1 General

Procurement shall be as per specifications governed by PCB Quality as per Para 4.1.

5.2 Procurement Specifications

The procurement specifications shall contain the following, a. PCB Quality Classification

Shall be as per para 4.1. b. Inputs

The PCB post-processed CAD data, drill details, the layer-stack, the material, the PCB batch identity requirements and the PCB batch size as authorized by Procurement authority

c. Applicable Refrences Shall be as per para 2.1.

d. Deliverables Shall be as per para 10.2.3.

5.3 Performance Specification Generation

Procuring Agency shall generate detailed performance specifications as follows, a. For class A, B and M, the PCB design for targeted performance should be within the

qualified capabilities of the vendor. b. For class C, design should be done considering the critical performance trade offs as per

Annexure 1.

5.4 Ordering Inputs

5.4.1 PCB Ordering Information

PCB ordering information shall be as per the Table 5-1.

Table 5-1: PCB Ordering Information

Sr. No.

PCB Feature PCB Details

1 PCB Title (as per instructions)

2 Card Code (as per instructions)

3 PCB Class A/B/C (as per latest ISRO PAX-304)

4 ISRO coupons to be added in the panel Yes/No

5 Batch testing required at vendors end Yes/No

6 PCB Type Rigid Flexi-Rigid Flex RF HDI Type1 HDI Type2 HDI Type3

6.a In case of Flex or Flexi-Rigid, thickness of flex core

2/4/6 mil

7 PCB quantity

Sr. No.

PCB Feature PCB Details

8 PCB External dimensions L x W (mm)

9 Material Glass Epoxy/Polyimide/Duroid (PTFE)/Hybrid

10 Finish HASL/ENIG/ENEPIG/Hard Gold/Soft Gold/No Finish (Cu)

11 Solder Mask Required/not required/material/glossy or matte/Selective only

11.a Solder Mask thickness

11.b Solder mask tenting on vias Required/not required

12 Legend Required/not required

13 Construction Foil/Laminate

14 No. of layers Refer Note 1 Below

15 PCB Thickness Refer Note 1 Below

16 Inner Layer Cu thickness ¼, ½, 1, 2 Oz.

17 Outer Layer base Cu thickness ¼, ½, 1, 2 Oz.

18 Outer layer finish Cu thickness ¼, ½, 1, 2 Oz.

19 PTH Yes/ No

20 NPTH Yes/ No

21 Blind via Layer wise detail

22 Buried via Layer wise detail

23 Via filling Yes/No

23.a Via filling and cap plating Yes/No

24 Controlled impedance requirements Yes/No

24.a If Yes, then layer wise details

24.b Impedance coupons required to be added in panel

Yes/No

25 Minimum Line definition (mil) 4/ 5/ 6 ….

26 Minimum Spacing (mil) 4/ 5/ 6 ….

27 Minimum PTH drill dia (mil) 4/ 6/ 8 ….

28 Internal Cut-outs Yes/No

29 IPC netlist provided Yes/No

30 Urgency Yes/No

Notes:

1. PCB thickness shall be subject to following limitations: Minimum dielectric separation of 70 microns for rigid and 25 microns for flex Qualified capabilities of the facility Lead length of component to be soldered Mechanical rigidity requirements for the PCB.

5.4.2 Applicable formats

Layers : Gerber 274X Drill (PTH/NPTH/Blind/Buried) : Gerber274X/Excellon2 Solder Mask : Gerber 274X

Legend Print (Silk Screen) : Gerber 274X Stackup : DOC/PDF Controlled impedance : DOC/PDF Fabrication Drawing : Gerber 274X/DOC/PDF Reports : Text/DOC/PDF All the above data may also be provided in ODB++ format.

6.0 LINE CERTIFICATION PROGRAM

6.1 Scope of Line Certification

Involves facility evaluation, audit and qualification of PCB manufacturing processes. a. The line certification program shall cover the following stages:

i. Request for line certification from the Supplier/facility with details of manufacturing capability and a draft PID as per para 6.2

ii. Capability Evaluation through assessment of a sample from a specific process to be qualified by the QA entity of the concerned ISRO centre as per para 6.2.

iii. Audit of the Supplier/facility’s facility by ISRO-QA as per para 6.4. iv. Execution of Qualification Program as per para 6.5 with PID revision if applicable

b. The approval from the ISRO-QA after successful completion of qualification as per this document and finalization of PID.

c. Verification of Qualification or Qualification Renewal (also sometimes referred as Maintenance of Qualification).

6.2 Request for Qualification

a. The Supplier/facility shall send a formal request for qualification to the ISRO-QA. b. The Supplier/facility shall provide documentary proof of his technological capability. c. The Supplier/facility shall also submit a draft Process Identification Document on the

process he wishes to adopt for the fabrication of PCBs for space use.

6.2.1 Process Identification Document

Before commencement of qualification activity, the manufacturer shall submit a draft copy of the process identification document (PID) which specifies the process steps and specifications that shall apply to meet the high reliability requirements of space use. The PID shall contain the following as a minimum

a. Production flow chart b. Specification of raw materials and semi-finished products that are part of the product c. Equipment & Machines used in the fabrication process d. Process specifications and tolerances e. In-process quality control inspection stages f. Accept/reject criteria for in-process QA/QC g. Process traveler formats h. Non Conformance management i. Functions of all key personnel involved

The draft PID shall be reviewed and approved by ISRO-QA prior to commencement of the qualification of the process. The stages of ISRO interaction shall be identified in advance as mutually agreed between Supplier/facility (henceforth referred as Facility) and ISRO-QA.

6.2.2 Vendor Process capability

Vendor shall submit details of process capability in the format similar to that provided in the Annexure 2. for reference or in a format that conveys the actual process technology expertise residing with the facility that can be readily demonstrated.

6.3 Capability Evaluation

Subsequent to the facility request to ISRO-QA, the facility shall supply a sample of 03 nos. of evaluation PCBs using Qualification Pattern to representing the facility’s highest manufacturing capability. The

evaluation tests shall be Group-1, Group-2 and Group-4 of the applicable PCB technology. The facility shall produce the evaluation PCBs with the materials, processes and equipment that are intended for use in subsequent production and are a part of submitted draft PID. The evaluation PCBs shall be representative in terms of technology for which the Supplier/facility applies for qualification and shall broadly cover

a. Dimensions of the boards, vias, pads and tracks b. Number of layers c. Pattern design

The evaluation PCBs shall be provided with associated test coupons and traveler sheet. Note - Evaluation tests like, initial visual inspection, solder dip followed by microsection and rework simulation tests on the samples submitted shall be carried out. If samples fail the initial evaluation tests, Supplier/facility shall resupply samples along with close out note and data analysis indicating the root cause of the problem noticed. Subsequently, if such iteration fails the evaluation exercise shall be terminated. ISRO-QA shall generate a Evaluation Test Report. If and only if the result is satisfactory, the qualification programme for the technologies that has been evaluated can be taken up.

6.4 Facility Audit

ISRO- QA shall audit the manufacturing line at the facility when PCB production is in progress. During the audit, the Supplier/facility shall make the following documents available:

a. Names and functions of all key personnel involved including structure of the quality system.

b. Identification of the parameters of the technologies. c. List of materials and equipment (including types and names of companies) used for

production of PCBs. d. Incoming material inspection, certificate of compliance monitoring, in-process inspection

plans. e. List of process and control specifications with number, issue number and date of issue f. Production flowchart, including quality assurance inspection point and relevant process

specification. g. Route card/Traveler card/In-process log sheet of the PCBs under investigation or audit. h. Details of facility like BBT, AOI, Rework mechanisms, metallographic examination,

chemical analysis, failure analysis, mechanical and acceptance test plans. i. Work area segregation .

A format for facility audit is provided in Annexure 3.

6.5 Qualification Program

6.5.1 Commencement of Qualification

The qualification program executed by ISRO-QA shall establish that the facility has the capability to manufacture PCB to meet the quality and reliability requirements for space use and shall follow the steps elaborated below –

a. Facility request for the process qualification received along with submission of brochures regarding process types, infrastructure, equipment, capacity, capability, Draft PID and list of important certifications obtained

b. Documentation review c. Review of results of initial evaluation by and of the PID with required modifications if any d. If PID review results are satisfactory, the facility shall generate the gerber as detailed in

para 9.2.6/9.3.8/9.4.6/9.5.7, as applicable. e. Facility shall then submit to ISRO the panelization scheme of Qualification test pattern

PCB and coupons for review and approval. f. Commencement of PCB fabrication strictly as per PID and submission of samples as per

9.0 for specific technology. g. Facility shall conduct acceptance tests (out-going inspection) on one set of coupons

(H & V) from identical panel and on finding it satisfactory, shall submit the Qualification batch along with accetance test results to ISRO-QA.

h. Acceptance tests on any one set of coupons (H & V) from identical panel, by ISRO-QA, from delivered qualification batch and review for conformance with facility acceptance test results acceptability.

i. Execution of qualification testing as per section 9.0 for identifed technology as per this document.

j. In case of non-conformance observed during the qualification, indicating over control in material, processing or outgoing acceptance, the supplier shall resubmit the qualification samples. If two such iterations are unsuccessful qualification exercise shall be terminated.

6.5.2 Qualification Program Implementation

a. The qualification programme shall be executed by ISRO-QA. While the qualification tests may be executed by established test houses, the test results shall be reviewed and approved by ISRO-QA.

b. The qualification testing shall be executed in conformance with the test sequence specified for respective PCB technology given in section 9.0.

6.5.3 Qualification Categories

A. Full Qualification

a. Full qualification shall be applicabe in case of the following, i. New Manufacturing Line

ii. New PCB Technology Qualification iii. Manufacturing line is moved to another location

b. Para 6.3 to para 6.6 shall be applicable

B. Re-Qualification

a. Re-qualification shall be applicabe in case of the following, i. Qualification is more than two years old and maintenance of qualification was

not assured ii. Interruption in the manufacturing of the PCBs for more than two years after

initial qualification iii. 10% rejects or drift in quality in preceding 12 months

b. Para 6.5 and para 6.6 shall be applicable c. ISRO-QA shall have the right to decide the stage and extent of re-qualification

C. Verification of Qualification

Required for a Qualified facility and technology every two years. VOQ shall be performed to assess quality conformance with initial qualification requirements, as defined in this document, by ISRO-QA. The following shall be a part of the VOQ,

a. This shall be initiated by facility two months in advance of expiry of the qualification. b. Facility shall provide the following,

i. A PCB from the normal production batch representing the highest manufacturing capability qualified, with associated coupons.

ii. A test report on evaluation of a PCB from the same batch. iii. All necessary documents and records of PCBs delivered in the time from issue of

existing Qualification. c. An audit of the facility shall be conducted by ISRO-QA d. On successful completion of VOQ, a report shall be generated and a new certificate shall

be issued by ISRO-QA to the supplier/facility.

D. Delta Qualification

Delta Qualification shall be carried out by ISRO-QA for any incremental process change by the facility with regards to mechanical process parameters or chemical process parameters or capability enhancement. This qualification test flow shall assess thermo-mechanical integrity, chemical stability and conformance to tolerances specified in this document. The tests applicable to carry out specific Delta Qualification becomes necessary are given in Table 9-4.

E. Project (or Design) Specific Qualification

The Project specific qualification shall be applicable for Class-A & M PCB quality and shall be carried out by ISRO-QA, with an assessment of the risk constraints, for technologies not available with qualified sources. However, this qualification shall be applicable for the batch so tested. This shall call for special approval termed as Request for Approval (RFA). The tests applicable to carry out Project Qualification are given in Table 9-4.

6.6 Qualification Approval

a. On successful qualification test program ISRO-QA shall provide a provisional clearance for the supplier/facility of onboard use PCBs.

b. ISRO-QA shall grant the qualification approval to a supplier/facility based on acceptance of evaluation in accordance with para 6.3, the audit in conformance with para 6.4, the qualification programme detailed in para 6.5 and submission of final PID.

c. Qualification Approval shall be valid for a period of maximum two years. d. ISRO-QA shall have the right to withdraw the qualification status in case of the following,

i. Frequent batch rejection in PCBs delivered ii. Repeated non-conformances observed during facility audit

iii. Process Changes with respect to PID not approved by ISRO-QA iv. Requirements of VOQ are not met

6.7 Process Change (PID modification)

a. A process change shall constitute of any intended alteration in process parameters, chemistry, material, equipment and layout, process flow, team-members and inspection

b. While all process change notices shall be submitted to ISRO-QA, the major changes shall be approved by ISRO-QA

6.8 Qualification PCBs

6.8.1 General Requirements

a. The qualification PCBs shall have test patterns as given in the ISRO approved gerber file

which includes patterns for evaluation of the specific characteristics, summarized in Table 9-3.

b. The qualification PCB shall consist of a test pattern demonstrating the declared technological capability of the facility together with the other test patterns.

c. The test pattern layout and design shall be in conformance with the design shown in this document.

6.9 Qualification Test Vehicle Design

a. Qualification test vehicle shall consist of all the test patterns identified in section 9 for the identified technology

b. The Qualification test-pattern layout shall be in conformance with latest revision of ISRO-PAX-301 for design rules, while layout schemes shall be as per relevant IPC test patterns.

c. The qualification test pattern shall be representative of the highest technological complexity for which qualification is requested.

d. The design of the qualification test vehicle shall accommodate the tests specified in section 9.

e. The coupons that are included in the qualification vehicle shall be in conformance with section 10.0.

6.10 Qualification Test Plan

This shall be applicable for specific technology as per section 9.0.

6.11 Quality Specifications

The quality specifications and accept/ reject criteria are as per section 0.

6.12 Maintenance of Qualification

Maintenance of certification shall be carried out in the following manner a. Facility audit at supplier/facility site shall be carried out by ISRO-QA, periodicity being as

per assessment of ISRO-QA or as agreed up on between ISRO-QA and the facility b. Verification of Qualification shall be carried out once in every two years or if the

manufacturer has not supplied flight grade PCBs for past six months c. Re-qualification shall be carried out, if;

i. Consistency in the quality is not maintained & assured ii. Changes made in the process, materials, PID, devices, laminates, key personnel or

changing of equipment layout (Plant layout) The line shall hence, be declared as certified to carry out production and delivery of flight model (FM) PCBs, to ISRO or ISRO Vendors, for the qualified technology. This information shall be made available on Centre Portal or DSRQ Repository to achieve optimal benefit of the Qualification activity carried out by an ISRO Centre.

7.0 Test Methods and Specifications

7.1 General

Unless otherwise specified, all tests except environmental tests shall be conducted under the conditions specified below,

a. Room temperature: (22 ± 3) °C b. Relative humidity: (55 ± 10)% c. Normal Atmospheric pressure

Following precautions shall be taken while testing, a. Keep the PCBs flat against a plane surface b. Before start of the any test program, All PCBs & test coupons shall be cleaned in

conformance with para 7.2.

7.2 Cleaning

Prior to the test programme all the boards shall be ultrasonically cleaned for 5 minutes using approved solvents. Purity of the cleaning solvent shall be such that any residue does not exceed 5 micro gram/cc of solvent. After cleaning the boards shall be dried at ambient temperature for five minutes.

7.3 Bare Board Testing (BBT)

Bare board Testing shall be performed in accordance with IPC-9252 (Guidelines and Requirements for Electrical Testing of Unpopulated Printed Boards). In case of controlled impedance boards, testing shall be performed to assure the impedance requirements as specified in PCB ordering sheet. Spool/gerber file data used for PCB manufacturing shall be used for extracting the BBT net list. Testing shall be performed for both continuity and isolation. If inner layer net open failure is detected specifically after hot air levelling of PCBs, it shall be reported and all the PCBs from this panel shall be subjected for non-conformance review. Net continuity shall be tested using 100 mA current with 5 ohms or less threshold. Isolation shall be tested with a minimum of 100 mil proximity rule at 250V with a minimum of 6 mega ohms’ threshold. All the power/ ground/split planes shall be tested for isolation with all other nets in the PCB. Bare board test report shall be preserved along with other test reports by the manufacturer. A BBT OK sticker shall be affixed on the board which passes the test. BBT test report shall be provided along with PCBs. BBT sticker shall not leave residues that affect the quality of bare PCBs.

7.4 Visual Examination

This visual inspection test will be conducted for locating the defect related to marking, contamination of particle, laminate defect and other visual associated defects in the PCB as per para 11.3.2. The test shall be conducted for the all PCB & associated test coupons on entire area. The PCB shall be inspected using microscope at minimum 10X magnification with suitable lighting conditions to verify the construction and workmanship requirements. In case of any irregularity, the area shall be examined at higher magnification.

7.5 Dimensional Verification

This test is to find out any dimensional mismatch between PCB and the PCB fabrication document. This verification shall be conducted on the PCBs & associated test coupons as below.

a. The dimensional verification shall be done in accordance with dimensions specified in the PCB fabrication document.

b. Unless otherwise specified; PCB thickness shall be measured between outer conductors of top and bottom layers including finish/coating.

c. Unless otherwise specified; PCB length and width shall be measured at all edges of the PCB.

d. The diameters of all holes should be verified with PCB fabrication document. e. Unless otherwise not specified in the document; the dimensional verification for the vias

of ≤ 0.6 mm may be omitted. f. Unless otherwise not specified in the document; the minimum conductor width and

spacing shall be verified on top and bottom layers. g. Unless otherwise not specified in the document; the conductor width minimum conductor

width and spacing shall be measured at the foot of the conductor. In case overhang or undercut causes the top of the conductor to protrude from the foot, conductor width and spacing shall be measured at the widest point of the conductor.

7.6 Dehumidification/Baking

Baking of PCBs shall be conducted to remove the moisture content in the test PCBs/ coupons prior to any thermal stress test(s) for a minimum of 6 hours at 120°C in ambient pressure.

7.7 Insulation Resistance

The insulation resistance test is to determine the degradation in electrical insulation due to processing chemicals and/or after the exposure of The PCB to high humidity and temperature conditions. This test shall be conducted for all intralayer and all adjacent interlayers on test pattern-E (as per Table 9-3) in conformance with following:

a. A direct voltage of (500 ± 50) V shall be applied between the two closest conductors that are not electrically connected

b. The insulation resistance (R) shall be measured 1 minute after the voltage has been applied

c. The intralayer insulation resistance shall meet the following requirements, i. As received shall be ≥ 10 GOhm

ii. After environmental tests ≥ 1 GOhm d. The interlayer insulation resistance shall meet the following requirements,

i. As received shall be ≥ 100 GOhm ii. Post environmental tests ≥ 1 GOhm

7.8 Dielectric with standing voltage

The dielectric with standing voltage is for measuring the withstand capability of the PCB against the application of high voltage between the isolated regions or the between ground and one of the isolated region on the PCB. This test is for endurance of the use of adequate use of insulating material and conductor spacing in the PCB. This test shall be conducted for all intralayer and all adjacent interlayers on test pattern-E (as per Table 9-3) in conformance with test method 2.5.7d (Condition-B) of IPC-TM-650. In addition to this following shall be considered,

a. The leakage current shall be limited to 100 μA b. Visual inspection shall show no evidence of breakdown, flashover or sparking.

7.9 Peel Strength

This test is to measure the peel strength of metal to the laminate at evaluated temperature. The test also determines the degradation in base material laminate after the test. This test shall be conducted on test pattern-P (as per Table 9-3) in conformance with test method no. 2.4.8c (condition-A) of IPC-TM-650. In addition to this following shall be considered,

a. The conductor selected shall be peeled back at one end for a length of about 10 mm b. The detached end of the conductor shall be firmly gripped over its whole widthISRO-PAX-

304 c. Traction shall be applied in a direction perpendicular to the plane of the PCB until the

copper starts to peel away. d. The rate of traction shall be kept constant at 50 mm/min e. The traction direction shall be kept perpendicular to the plane of the PCB f. Machine inertia shall not have effect on the measurement g. The conductor width to be taken into account shall be the actual width over which the

conductor is adhered to the laminate h. Peel strength shall meet the requirement as listed in 0A.

7.10 Coating Adhesion (Tape Testing)

This test is to determine the adhesion quality of the surface finish used in the PCB. This test shall be conducted on test pattern pattern-P (as per Table 9-3) in conformance with test method no. 2.4.1e of IPC-TM-650.

a. After cleaning, an adhesive tape, at least 50 mm long, shall be applied to the test surface and pressed down to eliminate all air bubbles.

b. After 1 minute, the tape shall be quickly pulled off perpendicular to the coating surface. c. The surface area to be tested shall be at least 1 cm2 of conductor. d. The tape shall have an adhesion of at least 4.4 N/cm. e. The surface finish shall not peel from the test surface or stick to the tape.

After test, visually examination shall be performed on the tape and test area for evidence of any portion of the material tested having been removed from the specimen. If Plating overhang breaks off (slivers) and adheres to the tape, it is evidence of overhang but not an adhesion failure and shall call for rejection.

7.11 Solderability

This test is to determine the quality of soldering of the PCB when the specimen is subjected to soldering operation.

a. This test shall be conducted on test pattern-AB/R (as per Table 9-3).

b. Test pattern shall include hole sizes of maximum or most frequently used dimensions.

c. PCB designs having PTHs may be tested only for hole solderability.

d. Flux used shall conform to the requirements of ISRO-PAX-300 Issue-5 para 5.3

e. The solder shall be Sn 63/37 and conform to ISRO-PAX-300 Issue para 5.2

f. The test machine shall be a rotary dip tester or similar equipment

g. The specimens shall be fluxed by immersion

h. Surplus flux shall be allowed to flow off the specimen by keeping it upright for minimum 1 minute.

i. The solderability test shall be performed with in 1 to 5 minutes after application of flux.

j. The specimen shall be arranged on the soldering machine and brought into contact with

the surface of the solder bath that is kept at the temperature of (235 ±5)°C for 3 seconds.

k. Prior to examination, all specimens shall have the flux removed using approved cleaning solvents as per para 5.4.1 of ISRO-PAX-304.

l. Microsection to be performed for the tested holes and shall be inspected at 100x or higher magnification.

m. Acceptance criteria for PTH and surface solderability shall be in accordance with Table 11-14.

7.12 Metallographic Inspection using Microsectioning

This test is to evaluate and analyse the quality of the laminate system, plating and the plated-through holes (PTHs). Further, the PTHs can be evaluated for characteristics of the copper foils, plating, and/or coatings to determine compliance to the PCB fabrication document. Metallographic sample preparation shall be done in conformance with test method no. 2.1.1e of IPC-TM-650. PCBs/coupons with soft finishes, additional protective plating of nickel (10-15µm) shall be used to avoid the plating desmearing.

7.13 Warp or Bow

This test is to find out the percentage of warp of the rigid PCB and the rigid portion of the flexi rigid PCB. This test shall be conducted on the finished PCBs in conformance with test method no. 2.4.22c of IPC-TM-650.

a. The PCBs shall be placed unrestrained on a plane horizontal surface with the convex side upward.

b. The two corners of the measured edge shall be in contact with the horizontal surface.

c. The warp shall be expressed in percentage terms.

d. The maximum warp between the plane horizontal surface and the PCB shall be measured and shall also meet the requirements as defined in Table 11-2.

e. The length of the PCB shall be measured

f. The warp percentage shall be calculated as per following equation,

Warp or Bow[%] =Max. bow in mm

Length of the PCB in mm∗ 100

g. This test shall not be applicable for RF PCBs fabricated using soft laminate material.

7.14 Twist

This test is to find out the percentage of twist of the rigid PCB and the rigid portion of the flexi rigid PCB. This test shall be conducted on the finished PCBs in conformance with test method no. 2.4.22c of IPC-TM-650.

a. The PCB shall be placed on a plane horizontal surface so that it rests on three corners

b. The twist shall be expressed in percentage terms

c. The distance between the plane horizontal surface and the fourth corner of the PCB shall be measured and shall also meet the requirements as defined in Table 11-2.

d. The length of the diagonal shall be measured

e. The twist percentage shall be calculated as per following equation,

Warp or Bow[%] =Max. bow in mm

Length of the PCB in mm∗ 100

f. This test shall not be applicable for RF PCBs fabricated using soft laminate material.

7.15 Reflow Simulation (Convection Reflow)

This test is used to replicate the thermodynamic effects by assembly on the test specimen. This test is intended to simulate those effects that are the result of soldering thermal excursion during the machine soldering. This test shall be conducted on the Rigid & Hybrid PCB and rigid portion of rigid-flex PCB in conformance with the test method 2.6.27A of IPC-TM-650.

a. This test shall be applicable for rigid and rigid flex PCBs

b. Reflow simulation shall be performed using a convection reflow equipment and process that are representative of assembly

c. The test board shall be demoisturized/baked in conformance with para 7.6.

d. Inter connection resistance (ICR) for all the daisy chain nets shall be monitored using 4-probe test method at ambient conditions & recorded it as a reference.

e. Initial ICR of >15 Ω shall be considered as open circuit in daisy chain.

f. The low temperature profile (230°C) of the method no. 2.6.27A shall be used.

g. The duration at the maximum temperature of the profile shall be between 25s and 30 s.

h. The sample shall be cooled at ambient temperature for at least 10 minutes.

i. Clean the sample with approved cleaning solvents as per para 5.4.1 of ISRO-PAX-304.

j. Resistance of daisy chain shall be recorded after cool down at ambient condition

k. The sample shall be exposed to a second reflow by repeating the steps from requirements of para 7.15 d to 7.15 j.

l. Total three such reflow cycles shall be conducted.

m. Unless otherwise specified, the maximum allowable percent change in resistance for each net shall be 5%.

n. Microsection shall be performed for the evaluation of PTH integrity & dielectric in conformance with Table 11-17.

7.16 Solder-bath Float

This test is used to evaluate the withstanding capability of the thermodynamic effects of the extreme heat to which they may be exposed during the assembly, rework or repair process. This test shall be conducted on to the test pattern-AB/R (as per Table 9-3) conformance with the test method 2.6.8e (condition-A) of IPC-TM-650.

a. This test shall be applicable for RF PCBs fabricated using soft substrates intended to be assembled on to the carrier plate using hot-plate reflow.

b. The test board/sample shall be demoisturized/baked in conformance with para 7.6.

c. The solder bath float shall be performed to one side of the sample by placing it horizontally for 10 s on molten solder, while bath is maintained at 288 ±5°C.

d. The sample shall be removed from the bath and cooled down to ambient conditions for a duration of at least 2 minutes.

e. Clean the sample with approved cleaning solvents as per para 5.4.1 of ISRO-PAX-304.

f. The 10 second float & cooling cycle shall be repeated 3 times.

g. The samples shall be visually inspected for non-conformances like pattern lift, blistering, laminate discoloration etc.

h. Microsection shall be performed for the evaluation of integrity of plating & PTH and dielectric in conformance with Table 11-17.

7.17 Solder-dip

This test is used to evaluate the integrity of the plated through holes for the thermodynamic effects of the extreme heat to which they will be exposed during the assembly, rework or repair process. This test shall be conducted as per the test method 7.16 except the conditions a, c and f. For the above, following shall apply,

a. This test shall be applicable only for Rigid & Hybrid PCBs and the rigid portion of the rigid-flex PCB.

b. The solder bath float shall be performed by dipping of the sample in the molten solder for 10 s in a solder bath maintained at 288 ±5°C.

c. The solder dip test shall be repeated 6 times for qualification and 3 times for quality conformance testing (batch acceptance testing).

7.18 Rework Simulation

This test is used to simualte the procedures for plated through hole (PTH) component removal and replacement , in order to determine the effects of rework on the quality and integrity of the PTH barrel and PTH pads. This test shall be conducted on to the test pattern-AB/R (as per Table 9-3) or on PCB in conformance with the test method 2.4.36C (Method A) of IPC-TM-650. This test shall be performed using the following parameter,

a. The test sample /PCB shall be demoisturized/baked in conformance with the para 7.6.

b. Material used for soldering shall be Sn63/Pb37

c. Soldering tip temperature shall be 260°C (default test condition as per IPC-TM-650)

d. Soldering time shall be limited to maximum 5 seconds

e. After soldering and de-soldering sample shall be allowed to cool down for at least 30 seconds

f. Total 5 cycles of soldering and de-soldering cycles shall be performed

g. Microsection analysis shall be performed on the soldered hole including the wire to evaluate the integrity of plating, PTH and dielectric as per Table 11-17.

7.19 Bending Flexibility

The objective of this test is to determine the adhesion of flex layers and the rigid-to-flex interface. This test shall be conducted on to the test coupon-X (as per Table 9-3) in conformance to para 3.6 of IPC-6013.

a. Test sample shall be the representative of the final PCB layer stack. Preferably this test shall be conducted on to the actual PCBs.

b. This test shall cover only the static application i.e. “flex to assemble”.

c. This test shall be performed using the following parameters,

i. Minimum number of bend cycles for static application shall be 25 ii. The diameter of the mandrel over which the flex laminate is bend shall be ≤ 24 times

of flex portion (including cover-lay) thickness. iii. Unless otherwise specified, bending flexibility test shall conform to

Figure: 7-1.

Figure: 7-1: Bending Flexibility Test

iv. Bend cycle is defined as taking one end of the specimen and bending it around a

mandrel and then bending back to the original starting position, travelling 180 in one

direction and 180 in opposite direction. A bend cycle may also be defined as bending ( using opposite ends ) and then bending them back to the original starting position,

with each end travelling 90 in one direction and 90 in opposite direction.

d. The specified number of bend cycles shall be performed with the mandrel placed in contact with the specimen on one side and then again with the mandrel placed in contact with the specimen on the opposite side.

e. Before and after the test, the resistance shall be measured using 4-wire resistance measurement with the sample in flat condition, bend 90° upwards and bend 90° downwards.

f. The acceptance criteria shall be as follows,

g. Resistance change while testing as per para 7.19 e shall be ≤10%.

h. Visual and microscopic inspection shall be conducted to detect non-conformances like delamination between coverlay and copper, between coverlay and flex laminate and between copper and flex laminate in the tested flexible zone.

7.20 Flexible Endurance or Fatigue Test

This test is to determine the ductility and adhesion of copper cladding, flex laminate and coverlay. This test shall be carried out on to the test coupon-X (as per Table 9-3) in conformance to the test method 2.4.3.1 of IPC-TM-650 and para 3.10.14 of IPC-6013C. The coupon dimensions may vary as per the test fixture while the test mechanism shall be as per method 2.4.3.1 of IPC-TM-650.

a. This test shall be performed on to the flex portion of the rigid-flex PCB.

b. Test sample shall have the representative construction of the circuit type (I-beam or staggered) on flex portion.

c. In general I-beam type of construction shall be avoided, however, this may require for control impedance designs.

d. In case of rigid-flex PCB with multiple flex laminates, this test shall be performed on the individual flexible laminate.

e. This test shall cover only the static application i.e. “flex to assemble”.

f. This test shall be performed using the following parameters,

i. Minimum number of cycles for static application shall be 250 ii. The diameter of the mandrel over which the flex laminate is bend shall be between 3

mm and 10 mm. The maximum mandrel diameter shall be less than the 24 times of flex portion (including cover-lay) thickness.

iii. The flexing rate does not exceed 20 cycles per minute iv. Travel loop shall be minimum 25mm v. One cycle includes bending the flex laminate upwards 90° and downwards 90°

g. Electrical continuity shall be continually monitored during endurance testing.

h. The method for determining end of life is an electrical discontinuity during monitoring, or passing the predetermined number of flex cycles without electrical discontinuity

i. The test vehicle shall be microsectioned at the zone that was bend during the test.

j. The test sample shall be visually inspected and microsectioned in conformance to para 7.19h.

7.21 Temperature Storage

This test is to assess the capability of the PCBs for continuous operation at elevated temperature. The board shall be subjected to a temperature of +1250C, at atmospheric pressure, for an un-interrupted period of 336 hours in a temperature chamber. Direct heat from heating element to the board shall be minimized. Upon completion of the specified storage period, the boards shall be cooled without forced air circulation for a period of not less than two hours. After hot storage test the boards shall meet the requirements for the following,

a. Warp and twist ( as per Table 11-2)

b. Visual Examination (as per Table 11-4)

c. Plated through holes requirements (as per Table 11-6)

7.22 Thermal Cycling Test

7.22.1 Conventional Method

a. This test is to simulated the effect of cycling temperature variation on the PCB and to assess the via/PTH reliability.

b. This test shall be conducted on to the PCBs having the daisy chained test pattern of via/PTH.

c. The test pattern shall have a sufficient number (>50 nos.) of via/PTH of each type.

d. All via/PTH shall be connected in series to form a chain to obtain the precision resistance measurement.

e. A typical test pattern for the via/PTH reliability may be designed in conformance with the coupon-D (as per Table 9-3).

f. The design of the daisy chain pattern shall be representative of the vias/PTH capability and shall be considered following minimum features:

i. The smallest size via/PTH and largest PTH (component hole) diameter and associated pad diameters.

ii. Minimum drill pitch for the via type iii. Two coupons shall be included:

Daisy chain formation from 2nd layer to n-1 layer, with all inner layers included.

Daisy chain formation from 1st layer to nth layer only. i. All plating sequence (Applicable for sequential lamination PCBs and HDI) to be

represented by individual coupon. ii. To accommodate the all plating sequence, multiple coupons may be placed.

g. Preparation of the Test PCB/sample shall be conducted as per following:

i. Dehumidification/baking in conformance with para 7.6. ii. Six cycles of reflow simulation of the PCB in conformance to the para 7.15.

iii. Inter connection resistance measurement shall be carried out before and after each reflow simulation test for all the daisy chain nets.

iv. Changes in ICR after 6 cycles of reflow shall be in accordance with para 7.15e.

h. Thermal cycling shall be conducted with the following parameters,

i. Thermal cycling shall be performed in an air circulating chamber with ambient pressure.

ii. A temperature sensor shall be in contact with the test vehicle to monitor its temperature continuously.

iii. The temperature should be minimum -60°C and maximum +140° C. iv. The dwell time at minimum and maximum temperature shall be at least 15

minutes. v. Zone transfer time from one zone to other zone shall be within 1 Minute.

vi. The cycling programme shall start with the hot cycle first. vii. The number of cycles shall be a minimum of 200 but should be tested up to 500.

viii. ICR resistance of daisy chain shall be monitored during each cycle at peak temperature i.e. at +140°C.

ix. Measured ICR at the end of the 1st cycle shall be considered as reference resistance.

x. The change in the ICR after 500 thermal cycles for all the nets shall be ≤10% of the reference value. More than 10% shall be considered as a failure.

xi. After ambient reconditioning for at least 2 hours the following shall be performed

Visual Examination (as per Table 11-4)

Peel strength Measurement (as per Table 11-13)

PTH Microsectioning (as per Table 11-6)

7.22.2 Rapid Thermal Cycling (Optional)

In lieu of the conventional thermal cycling test, one of the following rapid thermal cycling test methods may also be used to evaluate the via/PTH reliability.

A. Highly Accelerated Thermal Shock (HATS) This test to be conducted in conformance to the para7.22.1 except the following thermal cycling test parameters,

a. This test shall be performed in conformance to IPC-9151D

b. Custom coupon designs covering the feature defined in para7.22.1f may also be used.

c. The temperature should be minimum -40°C and maximum +145°C.

d. Per cycle time shall be around 10 minutes

e. The dwell time at minimum and maximum temperature shall be around 3 to 5 minutes.

f. The number of cycles shall be minimum 500.

B. Interconnect Stress Test Method (IST)

a. This test is applicable for HDI PCB

b. This test shall be conducted in conformance with test method 2.6.26 (method A) of IPC-TM-650.

c. IST testing following shall be considered,

i. Customised IST coupons to be included in panel shall be representative of the PCB design. ii. The extreme temperature for through hole shall be 150°C.

iii. The extreme temperature for micro vias shall be 190°C. iv. Minimum no. of test cycles shall be 250 but should be tested up to 500. v. Change in resistance shall be as per point x of para7.22.1h.

7.23 Long Term Damp Heat (Humidity) Test

This test shall be conducted on to the PCB to evaluate the impact of humid conditions at elevated temperature on the PCB material, finishes and impact on the electrical properties specifically on insulation and dielectric properties. This test shall be conducted as per following

a. Humidity test conditions shall be,

i. Temperature: (40 ± 2) °C ii. Relative humidity: 93% (+2%, ‐3%)

iii. Test Duration: 21 days

b. Visual examination shall be conducted and there shall not be any evidence of corrosion.

c. Before and after Intra and interlayer insulation resistance shall be conducted in conformance to the 7.7

d. Before and after Dielectric Withstanding voltage shall be conducted in conformance to the para 7.8.

e. Peel strength in conformance to the para7.9.

f. Solderability test in conformance to the para7.11.

7.24 Temperature Humidity Bias (THB)

a. Temperature humidity test is conducted to assess the effective ness of cleaning quality in internal layers.

b. This test is applicable for PCBs having the line spacing requirements of ≤150µm.

c. This test shall be conducted in conformance with para 9.7.2 of ECSS-Q-ST-70-60C.

7.25 Conductive Anodic Filament (CAF) Resistant Test

a. CAF resistant test is applicable for HDI PCBs or PCBs having the via pitch of ≤0.8mm.

b. This test shall be conducted in conformance with para 9.7.3 of ECSS-Q-ST-70-60C.

7.26 Control Impedance

Impedance test for controlled impedance lines shall be performed using TDR in conformance with test method 2.5.5.7A of IPC-TM-650. This test may be performed on specific coupons or on PCB.

a. This test shall not be a part of qualification activity

b. Shall be mandatory for all delivered PCB batches having control impedance requirements.

c. Procurement authority shall specifically mention this as a performance requirement in the procurement document.

d. Typical acceptable tolerance, as manufactured, may be 10% of the as design.

7.27 Dielectric Constant and Dissipation Factor (Optional)

This test method is to determine the dielectric constant and dissipation factor of raw printed wiring board material at 1 MHz. Dielectric constant and dissipation factor (loss tangent) measurement test shall be conducted in conformance with test method 2.5.5.2a of IPC-TM- 650 and shall meet the requirements listed against the specific slash sheet no. of IPC-4101E.

7.28 Plated Copper Purity, Tensile Strength and Elongation

This test is to determine the quality of the plated copper used for PTH and thickness bulid-up. Following requirements shall be met,

a. The purity of the copper plating shall be no less than 99.50%, when tested as specified in IPC-TM-650, method 2.3.15

b. The tensile strength of copper shall be no less than 275.8Mpa when tested as specified in IPC-TM-650, method 2.4.18.1 and the elongation shall be no less than 18%.

This test data shall be provided by the PCB supplier/facility in every 6 months and shall maintain the records for the same. ISRO-QA reserves the right to review the results as and when required.

7.29 Analysis of Sn-Pb Coating

This test is applicable for HASL finished boards. This test shall be conducted on to the test pattern-P (as per Table 9-3) in conformance to the following:

a. The tin-lead alloy should be chemically dissolved

b. The relative quantities of tin and lead should be determined by atomic absorption spectrometry

c. The composition of tin-lead shall be Sn = 63 % ± 5 % (for dissolved copper).

7.30 Flammability

The applicability of this test shall be as follows: 1. Class A/B/C PCBs: Optional 2. Class-M PCBs: Mandatory

This test method is designed to determine the degree of flame resistance of laminate, prepreg, unclad laminate or metal-clad.

a. Flammability shall be in conformance with ESA-HRE-IPL-RQ-0002 chapter 9.2.3.

b. Flammability testing should be performed in conformance with ECSS-QST-70-21.

7.31 Outgassing (Optional)

a. The test shall be carried out in conformance with ECSS-Q-ST-70-02C.

b. The test shall be carried out on a specimen entirely devoid of copper in order to determine the volume of included gas constituents, which threaten to contaminate a space environment.

c. The outgassing shall be determined after measurement of the difference in weight of the specimen before and after the test.

d. The out gassing requirements shall meet the following,

1. TML> 1% 2. CVCM > 0.1% M

7.32 Offgassing

The applicability of this test shall be as follows: 1. Class A/B/C PCBs: Optional 2. Class-M PCBs: Mandatory

Offgassing testing should be performed in conformance with ECSS-Q-ST-70-29 and shall meet the offgassing acceptance criteria in paragraph 7.7.3 of NASASTD-6001B.”

7.33 Thermal Analysis (Optional)

a. Thermal analysis should be performed on a sample without copper.

b. Td shall be measured in conformance with test method 2.4.24.6 of IPCTM-650 using TGA.

c. T288 shall be measured in conformance with test method 2.4.24.1 of IPCTM-650 using TMA.

d. Tg should be measured in conformance with test method 2.4.25c of IPCTM-650 using DSC.

e. Tg may be measured in conformance with test method 2.4.24c of IPC-TM-650 using TMA.

f. CTE in Z-direction or Z-axis expansion shall be measured in conformance with test method 2.4.24c of IPC-TM-650 using TMA.

g. The results of thermal analysis should be verified against the slash sheet of IPC-4101E and the supplier specification of the raw materials

h. Measured results of Tg & Td shall meet the requirements of respective slash sheet of IPC-4101E.

7.34 Compatibility of Gold Plating for wire/ribbon bondability

Compatibility of wire/ribbon bonding shall be carried out for the electrolytic gold, ENIG and ENEPIG finished board. Bond quality shall be examined in conformance to ISRO-PAX-305, Issue-2.

7.35 Compatibility of Adhesive and Conformal Coating materials

The compatibility of the adhesives and conformal coating materials as specified in ISRO-PAX-300 on to the PCBs shall be conducted as per following,

a. Processed PCB/test coupon shall be visually inspected for compliance to para 12.0 and 13.0 of ISRO-PAX-300 requirements.

b. PCB/test coupons with application of adhesives and conformal coating shall be subjected to thermal vacuum cycling with following parameters,

i. Temperature limits of -55°C to +85°C ii. Dwell period at each extreme of 24 Hrs

iii. Vacuum Level of 10-5 torr or better iv. Single Cycle v. Post-test, PCB shall be visually examined for defetcs like peeling, lifting or deformation

of adhesives and CC.

8.0 QA IN MANUFACTURING AND DELIVERY

8.1 Overview

The supplier/facility shall follow the requirements for quality assurance in manufacturing and delivery (shipment) as covered herein.

8.2 Product Quality Compliance

The supplier/facility shall deliver a product in conformance to the procurement specifications and not to this document. This is with regards to cover additional requirements generated in that document, and also to comprehensively affirm compliance to delivery as per demand.

8.3 QA Requirements for PCB Batch Manufactured

For Class A PCBs, the same line shall manufacture for flight models and qualification models. For Class B PCBs, in case a different Line is used for flight models and for qualification models, if required, the impact on the following items shall be evaluated:

a. Electrical performance

b. Mechanical performance

c. Thermal performance.

For Class C PCBs, any Line may deliver the PCBs as per the procurement specifications.

8.4 Production Batch/ Lot

Production of PCBs shall conform to requirements as described in the procurement specification and detailed as per Table 5-1. PCBs manufactured to this specification shall form a part of a uniform production lot. All the boards delivered for a single circuit shall be from the same batch, while a batch can have multiple panels. A batch shall have all PCB panels press-laminated on the same day and electroplated on the same day. All the boards shall be delivered along with the traveller sheet.

8.5 Quality Records

The Supplier/facility shall retain following quality records for at least ten years.

a. Qualification test reports

b. Traveller Sheet

c. Process records

d. COC of laminates & prepreg used

e. Batch acceptance test results

f. Documentation of the final inspection of manufactured PCBs including electrical verification, impedance measurement & other applicable test/ measurement data.

g. Non-conformance shall be dealt with in conformance with ISRO-PAS-100 Issue 3

h. Detail of and corrective actions taken

8.6 Control of Raw Materials & Chemistry

a. The base material shall be in conformance with IPC-4101E for Rigid PCBs, IPC-4103A for RF PCBs, IPC-4104 for HDI & Microvia and IPC-4203 / IPC-4204 for coverlay / Flexible-laminates

b. Raw materials and semi-finished products shall be selected, inspected and tested (eg. chemical and physical tests) in conformance with the production flow chart of Facility which is a part of declared PID.

c. The Facility shall separate and prevent the use of raw materials and semi-finished products that are awaiting completion of test results.

d. The facility shall control the storage conditions and duration of materials and chemistry with limited shelf-life and verify the validity of the relevant materials for use.

e. The purity and composition of PCB conductor structure shall be as tabulated below –

Table 8-1: Specification for PCB finishes

Sr. No.

Finish Purity / Composition Remarks

1 HASL Finish 63Sn / Pb37 -

2 Copper, Electrolytic ≥ 99.5% -

3 Soft Gold, Electrolytic ≥ 99.8%, ≤ 0.2% Ag For wire-bonding

4 Hard Gold, Electrolytic Cobalt 0.3%, Ag ≤ 0.2% For epoxy-attach

5 Nickel, Electrolytic ≥ 99.95% Underlayer below Au or Pd

f. The chemistry once declared in PID shall be adhered to. In case a change is required, the same shall be conveyed to ISRO-QA, with reasons to do so, and subsequently proposed for ISRO approval.

8.7 Traceability

a. The Facility’s control system shall make it possible to determine, in respect of any lot of PCBs, the history of all raw materials (Batch code, Batch acceptance test results or Certificate of compliance) and semi-finished products listed in the production flow chart and the individual process steps mentioned herein and to verify that the items originate from one production lot.

b. In case of materials with limited shelf-life, the Facility’s control system shall provide means to verify the validity of the relevant material for use.

c. In case of materials (like prepregs) which requires specific environmental conditions for the storage shall be kept in appropriate storage conditions. Log books pertaining to the storage conditions shall be maintained by the Supplier/facility.

d. Each PCB and coupon shall have a unique marking for traceability to batch and panel number.

e. A unique7 letter alphanumeric identification should be printed on individual PCB which shall consist of the following information, e.g.,

XXXXX-XX 1st letter, Vendor/ Manufacturer’s code (Numeric, 0-9) 2nd letter, Year Code (Alphabet, A=2003 … P=2018) 3rd& 4th letters, Week Code (Numeric, 01 to 52)

5th letter, Batch code (Alphabet, A = Batch-1 and so on) 6th letter, (Aphabet, A = Panel-1) & 7th letter, PCB ID in a panel (Numeric, 1-9)

8.8 Calibration

a. The Supplier/facility shall calibrate all related electrical and mechanical manufacturing equipment to traceable reference standards

b. The Supplier/facility shall record any suspected or actual equipment failure as a non-conformance and report the same to ISRO-QA. This shall be dealt with according to ISRO-PAS-100 Issue 3.

8.9 Cleanliness in Processing

High reliability can be inbuilt in the PCB manufacturing by implementing best practices in elimination of contaminants and residual remnants during handling, processing and sub-process storing. This can be achieved by introduction of inspection, cleaning and clean-environment mechanisms at critical stages. Electrical shorts or deterioration of conductors can result due to improper cleaning or inadequately controlled environment.

8.9.1 Clean environment

It is required that contamination control be incorporated such that deposition of particulate contamination on raw material like core laminates, prepregs, oven floor etc. does not lead to poor product quality. It is preferred that Class 100000 level of clean-room environment be maintained through the facility for storage, lamination, etching and inspection area. The temperature as well as humidity of these areas be controlled and monitored regularly. The storage of epoxy-resin based material and polyimide material shall be stored separately as the former is known to generate particulate or fiber debris. The facility may formulate the environment parameters and provide these as part of PID, to achieve best product quality and shelf-life. These above identified areas shall have an environment of positive pressure, operators shall wear garments that are lint free, static generating material that attract fibers to be avoided and direct human contact by touch with PCB raw material shall be avoided to the extent possible.

8.9.2 Cleaning

Vacuum cleaning or cleaning with tacky rollers or wipes is recommended to clean prepreg sheets and core laminates prior to layer stackup

8.9.3 Inspection

Verification that the raw material as well as semi-processed material is being forwarded to activities downstream shall be incorporated by the facility. Work instructions to this effect shall be issued by the facility to all operators involved.

8.10 Operator and Inspector Training

All operators and inspectors shall be suitably trained for their task and for the understanding of the necessary quality assurance requirements

8.11 Non-conformance Control Mechanism

a. If non-conformances are observed at facility/supplier side, during the process of acceptance/qualification testing of PCBs, QA/QC shall note all the deviations and shall be submitted for approval by ISRO-QA. Data pack of the PCBs shall contain the dispositions made.

b. If non-conformances observed during incoming acceptance testing, PCB procurement authority shall note all the deviations and submit to the concerned forum for disposition.

8.12 Packaging and Delivery

a. PCBs shall be ensured to be clean, dry and cleared by outgoing acceptance prior to packaging

b. Individual PCBs and coupons shall be packed so as to preserve these against corrosion and physical damage.

c. Packaging material should provide a moisture barrier to the enclosed product, which shall be either nitrogen purged or vacuum-packaged.

d. PVC material, pink-polyethylene, bubble-wrap or foam shall be avoided as the packaging material.

e. The packaging shall be such that damage due to abrasion or pressure is avoided, preferably with use of lint-free tissue or paper.

f. The shipping container shall be marked as demanded under procurement specifications

9.0 PCB QUALIFCATION REQUIREMENTS

9.1 General

This section defines the qualification and procurement requirements for PCBs for the following PCB technology:

i. Rigid ii. Rigid-flex

iii. High Frequency PCBs iv. HDI and Sequential Lamination

9.2 Rigid PCB

Double sided or multilayer PCBs fabricated for qualification and/or procurement purposes shall meet the requirements given in this section.

9.2.1 General

a. For qualification purposes, the supplier/facility shall use materials which conform to IPC‐4101E Standards.

b. For procurement of PCBs, the selection of laminate materials shall be from the approved PID.

9.2.2 PCB Build Up

A. Base Material

The base materials i.e. Laminate and Prepreg shall be in conformance with IPC-4101E and shall be one of the following,

a. Copper cladded woven‐glass‐reinforced epoxy resin FR4; b. Copper cladded woven‐glass‐reinforced polyimide resin.

B. Conductor

a. Electrodeposited copper foil shall be used for copper clad laminates b. Copper foil shall be Type E3 (THE) copper in accordance with IPC-4562A. c. Preferably, the thickness of the copper cladding on both sides of the laminate should be

equal except on outer layers d. The external and internal layers shall use basic copper thickness of 17 μm, 35 μm or 70

μm. e. The values from the Table 9-1 should be used in the design calculations for copper foil

thickness and for as manufacturing acceptance purposes.

Table 9-1: As-designed and As-manufactured copper foil thickness

As-designed foil thickness (μm) [oz]

Minimum as-manufactured thickness for internal layers (μm)

Minimum as-manufactured thickness for external layers (μm)

9 [1/4] 6 31

12 [1/3] 9 34

17 [1/2] 11 38

35 [1] 25 53

70 [2] 56 84

C. Dielectric Thickness

a. A minimum of two sheets of prepreg shall be used for insulation between two layers. b. A minimum of two sheets of glass should be used in glass-reinforced laminates. c. The insulation distance as-designed between two layers in rigid laminate or prepreg in Z

direction shall be ≥ 100 μm. d. The insulation distance as-manufactured between two layers in rigid laminate or prepreg

in Z direction shall be ≥ 70 μm.

D. Plating

a. Internal Layers

There shall be no protective plating on the internal layers. Copper plating for the desired levels are allowed for buried via PCBs.

a. Electroless Copper Plating

The electroless copper of sufficient thickness shall only be used to aid further electro deposition for

thickness build-up.

b. Electrolytic (Electro deposited) Copper Plating

Electrodeposited copper plating shall be used for additional copper thickness build-up in the surface and in holes. Electrodeposited copper plating shall meet the following criteria,

i. The purity of the copper plating in conformance with para 7.28 ii. The tensile strength and elongation of plated copper shall be in conformance to the

requirements of para 7.28. iii. Thickness on surface and on PTH shall be in the range of 35±10 µm.

E. PCB Surface Finishes (Conductive)

The final finish/coating can be one of the finishes/coatings specified below and is dependent on assembly processes and end-use. The specifications and applicability of these finishes are listed in Table 9-2.

Table 9-2: PCB Surface finish Requirements and Applicability

Finish Type Specification Application

HASL Tin content of solder alloy shall be 63 ± 5 wt. % Thickness on surface & PTH shall be 4 to 30 µm Thickness at PTH Knee shall be ≥ 1 µm

Copper Coverage and solderability

Electrolytic Soft Gold

Minimum purity shall be 99.8 wt. % Thickness on surface & PTH shall be 2 to 4 µm

Copper coverage, limited solderability and wire-bondability

ENIG* Electroless Nickel – 3 to 6 µm Immersion Gold – 0.05 µm (min.)

Copper coverage, limited solderability

ENEPIG* Electroless Nickel – 3 to 6 µm Electroless Palladium – 0.05 to 0.30 µm Immersion Gold – ≥0.15 µm

Copper coverage, improved solderability and wire-bondability and adhesive bonding

OSP/Antitarnish Minimum coverage to solderable locations To provide limited solderability after short term storage & pre-assembly baking

* Soldering or reflow process on these finishes may require review

F. PCB Surface Finishes (Polymer)

a. Unless otherwise specified, the use of non-conductive coating material shall be restricted to permanent solder-mask coating conforming to IPC-SM-840 class-H or equivalent.

b. Permanent solder mask coating shall only be used for the purpose of coating of non-melting materials like copper, gold and/or on PCB bare material.

c. Solder-mask material shall be of Liquid photo Imagible (LPI) type, and shall meet the requirements of IPC-SM-840.

d. Unless otherwise specified, thickness of solder-mask coating shall be 17-25µm. Additional coating requirements shall be specified separately.

G. Via Protection

Materials for accomplishing via plugging or filling may be of any type i.e. conductive or non-conductive. Selection of material shall be done considering the following minimum points,

a. CTE properties shall be closely matching to PCB

b. Shall meet the outgassing requirements as per para 7.31.

9.2.3 PCB Dimension

The maximum dimensions of the PCB depend on the panel dimensions used and qualified by the Supplier/facility.

9.2.4 Thickness of PCB

A. General

a. PCB thickness shall be measured from bottom insulation to top insulation

b. The total board thickness shall be ≤ 2.4mm unless otherwise specified. The lead-length of through-hole parts shall constrain the overall board thickness.

c. The manufacturing tolerance shall be ≤10% or 0.15mm whichever is less.

B. Number of copper layers in PCB

a. Number of copper layers shall be ≤ 24.

C. Aspect Ratio

a. The aspect ratio of vias/PTH shall be ≤ 10

9.2.5 PCB Acceptance Procedure

PCBs for space projects shall meet all the requirements of section 10.0.

9.2.6 Qualification Test Vehicle Description

A. Test Vehicle Configuration

Qualification Test vehicle for Rigid PCBs comprises of the following,

a. PCBs consisting of test coupon locations shall be in conformance to Table 9-3.

b. Batch Acceptance Test coupon placement in conformance to para10.3.

c. Number of test sample requirements in conformance to Table 9-4.

B. Test Vehicle Layout Design

a. Layout for PCB and test coupon shall be generated by the PCB fabrication agency

b. PCB layout shall be prepared using test patterns designed in accordance with IPC-2221B. The type and frequency of the test patterns in the PCB shall be as per Table 9-3.

c. Test coupon design shall be in accordance to para10.3.

Table 9-3: Detail of Test Pattern Design, Frequency and its location

Test Patterns Type (As per IPC-2221B)

Frequency Location Design Reference (As per IPC-2221B)

Test Purpose

E 1 Anywhere Appendix-A Moisture and Insulation Resistance

P 2 At one side-edge of the PCB

Appendix-A Peel Strength, plating Adhesion and Finish composition

AB/R 5 4 at corners, placed diagonally opposite 1 at center

Appendix-A Plated Hole/Via thermal evaluation, feature size and spacing, registration, hole solderability, thermal stress (solder-dip) and rework simulation

G 1 At one side of the Side edge

Appendix-A Solder mask Adhesion

H 1 Anywhere Appendix-A Surface insulation resistance

Z 1 Anywhere Appendix-A Controlled Impedance

K 1 Anywhere - Physical Tests (Flammability/ Outgassing/ Off-gassing/ thermal analysis/water absorption)

D 1 At PCB center, adjacent to AB/R pattern

Appendix A Plated Hole/Via thermal stress (Thermal Cycling)

IST Coupon 1 Anywhere

Custom build (Optional)

Plated Hole/Via thermal stress (Thermal Cycling)

C. Dimensions of Qualification PCBs

The maximum dimensions of the qualification PCBs shall be decided by the fabrication facility based on their maximum processing panel size. Maximum PCB size will be limited by the surface area left after the accommodation of the mandatory test coupons.

9.2.7 Production of Qualification PCBs

PCBs shall be manufactured using the Gerber file approved by ISRO-QA. PCBs being offered for qualification shall meet all the prerequisite requirements, inclusive of outgoing acceptance by supplier/facility and incomimg acceptance at ISRO, in accordance with section 10.0.

A. Production Batch

a. PCBs manufactured for qualification, shall be a part of one production batch. All the documentation along with the traveller sheet shall accompany the submission of qualification PCBs.

b. Each panel shall consist of one qualification PCB.

B. Workmanship

a. All PCBs shall be uniform in quality and shall meet all the quality requirements specified in this document.

9.2.8 Qualification tests

A. Test Matrix

Qualification PCBs shall be tested as per Flowchart 9-1.

Flowchart 9-1: Qualification Test Matrix for Rigid and Hybrid PCBs

6 PCBs and 6 set (H & V) of Batch Test Coupons

Group 1: As Received Test Group

A. Visual Examination [All] B. Cleaning [All] C. Visual Examination [All] D. Dimensional Verification [All] E. Insulation Resistance (IR) [All] F. Dielectric Withstanding Voltage (DWV) [All] G. Peel Strength [C1] H. Coating Adhesion [C1] I. Solderability [C1] J. Initial micro-section (PCB & Plating/Coating Thickness, Registration & Basic PTH/Via Quality) [C1]

K. Warp & Twist [All P]

Reference Test Vehicle

1 PCB

1 Set of Batch Coupon

5 PCBs and 5 set of Batch Test Coupons

Group 2: Assembly Stress (AS) Group (PCB-P1 & Coupon-C2)

A. Solder Reflow [P1]

B. Solder-Dip [C2]

C. Rework Simulation [C2]

D. Microsection (after solder float,

solder-dip [P1 & C2]

E. Microsection after RW [C2]

Group 3: High Temperature Storage

Group (PCB-P2)

A. Temperature Storage

B. IR

C. DWV

D. Coating Adhesion

E. Peel Strength

F. Warp & Twist

G. Solderability

H. PTH Microsection

Group 4: Thermal Cycling Test Group

(PCB-P3)

A. Thermal Cycling

B. IR

C. DWV

D. Coating Adhesion

E. Peel Strength

F. Warp & Twist

G. Solderability

H. PTH Microsection

Group 5: Temperature Humidity Bias Test

group (PCB-P4)

A. THB Test with bias on Comb Pattern

B. Solderability

(Pattern & PTH)

C. Microsection of

Comb Pattern

Group 6: Material and Assembly Compatibility Test Group (PCB-P5)

A. Compatibility of Gold-finish for

bond-ability B. Compatibility of Adhesives

C. Compatibility with Con-formal

Coating

D. Dk /Df for RF Materials

E. Flammability/Outgassing/Thermal Analysis

F. Off-gassing (only for manned mission)

P: PCB, C: Coupon

B. Test Selection & Acceptance Requirements for Rigid PCB Qualification

a. Selection of tests for various category of qualification shall be as per the Table 9-4.

b. For delta qualification, maximum two changes can be considered simultaneously. Multiple changes shall call for full qualification.

Table 9-4: Matrix for Applicability of Testing

Qualification Requirement Type Group-1 Group-2 Group-3 Group-4 Group-5 Group-6

Initial (First) Qualification OR Re-Qualification

C C C C C C

VOQ, Verification of Qualification C C - C - -

Delta Qualification for incremental Process Change like –

a) Reduction in dielectric thickness b) Conductor coating/ finish c) Higher AR d) Higher Layer count e) Higher Basic Cu f) Higher Board thickness g) Multiple Lamination/ Plating1 h) Reduction in via pitch2 i) Finer line/gap

C C C C C C C C C

C C C C C C C C -

- - - - - - - - -

P (200 cycles)

P (200 cycles)

C C C C C C -

- C - - - - - - -

- C - - - - - - -

Project / Design Specific3 C C - C - -

Notes : 1, only applicable to Sequential build & HDI 2, only applicable to HDI 3, only applicable for one-time use, does not indicate general capability qualification C: Complete, P: Partial

C. Qualification Sample Selection & Traceability

Before start of the qualification testing, all qualification PCBs and test samples shall be identified as per the following scheme,

a. PCB lot shall be serially identified as P1, P2, P3…Pn.

b. Test Coupon shall be serially identified as C1, C2, C3…Cn.

Sample Selections (PCBs or Coupon) for an individual test group may be randomly selected.

D. Qualification Acceptance Criteria

Qualification PCBs shall meet all the requirements of para 11.3.

a. Visual Inspection requirements

b. Dimensional Requirements

c. Electrical Test Requirements

d. Mechanical Test Requirements

e. Physical Test Requirements

f. Environmental Test Requirements

9.3 Requirements of Rigid-Flex PCBs

9.3.1 Material Selection

A. General

a. For qualification purposes, the supplier/facility shall use materials as 9.3.1B to 9.3.1E.

b. For procurement of PCBs, the selection of laminate materials shall be from the approved PID.

B. Rigid Laminates & Pre-peg Materials

a. Shall meet the requirements of 9.2.2A.

C. Flex Laminates

a. Shall be copper cladded flexible polyimide laminate without adhesive between copper & laminate. It shall meet or exceed the requirements of IPC-4204A.

b. The as-designed thickness of the flex laminate (excluding copper cladding thickness) shall be 25 µm, 50 µm, 75 µm, 100 µm or 150 µm. However, 50 µm thick laminate shall be used for general requirements.

c. The tolerance for the as-manufactured thickness of the flex laminate shall be:

i. for ≤ 50 µm flex laminate: ≤ ±12.5 %, and ii. for ≥ 75 µm flex laminate: ≤ ±10 %.

D. Cover-lay

a. Shall meet or exceed the requirements of IPC-4203A.

b. Thickness of the cover layer, including polyimide cover layer thickness and acrylic adhesive, shall be 50 µm.

E. Copper cladding

a. Shall meet the requirements of IPC-4562A.

b. Thickness of the copper cladding on rigid layers shall be as per Table 9-1.

c. Thickness of the copper cladding on flex layers shall be 35 µm.

d. Copper cladding on flex-laminate shall be the type of “rolled and annealed”.

9.3.2 PCB Surface finish

a. Surface finish for rigid portion of rigid-flex board shall meet the requirement as per Table 9-2. Only qualified surface finish shall be used.

b. No PCB surface finish is allowed on flex portion of the board.

9.3.3 PCB Build-up Design

a. The build-up of the rigid-flex PCB should be symmetric and shall be designed as per Figure: 9-1.

b. Like rigid PCB, a minimum of two sheets of prepreg shall be used for insulation between two layers.

c. The insulation distance as-fabricated between two layers in “rigid laminate” or “prepreg in Z direction” should be in conformance with the values from para 9.2.2C.

d. Bonding of rigid layers to the flex layers shall be done by using no-flow prepreg.

e. Copper foil thickness of 70 µm shall not be used on flex or rigid layers bonded with no-flow prepreg unless it is defined specifically.

f. In general, no. of flex laminates shall be one. However, the number of flex laminates shall be limited to 2, which can result in 4 copper layers when double sided flex laminates are used.

g. The cover layer shall be placed in the flexible section of the PCB.

h. The cover layer shall not be placed in the rigid section of the PCB, except for the interface to the flex section.

i. The cover layer shall extend into the rigid section of the PCB by 1.0 to 2.0 mm.

j. The cover layer shall not overlap the internal pad of a via in the rigid section.

Figure: 9-1: Example of a build-up of a 6 layer symmetric rigid-flex

9.3.4 PCB Dimension

Shall be in accordance with para 9.2.6C.

9.3.5 Thickness of the PCB

A. General

a. Over all board thickness when measured at rigid ends shall be measured from conductor to conductor including surface finish thickness, as per para 9.2.4A.

Clearance pad-stack to cover layer

Layer 1

Rigid laminate

Layer 2

Prepreg low -

Cover layer flow or Uni-flow Layer 3

Flexible laminate Layer 4

Cover layer Prepreg low -

flow or uni-flow Layer 5

Rigid laminate

Layer 6

Cover layer penetration

b. Flex PCB thickness shall be measured from coverlay to coverlay.

c. The PCB shall meet the dimensional requirements of Table 11-1.

B. Number of Copper layers

a. Total No. of copper layer, including conductor in layers of flex, shall be typically ≤ 24 in the prescribed PCB thickness as per para 9.2.4.

b. Total no. of flex-layers shall be ≤ 4.

C. Aspect ratio of vias

a. Unless otherwise specified, aspect ratio of via/PTH shall be in accordance with para 9.4.4C.

b. No via/PTH are allowed in flex portion of the rigid-flex PCB.

9.3.6 Bending Radius Requirements

a. The standard flex PCB for static applications shall be consist of 50μm laminate thickness, 35μm double sided copper thickness and cover-layer. Bend radius for this shall be ≥ 12x total thickness of the flex portion.

b. Other PCB build-ups or dynamic applications shall be qualified separately.

c. Bending of the flex PCB shall be designed not to occur on the termination zone and on an additional distance of 2 mm.


a. Shall meet the requirements of section 10.0.



Qualification Test vehicle for Rigid-flex PCBs comprises of the following,

a. PCBs & test coupons in accordance with para 9.2.6A

b. Rigid-flex test coupon as designed with test pattern “X” of IPC-2221B. Size of the test coupon may be tailored with the flexural fatigue equipment.

c. No. of test vehicles (PCBs and test coupons) shall be decided based on applicable qualification type as per Table 9-4.


a. Shall be in accordance with para 9.2.6.


Shall be as per para 9.2.6C.

D. Production of Qualification PCBs

Shall be as per para 9.2.7.

9.3.1 Qualification Tests

A. Test Matrix

Qualification PCBs shall be tested as per Flowchart 9-2.

Flowchart 9-2: Qualification Test Matrix for Rigid-flex PCBs P: PCB, C: Coupon

Group 2: Assembly Stress (AS) Group

(PCB-P1 & Coupon-C2)

A. Solder Reflow [P1 B. Solder-Dip [C2] C. Rework Simulation [C2] D. Microsection (after solder

float, solder-dip [P1 & C2] E. Microsection after RW

[C2]

Group 3: High Temperature Storage Group

(PCB-P2 & Coupon-X2)

A. Temp. Storage [P2 & X2] On PCB-P2:

B. IR C. DWV D. Coating Adhesion E. Peel Strength F. Warp & Twist# G. Solderability H. PTH Microsection On Coupon-X2:

I. Folding Flexibility J. Flexible Endurance K. Microsection



A. Thermal Cycling [P3 & X3] On PCB-P3:

B. IR C. DWV D. Coating Adhesion E. Peel Strength F. Warp & Twist# G. PTH Microsection

On Coupon-X3: H. Folding Flexibility I. Flexible Endurance J. Microsection

Group 5: THB/Humidity Test Group


On PCB-P4: A. THB Test on Comb

Pattern B. Solderability C. Microsection of Comb

Pattern

On Coupon-X4: D. Humidity Test E. Folding Flexibility F. Flexible Endurance G. Microsection

Group 6: Material and Assembly Compatibility Test

Group (PCB-P5)

A. Compatibility of Gold-

finish for bond-ability B. Compatibility of

Adhesives C. Compatibility with Con-

formal Coating D. Flammability/Outgassing/

Thermal Analysis#/ E. Off-gassing (only for

manned mission)

6 PCBs, 6 set (H & V) of Batch Test (BAT) coupons and 6 nos. of Rigid-flex coupons


A. Visual Examination [All P] B. Cleaning [All P] C. Visual Examination [All P] D. Dimensional Verification [All P] E. Insulation Resistance (IR) [All P] F. Dielectric Withstanding Voltage (DWV) [All P] G. Peel Strength [C1] H. Coating Adhesion [C1] I. Solderability [C1] J. Initial micro-section (PCB & Plating/Coating Thickness, Registration & Basic PTH/Via Quality) [C1]

K. Warp & Twist# [All P] L. Folding flexibility and Bending Endurance [X1]


1 PCB


1 no. of Rigid-flex Coupon

5 PCBs, 5 set of BAT & 5 nos. of Rigid-flex coupons

B. Test Selection & Acceptance Requirements for Rigid-flex PCB Qualification

a. Selection of tests for various category of qualification shall be as per 9.2.8a.

b. Consideration of qualification category shall be in accordance with 9.2.8b.


a. Shall be in accordance with para 9.2.8C, except the following,

b. Additional coupons of rigid-flex shall be serially identified as X1, X2, X3…Xn.


Qualification PCBs shall meet all the following requirements,

a. Rigid portion requirement as per para 9.2.8D.

b. Rigid-flex transition Zone requirements as per Table 11-4.

c. Flex testing requirements in conformance with para 7.19 & para 7.20

9.3.2 Applicability of Qualification Testing

a. Applicability of testing for initial qualification, VOQ, Delta and Project specific qualification shall be in accordance with Table 9-4.

9.4 Requirements for RF (High Frequency) and Hybrid PCBs

9.4.1 Material Selection

a. For qualification purposes, the Supplier/facility shall use materials which conform to IPC‐4103 Standards. Typical Substrates includes PTFE or Hydrocarbon based resin systems including thick copper planes of around 1mm on one side.

b. For procurement of PCBs, the selection of laminate materials shall be from the approved PID for specific technology.


a. The build-up of RF PCBs shall be in conformance with requirements as per para 9.2.2 except the following,

i. Base material selection in conformance with para 9.4.1.

b. For copper cladding and copper foils the requirements of para 9.2.2B(b) shall not apply.

c. Copper type “electrodeposited - ED” or “rolled and annealed - RA” should be used for copper cladding and copper foils.

9.4.3 PCB Surface finish

a. Conductive finish for RF PCBs having wire-bonding requirements shall be of electrolytic soft gold plating only as per Table 9-2.

b. RF PCBs for patch antenna applications with isolated soldering requirements, PCBs with other alternative finishes or bare copper with appropriate antitarnish coating may be used.

9.4.4 Thickness of RF PCB

A. General

a. The thickness of RF PCB as-designed should be 9.2.4A.

b. Unless otherwise specified the finished PCB thickness tolerance shall be as per Table 11-1.


a. The number of layers for RF PCBs should be ≤ 10.


a. Unless otherwise specified, aspect ratio of via/PTH shall be ≤ 8.


PCBs for space projects shall meet all the requirements of section 10.0.



Qualification Test vehicle for RF PCBs comprises of the following,

a. PCBs & test coupons in accordance with para 9.2.6A.

b. No. of test vehicles (PCBs and coupons) shall be decided based on applicable qualification type as per Table 9-4.


a. Shall be in accordance with para 9.2.6.

b. Specific features like slots (for chip device), ground-source-ground (GSG) input and output feature for MMICs etc. may be included as applicable.


a. Shall be as per para 9.2.6C.


a. Shall be as per para 9.2.7.


A. Test Matrix

Qualification PCBs shall be tested as per the Flowchart 9-3.

Flowchart 9-3: Qualification Test Matrix for RF PCBs


Group (PCB-P5)

A. Compatibility of Gold-finish for bond-ability

B. Compatibility of Adhesives C. Dk/Df measurements D. Flammability/Outgassing/

Thermal Analysis E. Off-gassing (for manned

mission)

Group 5: Humidity Test Group (PCB-P4)

A. Humidity Test B. Solderability

(Pattern & PTH) C. Microsection PTH

(after solderability)


(PCB-P3)

A. Thermal Cycling B. IR C. DWV D. Coating Adhesion E. Peel Strength F. PTH Microsection


Group (PCB-P2)


B. IR C. DWV D. Coating Adhesion E. Peel Strength F. Solderability G. PTH Microsection


(Coupon-C2) A. Solder Float [C2] B. Microsection

(after solder float)



A. Visual Examination [All P]

B. Cleaning [All P]

C. Visual Examination [All P]

D. Dimensional Verification [All P]

E. Insulation Resistance (IR) [All P]

F. Dielectric Withstanding Voltage (DWV) [All P]

G. Peel Strength [C1]

H. Coating Adhesion [C1]

I. Solderability [C1]

J. Initial micro-section (PCB & Plating/Coating Thickness, Registration & Basic PTH/Via Quality) [C1]


1 PCB



P: PCB, C: Coupon


a. Selection of tests for various category of qualification shall be as per the para 9.2.8a.

b. Consideration of qualification category shall be in accordance with para 9.2.8b.


a. Shall be in accordance with para 9.2.8C.


a. Qualification PCBs shall meet the all the requirements of para 9.2.8D.

b. Additionally, RF boards shall meet the plating overhang criteria as per Table 11-15.

9.4.8 Hybrid PCBs

These PCBs shall consist of a mix of RF and FR4 laminate materials. By convention, the top and Bottom laminate shall be RF material and the intervening layers shall consist of FR4 material. The manufacture and qualification of these PCBs shall be as per Rigid MLB requirements in accordance with para 9.2.6.

9.4.9 Applicability of Testing


9.5 Requirements for HDI and Sequential Build-up PCBs

9.5.1 General

a. For qualification purposes of HDI PCBs, the Supplier/facility shall use base materials conforming to IPC/JPCA‐4104.

b. For procurement of PCBs, the selection of laminate materials shall be as per the approved PID for specific technology.


A. Rigid Laminates & Pre-peg Materials

a. Shall meet the requirements of para

B. HDI Base Materials

a. Shall meet the following requirements

i. Dielectric materials as per section 3.7.1 of IPC-4104 ii. Materials for conductive path as per section 3.7.2 of IPC-4104

iii. Materials with dielectric and conductive functionality as per section 3.7.3 of IPC-4104.

C. Conductor

a. Shall be in accordance with para 9.2.2B.

D. Plating

a. Shall be in accordance with para 9.2.2D.

b. Via filling material

E. Surface Finish

a. Shall be in accordance with para 9.2.2E.

9.5.3 Dielectric Thickness

b. For HDI layers following shall apply,

i. Between two HDI layers or a HDI and non HDI layers, a single ply of laser drillable pre-preg may be used.

a. For non-HDI layers, requirements of para 9.2.2C shall apply.

9.5.4 HDI Types

HDI construction type definition/classification shall be in accordance with IPC-6018. The applicable types are as per following Table 9-5.

DJBhatt

Highlight

DJBhatt

Highlight

DJBhatt

Highlight

Table 9-5: HDI Type/classification

S. No. Type Figure

1 Type I 1-[C]-0 or 1-[C]-1 Without buried vias

2 Type II 1-[C]-0 or 1-[C]-1 With buried vias

3 Type III

≥2-[C]-≥0 Staggered microvia is recommended over stacked microvia. Stacked microvia over buried via may result in reduced reliability due to z-axis stress during thermal excursion.

Staggered construction

Stacked construction

9.5.5 Thickness of PCB

A. General

a. The total thickness of HDI PCBs shall meet the requirements of para 9.2.4A.


a. The number of HDI layers for shall be ≤ 6.

b. Total no. of layer count shall meet the requirements of para 9.2.4B


a. Aspect ratio of a laser drilled HDI via shall be ≤ 1.

b. Aspect ratio for non-HDI PCB shall meet the requirement of para 9.2.4C.


a. PCBs for space projects shall meet all the requirements of section 10.0.



Qualification Test vehicle for Rigid-flex PCBs comprises of the following:

a. PCBs & test coupons in accordance with para 9.2.6A.

b. No. of test vehicle (PCBs & test coupons) shall be decided based on applicable qualification type as per Table 9-4.


a. Shall be in accordance with with para 9.2.6.


a. Shall be as per para 9.2.6C


a. Shall be as per para 9.2.7.


A. Test Matrix

a. Qualification PCBs shall be tested as per Flowchart 9-4.

Flowchart 9-4: Qualification Test Matrix for Sequential Build-up and HDI PCBs P: PCB, C: Coupon



A. Visual Examination [All P] B. Cleaning [All P] C. Visual Examination [All P] D. Dimensional Verification [All P] E. Insulation Resistance (IR) [All P] F. Dielectric Withstanding Voltage (DWV) [All P] G. Peel Strength [C1] H. Coating Adhesion [C1] I. Solderability [C1] J. Initial micro-section (PCB & Plating/Coating Thickness, Registration & Basic PTH/Via Quality) [C1]

K. Warp & Twist [All P]


1 PCB




(PCB-P1 & Coupon-C2)

A. Solder Reflow[P1] B. Solder-Dip [C2] C. Rework Simulation [C2] D. Microsection (after solder

float, solder-dip [P1 & C2] E. Microsection after RW [C2]


Group (PCB-P2)


B. IR C. DWV D. Coating Adhesion E. Peel Strength F. Warp & Twist G. Solderability H. PTH Microsection


(PCB-P3)

A. Thermal Cycling B. IR C. DWV D. Coating Adhesion E. Peel Strength F. Warp & Twist G. PTH Microsection

Group 5: Temperature Humidity Bias Test &

CAF Test group (PCB-P4)

A. THB Test with bias

on Comb Pattern B. CAF Test on CAF

pattern

C. Microsection of Comb & CAF Pattern


Group (PCB-P5)

A. Compatibility of Gold-finish for bond-ability

B. Compatibility of Adhesives C. Compatibility of Con-

formal Coating D. Flammability/Outgassing/T

hermal Analysis#/ E. Off-gassing (for manned

mission)


a. Selection of tests for various category of qualification shall be as per 9.2.8a.

b. Consideration of qualification category shall be in accordance with para 9.2.8b.


a. Shall be in accordance with para 9.2.8C.


a. Shall meet the requirements of section 0.

9.5.9 Applicability of Testing


10.0 PCB BATCH ACCEPTANCE

10.1 General

This chapter describes the procedures and guidelines for acceptance of PCBs for space use.

10.2 BAT/QCI Procedure

BAT (Batch acceptance testing) or QCI (Quality Conformance Inspection) shall cover the following,

a. QCI shall be conducted for each and every batch/lot of PCBs fabricated by qualified facilities for space use.

b. Batch consisting of multiple panels, PCBs and coupons of all panels shall be subjected for QCT.

c. The batch acceptance procedure is divided into two phases,

i. First, to be carried out at supplier/facility end, as part of supplier/facility outgoing acceptance as per para 10.2.1.

ii. Secondly, to be carried out at PCB procurement authority, as part of incoming acceptance as per para 10.2.4.

d. The method for BAT are, in principle, same for both the agencies.

e. Batch shall be considered acceptable, only after acceptance by the PCB procurement authority. In case of conflict between the facility and PCB procurement authority, facility shall be required to provide the closeout.

10.2.1 Facility Outgoing QCI Test Flow

a. The supplier/facility shall conduct the outgoing acceptance of each processed panel in accordance with Flowchart 10-1.

b. In case, batch is formed of multiple panels, outgoing acceptance shall be conducted for all panels.

c. To support the test requirements, the vendor shall have in-house test facility to ensure QCI of fabricated PCBs.

Flowchart 10-1: Panel wise BAT Acceptance Procedure

10.2.2 BAT Tests

The QCI test description and its applicability shall be in accordance with Table 10-1.

Table 10-1: BAT Tests & Applicability

Sr. No. Tests Test Samples

1. BBT (Pre and post finish) All PCBs and Coupons

2. Control Impedance PCB/Coupon

Pre-finish BBT for Week-Year coded panel

- Post Finish Visual Inspection - XRF Measurement (for

ENIG/ENEPIG)

Post Finish BBT

Control impedance

Mechanical Inspection

Visual Inspection

Acceptance Testing of Coupon

Review & Compilation of reports

Reject NC Review & Management by facility QA

Note-1: PCB failing the post HASL BBT, shall call for panel to be quarantined and facility NC review to be shared with ISRO-QA. Note-2: Any trend/event causing lower yield of processed batch having multiple panels shall be shared with ISRO-QA. Note-3: BBT is limited to supplier/facility.

Fail

Fail

Fail

Fail

Pass

Pass

Pass

Pass

Pass

Pass

Pass

Fail

Report

Report

Report

Report

Report

Report

Sr. No. Tests Test Samples

3. Mechanical Inspection All PCBs

4. Visual Inspection All PCBs and Coupons

5. Peel Strength Coupon

6. Rework simulation Coupon

7. Solder dip ( 3 dip cycles) Coupon

8. Solderability Coupon

9. Insulation resistance intra-layer Coupon

10. Insulation resistance inter-layer Coupon

11. Dielectric withstand voltage intra-layer Coupon

12. Dielectric withstand voltage inter-layer Coupon

13. Microsectioning of initial sample Coupon

14. Microsectioning of rework simulated test sample Coupon

15. Microsectioning of solder dip tested samples Coupon

16. Bending Flexibility Coupon

17. Flexible Endurance Coupon

10.2.3 BAT Deliverables

The facility shall submit PCBs and coupons to its outgoing (pre-dispatch) accepatnce. The facility shall deliver the PCBs from the outgoing accepted lot defect free PCBs along with coupons, lot-traveller, microsectioning report and batch-clearance report along with requisite material conformance certificate, as per following data packs: The vendor, at the time of shipping the PCB batches, must provide all the test reports along with following data pack:

a. IPC Compliance certificate of the laminate and prepreg material used

b. Traveller card of the PCB panel

c. PCB layer stack-up

d. Bare board test label on the PCB

e. Mechanical inspection report (As per format in Annexure 5)

f. Visual Inspection Report

g. Microsection report (As per format in Annexure 6 & Annexure 7)

h. Coupon testing report (As per format in Annexure 8)

i. Final inspection report (As per format in Annexure 9)

j. Non-conformance and close out report, if any (As per format in Annexure 10)

10.2.4 Incoming Acceptance by PCB procurement authority

After receiving the PCB batches and data pack from supplier/facility, PCB procurement authority shall conduct the BAT as a part of incoming acceptance in accordance with Flowchart 10-1.

10.3 BAT Test Coupons

The supplier/facility shall produce the two sets of batch acceptance test coupons with each processed panel. These coupons shall be representative of actual boards being processed in the panel in terms of type of material, chemistry and process used, design features (PTHs, vias and line definitions). Batch test coupons shall be designed in conformance with Table 10-2 and the placement of these coupons on to the processing panel shall be in accordance with para 10.4. Minimum number of required batch test coupons in each processed panel shall be as follows,

- Two sets of Horizantal Coupons (HC) i.e. HC-1 and HC-2 - Two sets of Vertical Coupons (VC) i.e. VC-1 & VC-2

Horizantal (H) and vertical (V) test coupons shall have the identical designs. One set of test coupons (H & V) shall be tested by supplier/facility for their in-house quality control purposes as a part of outgoing acceptance and one set to be supplied to the PCB procurement authority. The supplier/facility shall provide unique labelling for each coupon of a processed panel for proper identification, so that every coupon shall be identifiable by its own unique number.

10.3.1 Coupon Designations

The batch test coupon are sub divided into diffenert zones identified as Z1 to Z11 Table 10-2, where each zone has specific feature to test a particular aspect of a batch and technology. All panels shall have general test coupons Z1 to Z9. For technology specific designs, spacial coupons (Z10 to Z16) shall be added in the panel as applicable.

10.3.2 Coupon Grouping in Panel

All the general and HDI specific (if required) coupons zones shall be grouped as Horizontal and Vertical coupons as shown in Figure: 10-1. The other technology specific coupon zones (Controlled Impedance, Rigid-Flex) are to be placed anywhere in the panel.

Z1 Z2 Z3 Z4 Z5 Z8 Z9 Z10 Z11

Figure: 10-1: Coupon grouping for Horizontal and Vertical Placement in Panel

Table 10-2: Test Coupon Description

Sr. No.

PCB Type wise Applicability of coupons

Coupon ID

Test Pattern Name

Parameters to be Assessed

Design Reference

1.

General

Z1 Initial-Microsectioning

- PCB construction

- Drilling & alignment

- Via/PTH size, plating

Refer Table 9-3

Z7

Z7

Z6

Z6

Sr. No.

PCB Type wise Applicability of coupons

Coupon ID

Test Pattern Name

Parameters to be Assessed

Design Reference

thickness & intigrity

- Plating/coaitng thickness on surface

- Solder-mask coverage and thickness

2. Z2 Solder Dip PCB construction & PTH integrity

3. Z3 Rework Simulation

PTH & land pad integrity

4. Z4 Solderability Wettability of conducor finish

5. Z5 IR & DWV Isolation and dielectirc property

6. Z6 Peel Strength & Coating Adhesion

- Conductor adhesion

- Plating/coaitng adhesion

7. Z7 Line width / spacing (by microsectioing)

Min. line/spacing capability

8. HDI

Z8 Buried - PCB construction

- Via plating, plugging & integrity

9. Z9 First layer of via

10. Z10 2nd layer of via

11. Z11 All together

12. Impedance Coupons

Z12 Impedance Coupons (As applicable)

Control impedance performance

Refer Table 9-3

13. Rigid-flex Z13 Bending Flexibility

PCB construction integrity and bending performance

Refer para 9.3.8A(b)

Flexural Endurance

PCB construction integrity and copper flexibility

14. Z14 Flex Impedance Coupons (As applicable)

Control impedance performance

10.4 Placement of Batch Test Coupons

Two sets of batch test coupon shall be placed in horizontal and vertical directions at the edges of each panel. Coupons other than Horizontal and Vertical (Control Impedance, flexi-Rigid etc) must be places to capture the worst case process tolerance/limitations. In addition of ISRO batch coupons, the vendor may add his own coupons for tests at his end.

Figure: 10-2: BAT Coupon Placement Diagram

10.5 Batch Workmanship

As per Acceptance criteria in section 0.

10.6 Non-Conformance (NC) Management

10.6.1 NC Control at Vendors’ End

If non-conformances are observed at manufacturer side, during the process of outgoing acceptance of PCBs, Vendor’s QA/QC shall note all the deviations and review quality inspection internally. Root cause shall be identified and Data pack of the PCBs shall contain the dispositions made. In case root cause is not identified, PCB procurement authority shall be consulted.

10.6.2 NC Management by ISRO-QA

If non-conformances are observed at ISRO side, during the process of incoming inspection of PCBs, QA/QC (qualification team) of PCB procurement authority shall record the deviations, review corrective/ preventive actions by facility and subsequently formulate appropriate recommendation. The recommendation may cover corrective action, review of facility quality system, facility audit, requalification or termination of qualification of the facility, any of these as found fit.

11.0 ACCEPTANCE CRITERIA

11.1 Overview

Visual Inspection is carried out at various stages and various phases, viz. outgoing acceptance at the Facility, incoming inspection by PCB procurement authority, during evaluation, qualification or maintenance of qualification or as a part of Re-lifing. The PCB is required to conform to required quality for space use and hence, the guideline for visual inspection and acceptance criteria are covered in this clause.

11.2 Verification of Marking

a. Each board shall be inspected with the naked eye for correct marking b. Each board shall have a marking as agreed upon with ISRO-QA to cover the vendor/facility

identification marker, followed by year of manufacturer, week of the year, day of the week and the panel ID.

c. The PCB shall also carry the Circuit ID as desired by the procurement agency and conveyed along with the gerber data.

d. The marking shall be legible and resistant to test stresses. The non-conformance criteria shall be as follows: i) Identification impossible ii) Marking not conforming to the specification

11.3 Categories of PCB Inspection

a. Dimension Measurements b. External visual c. Electrical d. Physical e. Mechanical f. Internal Visual & Dimensional (of microsection) g. Post test monitoring

11.3.1 Dimensional Measurements

Each PCB shall be subjected to dimensional measurements using applicable standard tools. A. External Dimensions

Table 11-1: PCB External Dimensional Requirements

Sr. No.

Feature Specification/Tolerance

Special Note; Figure

1.

PCB Thickness

Rigid ±10% or 0.15mm, whichever less

PCB thickness shall be measured from top conductor finish to bottom conductor finish

Flex ±20% PCB thickness shall be measured including top & bottom coverlay

2. PCB overall dimensions

Rigid ≤ ±0.2mm, ---

Flex ±0.4mm

3. Stacking Hole Diameter +0.1/-0.0mm ---

4. Stacking Hole centering +0.1mm ---

B. Warp or Bow

Table 11-2: Warp Requirements

Sr. No.

Feature Specification Special Note; Figure

1.

Warp or bow % Not Applicable for Non-rigid RF board

≤ 1% (In general) ≤ 0.75% for CCGA*

Note * for CCGA the board thickness and size should aid to minimize warp and twist, by using appropriate copper-balancing and symmetric stack-up.

2.

Twist % Not Applicable for Non-rigid RF board

≤ 1% (In general) ≤0.75% for CCGA*

C. Specific Dimensions

Table 11-3: Specific Dimensional Requirements

Feature Specification/Tolerance Special Note; Figure

1. Line (Conductor trace) Width Tolerance allowed

unless otherwise qualified 0.15mm, ±10%

---

2. Gap (Spacing) Line to line Line to Free Hole Line to Card Edge Tolerance allowed

Unless otherwise qualified… 0.15mm 0.5mm 1.0mm ±10%

3. Annular Ring,

Unless Otherwise qualified,


Internal External

0.05mm (minimum) 0.125mm (minimum)

4. Holes/ Vias Diameter Tolerance in Dia.

Unless Otherwise qualified, 0.2mm minimum ±0.05mm

5. Hole Pitch ± 0.1 mm

6. PTH Pad Diameter ± 0.1 mm

7. Any circuit trace/feature

Strictly conforming to procurement document

8.

Rigid-flex Coverlay beyond copper-edge

At least 1mm margin between flex edge and copper edge, no copper visible at edge

Reject

11.3.2 External Visual

Each PCB shall be inspected under magnification of 10x to 40x with adjustable brightness and lighting conditions to verify that construction and workmanship meet the requirements A. Laminate Defects

Table 11-4: Subsurface Visual Aspects

Sr. No.


1. Scratches None (exposing glass

fibre)

---

2. Crazing and Haloing None (visible with naked

eye)

3. Weave texture None (visible with naked

eye)

4.

Non-homogeneity, particulate inclusions, stains, discoloration, etc

None (visible with naked eye, raising doubt on material and/or process)

5. Inclusion of foreign material,

None

6. Delamination None

7.

Measling Across the board Across the gap > 50% of a gap

None None None

No Margin

Copper Visible

Sr. No.


8. Fungus growth None

9. Contamination not removable by prescribed cleaning

None

10. Rigid-Flex Edge finish

No evidence of burrs, nicks, cuts and delamination

Burrs at edge

11. Rigid-Flex Strain-relief fillet zone

1 – 2.5 mm at the transition-zone from rigid-edge

12. Rigid-Flex Epoxy-staking for stain relief

Shall have no inclusions, bubbles, etc.

Bubbles

13. Rigid-Flex Transition Zone

Stress-free, wrinkle-free

Reject

Wrinkles

Sr. No.


14.

RF Laminate, Gold Finish Blisters

None

15.

RF Laminate, Gold Finish Nodules in PTH

None

Top View Microsection View

B. Conductor Pattern / Gap Defects

Table 11-5: Conductor Pattern Requirements

Sr. No.


1. Pattern or Pads not conforming to spec.

None

--- 2.

Traces or pads partially or completely missing due to tooling, processing, etc.

None

3. Pattern Short or gap reduced by >10%

None

4. Lifting/ delamination of

None

Sr. No.


conductor pattern

5. Scratch in finish exposing underlayer

None

6. Oxidation/ corrosion of exposed copper

None

7. Dewetting in Solder finish

None

8.

Line/ gap combination a > 20% of x b > x Opposite peaks: if z < 80% of y Isolated peaks or valleys: h > 20% of x and z < requirement Conducting island: a + h > 20% of y b > y

None None None None None None

C. Plated Through Hole Defects

Table 11-6: PTH Requirements

Sr. No.


1. Non-compliant holes

None

--- 2.

Partially or completely missing barrel wall

None

3.

Through holes ≥0.5mm partially or completely filled during HASL

None

4.

Rigid-Flex Clearance of PTH to Rigid-section edge at Rigid-flex transition zone

2.3mm, PTH center shall be (2.3mm + PTH radius) distance away from the rigid section edge at transition zone

D. Solder mask related

Table 11-7: Solder mask Requirements

Sr. No.


1. Solder-mask clearance from land

>50µm ---

2. Solder-mask mis-registration

No mask over-run on solderable pad/land

3. Inadequate solder-mask application

None

11.3.3 Electrical

Each PCB shall be tested using applicable standard high-resistance/insulation measuring equipment, high-voltage source, digital multimeter, etc. to assess required insulation, withstanding-voltage thresholds, continuity, etc.

A. Intralayer Insulation Resistance

Table 11-8: Insulation Resistance Intralayer

Sr. No.


1. Before environmental tests

R < 1x10E10 Ω

---

2. After environmental tests

R < 1x10E9 Ω

B. Interlayer Insulation Resistance

Table 11-9: Insulation Resistance Interlayer

Sr. No.

Feature Specification/Tolerance Method

1. Before environmental tests

R <1x10E11 Ω

---

2. After environmental tests

R <1x10E10 Ω

C. Dielectric Withstanding Voltage (DWV) Intralayer and Interlayer

Table 11-10: DWV Requirements

Sr. No.


1. DWV No Evidence of breakdown, flashover or sparking…

2. Interlayer

3. Intralayer

11.3.4 Physical

A. Water Absorption Test (optional)

Table 11-11: Water Absorption Requirements

Sr. No.


1.

Water Absorption Weight increase post water-immersion not to exceed by 0.2%

B. Outgassing Test

Table 11-12: Outgassing Requirements

Sr. No.


1.

Outgassing (release of gases from the MLB under vacuum condition)

TML > 1% and CVCM > 0.1%

Note: The test shall be carried out in conformance with ECSS-Q-ST-70-02C.

11.3.5 Mechanical

A. Peel Strength

Table 11-13: Peel Strength Requirements

Sr. No.


1.

Peel strength 1. On FR4: ≥ 12 N/cm 2. On polyimide: ≥ 12 N/cm 3. On PTFE reinforced/ ceramic filled or nonfilled: ≥ 8 N/cm 4. Cross- linked hydrocarbon : ≥ 8 N/cm 5. On flex laminate: ≥ 10 N/cm

B. Solderability Requirements

Table 11-14: Solderability Requirements

Sr. No.


1. Solder wetting of PCB PTH

Poor wettability - None As shown below

Pad lift - None

Good wettability Poor wettability

11.3.6 Internal Visual & Micro sectioning

Required tools to perform microsectioning and an inverted microscope with a magnification from 50x to 1000x shall be used for internal visuals and measurements…

A. General

Table 11-15: Internal Visual Aspects

Sr. No.


1.

Conductor thickness

w = 150μm +10%/ -0μm te = 130 μm, unless otherwise specified ti = 50 μm, unless otherwise specified td = 200μm for Rigid & 100μm for HDI, ±50μm h = (9/17/35/70μm, Basic) + 35μm, Deposited Copper… ±10 μm Annular Ring for non-soldered PTH & buried via ≥ 50microns

w - Width of conductor te - minimum annular ring on external layer ti - minimum annular ring on internal layer td - finished diameter of plated through hole h - Total conductor thickness

2.

Basic copper – Copper coming along with the core laminate, or the copper-foil bonded with the laminate by facility, typically – 9/17/35/70μm, if not met, Major Defect with following specs- Basic 9μm± 4μm Basic 17μm± 4μm Basic 35 μm± 5μm Basic 70μm± 5μm

Average of 3 readings, at ¼, ½, ¾ PTH barrel height

3.

Deposited copper – copper thickness built up by facility to metalize holes/ vias, Thickness - 35μm± 10μm,

4.

HASL finish – 5μm minimum at top, bottom and in PTH, 1μm minimum at PTH knee,

Sr. No.


5.

ENIG finish – 0.08 to 0.13μm Gold, 3 to 6μm Nickel underlayer

6.

ENEPIG Finish – 0.05μm Top Gold, 0.1μm Palladium underlayer, 3 to 5μm over deposited copper

7.

Pad Lift post rework-simulation

None

8.

Rigid-Flex Copper-trace construction for double-sided flex

I-beam construction “Not recommended” by IPC, as long-term reliability limited Interlace construction recommended by IPC, but will not support Impedance-line applications

I-beam Interlace

9.

Rigid-Flex Symmetrical Stack build

Flex dielectric shall be centrally placed in the rigid-flex MLB stack

Accept

10.

Rigid-Flex Coverlay overlap in Rigid section

At least 1mm

Accept

11. RF Laminate, Gold finish Thickness

2 to 4 µm

Sr. No.


12.

RF Laminate, Gold Finish Discontinuity in PTH/via

None

13.

RF Laminate, Gold Finish Overhang

≤ top layer thickness

14.

RF Laminate, Gold Finish Separation of laminate from Copper backup

None

Sr. No.


15.

HDI & Sequential Build Dielectric Crack, internal

≥ 50µm, None

B. Etch Profile on Pattern and in PTH

Table 11-16: Etch Profile Requirements

Sr. No.


1. Undercut, U U≤ T,

2.

Overhang, O O ≤ t,

C. Plated-Through Hole Aspects

Table 11-17: PTH Aspects


1.

Resin Smear, Resin Recession, Voids

No Resin smear at internal layer, Resin recession, > 50% of dielectic layer or 40% PTH height, Void > 50% of isolation/ conductor-gap or 80μm

Laminate Void

Basic Copper

Deposited

Top Finish

Undercut, U

Overhang,

T

t


Resin Recession Resin Smear

2.

Barrel Separation at inner layers and dielectric

None

3.

Barrel Discontinuity

None

4.

Barrel pull-out

None (barrel separation indicates moisture absorption)


5. Etchback

Negative : 5µm Positive : 13µm

Negative Etchback Positive Etchback

6.

Nail-Heading

1.5x copper thickness in layer i.e, b ≤ 1.5a

7.

Discontinuity in internal layer Example of zero annular ring due to mis-registration

None

a b


8. Irregular Barrel

< 80µm perpendicular to PTH Barrel

9. Barrel Crack,

post solder-dip None

10. Cap-plating

No separation in cap and epoxy filling for ≥3µm

11.

HDI & Sequential Build Microvia Aspect Ratio

≤ 1

Z/X≤ 1

Y


Contact Dia. With Capture pad Annular ring at capture/ target pad

≥100µm Y ≥ 10µm

12.

Void in copper-filled microvia Dimple Bump

Shall have minimum 25µm copper-fill at hole-wall, capture-pad and top-surface ≤ 50µm in height ≤ 15µm in height

13.

HDI & Sequential Build Annular Ring Internal

≥50µm


External ≥100µm

14.

HDI & Sequential Build Resin in blind/ buried hole/via

none allowed across the hole diameter, OR none that reduces filling by more than 15%

Accept

Reject

15.

HDI & Sequential Build Dielectric Thickness

≥70µm

11.3.7 Post Test Monitoring

Post environmental test monitoring of external and internal PCB features shall be performed using above methods from 9.3.1 to 9.3.5

Table 11-18: Post Thermal Stress and Environmental Test Requirements

Sr. No.


1.

Post Hot Storage

Warp and Twist Pattern/laminate discoloration Oxidation/ corrosion

---

Post Thermal Stress Solder Reflow

Warp and Twist, Measling, Broken finish or conductor,

---

Sr. No.


2.

Solder Dip Rework Simulation

Peel strength, Continuity & ICR PTH Integrity by Microsectioining, Blistering/ Charring, Discoloration, Measling, Lifted Conductor, PTH Integrity by Microsectioining,

3.

Post Cycling Laminate Discoloration, Peel Strength, Continuity & ICR, Intralayer and Interlayer IR DWV PTH Integrity by Microsectioining

---

4.

Post Humidity Laminate Discoloration Peel Strength, Intralayer and Interlayer IR &DWV, Evidence of Corrosion, PTH Integrity by Microsectioining

---

5.

Post Assembly Processes

Compatibility to assembly and wiring processes under ISRO-PAX-300

---

12.0 HANDLING, STORAGE AND RE-LIFING

12.1 Overview

The PCB finish is the most sensitive as well as critical aspect, which is not only significant from the assembly and wiring point of view but also difficult to preserve from atmospheric affect. The following paragraphs provide details of the sensitivity and safeguarding necessary to preserve PCB life.

12.2 Handling Precautions

To the extent possible the finished PCB shall not be handled with bare hands and under uncontrolled environment. The PCB will have either an HASL finish or Gold-finish which can be tarnished by atmospheric moisture or contaminants. The following precautions shall be taken during handling and packing PCBs.

a. PCBs shall be handled such that these are not subjected to any mechanical shock PCBs shall not be subjected to abrasion against any hard surface.

b. Handling after the cleaning operation shall be done with protective gloves. c. PCBs shall not come in contact with any paper containing Sulphur traces. d. Stapler pins shall not be used for sealing the polythene bags. e. In the event of removal of the PCB from its protective packing, for the purpose of inspection,

refiling or for any other reason temporarily, it shall be opened in a controlled environment specified in ISRO-PAX-300/305. It shall be handled with all the precautions and safeguards elaborated above.

12.3 Packing and storage

There is a slow decline in wettability in Tin / Lead finishes. This degradation is independent of packaging material. The root cause of Solderability loss is growth and oxidation of Cu6Sn5 and Cu3Sn intermetallic phases. When these intermetallic compounds (IMCs) reach the surface and oxidize, Solderability is lost. Thinnest areas (PTH knee for HASL finish) lose solderability faster (6 months to a year typical). Remaining surface typically remain solderable for 1-2 years depending on SnPb thickness, in case the PCB is subjected to uncontrolled temperatures, humidity and contamination. Typically, class 100k cleanroom with temperature of 23±2 deg C and humidity of 55±5% RH is recommended for handling, however, PCB storage shall be preferably carried out in dry, contamination free and sealed packing. Further details are as follows –

a. PCBs shall be stored in moisture free environment and shall be packed along with a sachet of silica gel, which shall retain blue color throughout storage period.

b. Vacuum sealing or nitrogen purged packing is preferred for PCBs for storage and transportation. c. Packaging materials bearing direct influence the longevity and preservation of printed boards

with regard to moisture absorption and meeting the requirements ofIPC-J-STD-033, which specifies a WVTR of < 0.002 g /100 Sq. inch are preferred. A commonly available Moisture Barrier Bag (MBB) construction that incorporates an outer layer of static dissipative nylon, aluminum foil middle layer, and an inner layer of polyethylene. This structure provides very good moisture barrier characteristics with typical WVTR values of < 0.0005gm/100 sq. inch

d. Prior to packaging, the printed boards should be clean. Moisture Barrier Bag should be heat sealed to keep out moisture. Full air evacuation is not needed or recommended; light air evacuation will reduce the packaging bulk and facilitate carton packing. Excessive evacuation may impede desiccant performance and lead to MBB punctures.

e. Empty space in the container should be filled with appropriate packing material so that the product cannot shift within the packaging and will be protected during shipment. When

necessary, especially for large printed boards, corner protectors should be used. Materials used should be free of contaminants.

f. Use of anti-static or static dissipative materials provided for transportation are to be opened within an ESD Protected Area (EPA)for assembly.

g. Before opening, dry packed packages should be inspected to verify that there are no tears punctures or openings of any kind that expose the contents. If openings are found, the dry environment of the bag has been compromised, then the printed boards should be visually inspected for any changes to the final finish that may indicate that Solderability has been degraded.

h. During physical inspection, intact bags may be opened for inspection by cutting at the top of the bag near the seal. Time of exposure to ambient conditions should be controlled to minimize moisture uptake.

12.4 Shelf-life & Re-lifing of Stored PCBs

All PCBs after successful inspection and approval shall be stored in dry Nitrogen storage cabinet or controlled environment desiccators. In case of non-availability of dry Nitrogen cabinets, MBB bags purged with dry Nitrogen may be used. The normal Shelf-life of any PCB is expected to be 6 months, beyond which its usability shall be assessed. Long duration stored boards shall undergo rescreening/refiling under specific categorization as follows

Table 12-1: PCB Shelf Life and Re-lifing Requirements

Note - The batch of PCB left with one card balance shall not be taken for re-screening. Moreover, these shall not be allowed for space use

PCB Storage Duration Category-1 PCBs w/o dry N2 purged bags

Category-2 PCBs Stored with dry N2 purged bags

6 months ≤ t ≤ 1 yr. Visual Inspection of Actual Cards Use as s

1 yr. < t < 2yrs. •Actual Card Inspection

•Solderability on One Card Visual Inspection

˃ 2 yrs. Not for Space Use Visual inspection on actual card.

Solderability test on one card.

˃ 5 yrs. Not for Space Use PCB procurement authority may

assess usability

13.0 OTHER TECHNOLOGIES NOT COVERED

There are several other PCB technologies that are commercially available for industrial use and for automotive appliations. However, these have not found use in ISRO applications and are hence, NOT COVERED in this document at present. These technologies if requried at such a point of time shall be adequately assessed and qualified by ISRO-QA prior to being cleared for space use. A brief summary of some such technologies is given below.

13.1 PCBs with Embedded Passives

Embedded Passives, like resistors and capacitors, in the circuit board has following advantages – a. System cost and mass savings (passives eliminated), b. Assembly cost savings (no soldering), c. Board surface area savings (smaller boards), d. Performance benefits (lower parasitic), e. Reliability benefits (partially soldering process and solder-joints eliminated), f. Design density and functionality benefits (volume saving).

Capacitance can be distributed as an entire plane between the power and ground planes in the PCB, while the resistor layer can be deposited and etched away to requirement in a layer, thus having shorter leads and lower inductance. Additionally, embedded passives have no solder-joints. These two aspects enhance the reliability.

Figure: 13-1: Embedded R & C Figure: 13-2: Distributed C plane

Reference : Embedded Passives Technology, An Overview, 2004; Author: R. David Gerke

IPC Standards available can be referred in case required, IPC-2227, Sectional Design Standard for Embedded Passive Printed Board IPC-2316, Design Guide for Embedded Passive Device Printed Boards IPC-4811, Specifications for Embedded Passive Device, Resistor Materials IPC-4821, Specifications for Embedded Passive Device, Capacitor Materials IPC-6017, Qualification and Performance Specification for Printed Boards Containing Embedded Passives

13.2 Flexible PCBs

Assembly on all flex PCBs can be an issue, however, this PCB type and subsequent wiring requirements are at present not employed at ISRO. Though there are distinct advantages like low bulk and volume of a Flex assembly there are several concerns like fragile structure, low rework feasibility, etc.

Figure: 13-3: Flex card along with harness

There is a variant available in flex called sculptured flex, wherein, the copper goes through multiple-step etching to yield a flexible circuit with traces of different thicknesses to suit the purpose and extra thick at the card ends to facilitate plug-in without use of edge connectors

Figure: 13-4: Example of Sculptured flex card

Available standards that may be useful are – IPC-2223, Sectional Design Standard for Flexible Printed Circuit Boards IPC-4203/4, Material Specification Standards for Adhesive coated Dielectric Films and Metal Clad Flexible dielectrics ESCC-Q-ST-70-60, Qualification and Procurement of Printed Circuit Boards

13.3 Lead-less finish

This document is not covering Lead-less finish or lead-less soldering compatibility. Lead-less solders are not only known to have limited wettability, they are also known to have higher melting points. This increase in melting point would have multiple impact on reflow-profile as well as evaluation methodology. This requirement of addressing Lead-less solders shall be defined by specifications for assembly and wiring on PCBs covered in dcoument ISRO-PAX-300, “Workmanship Standards for the Fabrication of Electronic Packages” Hence, lead-less finish is not being addressed in the document herewith

Annexure 1: PCB Design Feature and Impact Trade off

PCB Design Features & Impact Trade-off (Impact shown for increase in PCB feature size, for decrease the impact shall be considered reverse of that shown) –

PCB feature Parameter Relation Impact Aspect Impacted

Line Spacing (lateral)

Cross-talk Isolation

Inverse Direct

Enhances Enhances

Electrical Yield

Line Spacing (vertical)

Cross-talk Inverse Enhances Electrical

Line width Cross-talk Zo

Direct (vertical) Inverse

Degrades To be watched

Electrical Electrical

Line Thickness Cross-talk Signal Integ.

Direct (lateral) Direct

Degrades Enhances

Electrical Reliability

Annular Ring Producibility Direct Enhances Yield

Aspect Ratio Via Integrity Producibility

Inverse Inverse

Degrades Degrades

Reliability Yield

Core Thickness

Cross-talk (latr) Cross-talk (ver) Zo Via Integrity Flatness

Direct Inverse Direct Inverse Direct

Degrades Enhances To be watched Degrades Enhances

Electrical Electrical Electrical Reliability Mechanical

Prepreg Thkns Same as that for core thickness

CTE (vertical) Via Integrity Inverse Degrades Reliability

CTE (lateral) Solder joint Integrity

Inverse Degrades Reliability

Resin Tg Via Integrity Solder joint Intg

Direct Direct

Enhances Enhances

Reliability Reliability

Resin Flow Delamination, voids Inverse Enhances Yield

Volatile Content

Delamination, voids Direct Degrades Yield

Rigidity Flexural Modulus Direct Enhances Mechanical

Cu Peel Strgth Land to laminate adhesion

Direct Enhances Reliability

Cu Plating Thickness

Via Integrity Direct Enhances Reliability

Finish HASL ENIG ENEPIG

Cu Protection Solderability Lead-free Planarity Wire-bonding

Direct a/b possible a/b/c/d possible a/b/c/d/e, all

Selective Preference c, d & e are NA b/e limited best option

Reliability& Yield Fine-pitch assembly difficult Ni Oxidation &processing Processing

PCB feature Parameter Relation Impact Aspect Impacted

Solder mask Cu Protection and prevent bridging in fine-pitch

Direct Enhances Reliability & Yield

Annexure 2 Process Capability Format (for reference only)

Format for Rigid Boards

Sr.No. Parameters Standard Complex

1 Base Material (CAF Resistance)

FR4, G10, PTFE, P95, ROGERS, Metal Clad, Taconic, Arion, Nelco, Panasonic

RT/duroid - 5870, 5880, 5880LZ, 6002, 6006, 6010, 6035 HTC, 6202, 86202 PR, As is required by Customer

2 Surface Finishes Lead Free HASL, HASL, ENIGold, ENI Palladium Gold, Immersion Tin, Immersion Silver, Carbon

Electrolytic Gold over Nickel, Electrolytic Direct Gold on copper, Electroless Direct Gold on copper, Electrolytic Palladium

3 Minimum Copper Thickness 1/2 Oz Copper (18 Microns) to 6

or (210 Microns) (Unbalanced copper Layers

also available on special r e q u e s t )

As is required by Customer

4 Board Thickness 14 mils to 125 Mils (0.35 to 3.2mm) Can be thicker for special MLB Back Panels

0.30 to 5.50mm

5 Minimum Core thickness for MLBs

4 mils (0.10mm) 3 Mils (0.078mm)

6 OL track Width / Space 5/5 Mils (0.127mm / 0.127mm)

4 Mils (0.10mm)

7 UL Track Width / Space 5/5 Mils (0.127mm / 0.127mm) 4 Mils (0.10mm)

8 Minimum Finished Hole size

8 Mils (0.20mm) 6 Mils (0.15mm)

9 Minimum SMD Pitch 19 Mils (0.50mm) 10 Mils (0.25mm)

10 Minimum Gap between SMDS

9 Mils (0.225mm) 7 Mils (0.20mm)

11 BGA Pit ch 31 Mils (0.78mm) 31 Mils (0.78mm)

12 Cu Thick/ Tr.Width/ Spacing

35 with 5 Mils Track/5 Mils Spacing 70 with 12 Mils Track/12 Mils Spacing 105 with 14 mils Track/14 Mils Spacing

35 with 5/5 Mils 70 with 10/10 Mils 105 with 12/12 Mils

13 Isolation Of Pads or Traces or SMTs on ground Planes

10 Mils Minimum (0.25mm) 8 Mils Minimum (0.20mm)

14 Inner Layer isolation 12 MIis (0.30mm) 10 mils (0.25mm)

15 Minimum Annual Ring 1/L via

5 MIis (0.125mm) 5 mils (0.125mm)

16 Minimum Annual Ring OIL via

5 mlls (0.125mm) 5 mils (0.125mm)

17 Minimum Annual Ring Comp

6 Mils (0.15mm) 5 mils (0.125mm)

18 Minimum Epoxy space in hatch

10 Mils (0.25mm) 8 Mils (0.20mm)

19 Aspect Ratio 10 : 1

12 : 1 20 Buried Via Yes Yes

21 Blind Via Yes

Yes

22 Maximum PCB or array Size

2L 15' X 20'. 4L 15' X 20'.

As standard

23 legend Character Width 7 Mils (0.175mm)

6 Mils (0.15mm)

24 Carbon(Resistance) >20 ohms

10 to 20 Ohms

25 Peelable Mask Thickness 300 microns

600 microns

26 Maximum dia for Peelable Mask

3.2 mm as per customer requirement

27 Non Standard Buildup Refer FINELINE

As standard

28 Minimum Scoring Web 12 Mils (0.30mm)

12 Mils (0.30mm)

29 PCB Edge to Clearance 8 Mils (0.20mm) Minimum 6 Mils (0.15mm)

30 Minimum NPTH Slot width

0.75mm

0.50mm

31 Board Thickness Tolerance +/- 10%

+/- 8%

32 PTH Tolerance +/- 3 Mils (+/- 0.078mm) +/- 2 Mils (+/- 0.050mm)

33 NPTH Tolerance +/- 3 Mils (+/- 0.076mm) +/- 2 Mils (+/- 0.050mm)

34 Routing Tolerance +/- 6 Mils (+/- 0.15mm)

+/- 4 Mils (+/- 0.100mm)


35 Press Fit Hole Tolerance +/- 2 Mils (+/- 0.05mm) +/- 2 Mils (+/--0.050mm)

36 Punching Fr4 Board Max Thickness

1.6 mm (0.062') 1.6 (0.062')

37 Punching [Single Punch & Remove] or [Punch & Retain]

As standard

Format for Rigid-flex Boards


A. MATERIAL

1. Rigid Section Nonnal Tg FR4, High Tg FR4, FR5, BT, Polyimide, Metal

2. Flex Section Polylmlde, LCP,Thin Core FR-4

3. Copper Foils ( RAor ED ) 0.25 oz (9um ), 0.33 oz (12um),0.5 oz (18um), 1.0 oz (35um), 2 oz (70um)

B. LAMINATION ( Flex Section ) MM MIL MM MIL

1. Max, Layer Count B L 10 L

2. Min. Dielectric, Thickness 0.05 2 0.05 2

3. Min. Base Copper Thickness 0.018 0.7 0.07 3

C. PATTERN CAPABILITIES AND TOLERANCES

1. Min Trace and space ( 0.25oz) 0.076 / 0.076 3/3 0.076 / 0.076 3/3

2. Min. Trace and space (0.33oz) 0.10 / 0.10 4/4 0.10 / 0.10 4/4

3. Min. Trace and space (0.5oz l 0.127 / 0.127 5/5 0.10 / 0.10 4/4

4. Min Trace and soace ( 1.0oz l 0.127 / 0.127 5/5 0.10 / 0.10 4/4

5. Min Outer laver Pad size = FHS plus dr!-0.30 12/12 dr+-0.25 10/10

6. Min Innerlayer Pad size = FHS plus dr!-0.35 14/14 dr+-0.30 12/12

7. Min. Inner layer Plane Clearance = FHS plus dr!-0.60 24 dr+-0.55 22

8. Min. Legend Line Width 0.18 7 0.15 6

D. DRILL CAPABILITIES

1. Finish Hole Diameter Tolerance

Plated +/-0.075 3 +/-0.050 2

Non-plated +/-0.050 2 +/-0.050 2

2. Cu Thicknessin Throu11h Hole >0.025 1 >0.025 1

3. VIS Formation

E. MECHANICAL DRILLING

1.Aspect Ratio 8 : 1 10: 1

2. Min. Drilled Micro via Diameter 0.25 10 0.20 8

3. Min. Finished Micro via Diameter 0.20 8 0.15 6

4. True Position Tolerance ( Riaid Section l 0.15 6 0.10 4

5. Min Hole-ed11e-to-Hole ed11e ( depend on

0.30 12 0.25 10

6. Board I mck. And drlll bit size)

F. PLASMA ETCHING

1. Min. etched Micro via Diameter 0.25 10 0.20 8

2. Min. Finished Micro via Diameter 0.20 B 0.15 6

3. True Position Tolerance ( Rigid Section ) +/-0.15 6 +/-0.15 6

G. FABRICATION TOLERANCES

1. Min. Trace to =ute Eelge D1mens10n 0.20 8 0.20 8

2. Min. Route Dimensional Tolerance +/-0.15 6 +/-0.13 5

3. Min. Tolerance of ZIF Connector to Edge of Flex

+/-0.13 5 +/-0.13 5

4. Min. Feature to Feature Dimensional Tolerance

+/-0.13 5 +/-0.13 5


5. Impedance Tolerance ( design dependent) (500hm+

+/-10% +/-5%

H. SOLDER MASK & PHOTOIMAGABLE COVERLAY

1. Min. claerance

eVia Hole Covered Covered

eComponent Hole 0.05 2 0.05 2

•Feature definition 0.15 6 0.15 6

I. COVERLAY

1. Min. clearance

eVia Hole Covered Covered

•Component Hole 0.15 6 0.10 4

•Feature definition 0.20 B 0.15 6

J. SURFACE FINISH

1. Gold/ NiCKBI (Electrolytic Pure Gold) yes yes

2. Gold/ Nickel ( Electrolytic Hard Gold yes yes

3. Gold/ Nickel ( immersion / electro less )

a. Nickel Thickness >3.8um >0.15 >3.Bum >0.15

b. lmmer111on Gold thickness 0.05-0.1um 0.002 to 0.004

0.05-0.1um 0.002 to 0.004

4. Selective EN / IMG yes yes

5. HASL, aer lrlickness 4 -Bum 0.16 to 0.32 4-Bum 0.16 to 0.32

6. Immersion Silver yes yes

7. Immersion Tin yes yes

8. Lead free Compatible yes yes

K ELECTRICAL TEST CAPABILITIES

1. Smallest SMD Pitch 0.50 20 0.50 20

2. Smallest BGA Pitch 0.78 31 0.78 31

L CONTROLLED IMPEDANCE

1. Impedance Control Tolerance +/-10% +/-5%

2. Differential Impedance Control Tolerance +/-10% +/-5%

Format for RF/Microwave Boards


A MATERIAL

Rogers RT/duroid 587015880 / 6002 / 600616010 IRO 3000 / TMM 10i

Others Mon / Neltec /Taconic / Polyfon

Material Details

Random Glass, Thermoset polymer. woven glass ceramic fillers, PTFE with ceramic fillers, LCP ,CIC

Copper Foils RA or Ed ) 0.25oz.(9um\/ 0.33oz.112umlI0.5oz.118umlI10z.35umlI2o:i!.l70uml

Copper back up 0.50mm. 11.0mm.I2.0mm. 13.0mm

Hvbrid Contruct on Rogers materials with Fr 4 materials

B BOARD DIMENSIONS MM INCH MM INCH

1. Max standard panel size 457 X 610 18 X 24

Other oversized boards are to be assessed after the Gerber

verification

2. Min. standard Panel size 101X 152 4 x 6

3. Large format capability 100 X 787 4x 31

4. Large Antenna capability 100 X 1016 4x 40

5. Minimum laminate thickness 0.127 0.005

6. Max.Board Thickness 3.50 0.138

C CIRCUIT CAPA.BILITY

1.Min. Trace and Space 0.25 oz / 9 um l 50 um 0.002

2.Min.Trace and Space 0.5 oz I18 uml 75 um 0.003


3. Min.Trace and Space 1.0 oz I35 um 125 um 0.005

4. Min.Trace and Space 2.0 oz I70 um l 150 um 0.006

D PAD • DRILLED REGISTRATION

Standard & Complex +/· 50 um +/-0.002 +l-30um +10.0011

MINIMUM ANNAULAR RING

Standard & Complex 100 um 0.004 50 um 0.002

E IMAGE REGISTRATION

Standard & Complex +/. 45 um +/. 0.0018 +/. 25 um +l-0.001

F DRILL CAPABILITIES

1.Finish Hole Diameter Tolerance

Plated +/-0.075 0.002 +/-0.05 0 002

Non-plated +1-0.05 0.001 +/-0.05 0.002

2.Cu Thickness in Through Hole >0.025 0.001 >0.025 0.001

G MECHANICAL DRILLING

1.Asoect Ratio 10:1 11:1

2.Aspect Ratio with metal back up 8:1 10:1

3. Min. Drilled Micro via Diameter 0.20 0.008 0.15 0.006

4.Min. Drilled dia.with metal back up 0.60 0.024 0.5 0.020

5.Min.Hole- edge-to-Hole edge 0.35 0.014 0.30 0.01

(depend on Board Thick. And Drill Bit I

H MECHANICAL MACHINING & TOLERANCE

1.Min.internal radii( metal back up) 0.50 0.020 0.40 0.0,6

2.Min.route Dimensional Tolerance +1-0.10 +1-0.004 +/-0.05 +1-0.002

3."Z- axis depth control! +/•0.15 0.006 +/-0.13 0.005

I CAVITY DESIGN

1.Cavitvin Inner lavers • minimum core thickness

0.50 0.020 0.40 O.Q16

2.Cavitvinouter lavers with/Without cu. back up

0.50 0.020 0.40 0.016

K PLASMA ETCHING 1.Min. Etched Micro via Diameter

0.25

0.010

0.20

0.008

L SODIUMTREATMENT

1.Min. Etched Micro via Diameter 0.25 0.010 0.20 0.008

M SOLDER MASK

Type : Electra EMP110

Colour: Green Blue, Red. white .Black, Transparent

Hardness :6H

Min. clearance 0.10 0.004 0.08 0.003

Micro Vie Hole Covered Covered

Comment Hole 0.13 0.005 0.10 0.00

Minimum solder mask Dam 0.20 0.008 0.15 0.006

N PEELABLE SOLDER MASK

Type : Peters ink 2955

Minimum thickness 0.30 0.012 0.20 0.008

Colour : Green Red

O SURFACE FINISH

1.Electrolvtic oure Soft Gold Direct on Copper

Yes Yes

Gold Thickness Gold wire bonding) > 0.5 to 5.0 um > 0.5 to 5.0 um

Gold Over hana Controlled to < 10 um 510 7 um

2. Electrolytic Pure Gold on Nickel barrier

Yes Yes


3.Electrolytic Hard Gold on Nickel barrier

Yes Yes

4. Electroless Nickel & Immersion Gold (ENIG)

Yes Yes

a.Nick.et Thickness >3.8um >3.8um

b. Immersion Gold Thickness 0.05-0.1um 0.05-0.1um

5.ENEPIG

6.EPAG

7.Selective Hard Gold with ENIG Finish 0.5 to 3.0um 0.510 3.5 um

8. Selective Hard Gold with Hal Finish 0.5 to 3.0um 0.5to 3.5 um

9. Selective ENIG IHAL Combination Yes Yes

10. HASL/ LFHAL Solder Thickness 4 to 8 um 4 to Bum

11. Immersion Silver yes yes

12. Immersion Tin yes yes

Annexure 3: Facility Audit format for PCB Manufacturing Job in progress

Sr. No.

Type of PCBs & its Identification Stage of work Observation

1

2

3

Laminate / Pre-peg Storage

Sr. No.

Particular Requirements Observation

1 Laminate segregation Shall be segregated separately each type & labelled as “only use for ISRO”

2 Storage of Laminate All Laminates shall be store parallel to plane. Shall be store in controlled environment. (Temperature: Less than 20°C)

3 Storage of Pre-peg All pre-preg shall be store parallel to plane. Self-life (Manufacturing & Expiry date) of the pre-preg. Expiry pre-preg shall be segregate & it shall be discard from stock. Shall be store in controlled environment. (Temperature: Less than 20°C, RH: ≤ 50% ---- for 3 Months or Temperature: Less than 5°C, RH: ≤ 50% ---- for 6 Months).

4 CoC Shall be available at the time of facility audit for all the laminates & pre-preg.

5 Film Storage Shall be store in controlled environment in individual bag. (Temperature: Less than 20°C, RH: ≤ 50%). Individual films bag shall be hang with clip & shall be check for wrinkle free.

6 Dry Film Check for self-life mentioned by manufacturer

7 Yellow Room Temperature: 23 ± 2 ºC

Humidity: 50 ± 10% RH

Light Intensity : Light shall be Yellow in room & Min. 60 lm/m2 on work place.

Particulate level: Class-100000 or better

Air shower for minimum two persons capacity at the entrance of Room.

Clean room Garments: Clean antistatic aprons with head caps & shoe covers and its maintenance.

Sr. No.

Particular Requirements Observation

Exposing & Developing parameters shall be as per PID.

8 Drilling Drilling parameters entered in log book shall be as per PID.

Type of drill bit & router shall be as per PID.

Entry back up material and stack height shall be as per mentioned in PID.

Changing of drill bit records shall as per mentioned in PID (i.e. After 300 hit drill bit shall change)

Over all cleanness after drilling

9 Plating Records of in-house chemical analysis & maintaining of chemical composition.

Separate plating lines for ISRO PCBs manufacturing,

Plating parameters shall be as per PID.

10 HAL Check records for solder bath analysis (shall be done every 3 months).

Bath temperature / air Knife temperature, air pressure parameters logbook & shall be as per PID.

11 BBT Records of BBT shall be verified.

12 Trained manpower QC Inspector

Sufficient Nos. of inspectors certified during qualification. In-house Microsectioning records shall be verified.

13 Equipment calibration facility

All equipment / machine shall be calibrated by third party / In-house.

14 Documentation & non-conformance management procedures

Records for the verification of process parameters & process traveler’s sheet shall available in Facility.

Annexure 4: Acceptance Tests

Sr. No. Tests Test Method Accpetance criteria

Test Report

1 Peel Strength

2 Bond Strength

3 Rework simulation

4 Solder dip

5 Solderability

6 Interconnect resistance

7 Insulation resistance intra-layer

8 Insulation resistance inter-layer

9 Dielectric withstand voltage intra-layer

10 Dielectric withstand voltage inter-layer

11 Microsectioning of initial sample

12 Microsectioning of solder dip tested samples

13 Microsectioning of rework simulated test sample

14 Controlled impedance test1

15 Bend test2

16 Endurance test3

1Only for controlled impedance requirements. 2Only for flex or rigid-flex PCBs.

Annexure 5: Mechanical Inspection Report Format REPORT NO: PROJECT: DATE: MODEL:

INSPECTEDBY Note: Unless otherwise specified in drawing, the acceptable values for the listed parameters are: cardsize±0.2mm, pitch±0.1mm, thickness ±0.15mmfor<2.4mm PCB thickness, ±10%for>2.4mm PCB thickness, Free holes dia +0.1/0.0mm, warp maximum 1.0% of length and twist maximum 1.0% of diagonal length.

SL NO. CARD NUMBER SPECIFIED DIMENSIONS Card size, pitch, thickness, free hole dimensions

MEASURED DIMENSIONS, WARP AND TWIST Card size, pitch, thickness, free hole dimensions

BOX MATCHING/TRIAL SUITING

REMARKS

DISPOSITION

ACCEPTED

REWORK

CLARIFICATION

REJECTED

Annexure 6: Micro section and Report Format A

Card No: Batch No: Panel No:

No of Layers Qty /Panel QA/QC Code

SL. NO

PARAMETER OBSERVATIONS (VALUE IN MICRONS) Unless otherwise specified in the ordering sheet the default values are as below

HOLENO. HOLENO. SIDE 1 SIDE 2 SIDE 1 SIDE 2 1.LANDREGION(TOP) 01 02 03 04 05 06

Total Copper Thickness Basic Copper Thickness Deposited Copper Thickness Protective plating thickness At center max. (for tin lead) On side max. (for tin lead) At knee Conductor undercut Solder mask thickness

52.5/70/105+10microns 18+4/35/65+5microns 35+10microns 8to30 microns 8to30microns minimum1µm/just coverage <Cu thickness. 17to25 microns II. HOLEWALL

01 02 03 04

Copper thickness Protective Plating thickness (for tin lead). Copper thickness at knee Resin recession

35+10 microns 8to30 microns 35+10 microns Lessthan20%

III. LANDREGION (BOTTOM) 01 02 03 04 05 06

Total Copper Thickness Basic copper thickness Deposited copper thickness Protective plating thickness At center max. (for tin lead) On side max (for tin lead) At knee Conductor undercut Solder mask thickness

52.5/70/105+10microns 18+4/35/65+5microns 35+10microns 8to30 microns 8to30 microns minimum1µm/just coverage <Cu thickness. 17to25microns.

01 Homogeneity Drilling/barrier regularity Protective plating uniformity Registration error Other defects, if any.

Max.80microns 8to30 microns Max.250micronsprovidedannularringrequirementsare met.

1. If protective plating is gold, then thickness is 2.5 to 3 microns. 2. If protective plating is gold over nickel, then 3 to 5 microns of nickel and 1 to 3 microns of gold is required.

Annexure 7: Micro section and Report Format B

HOLENO: SIDE NO: HOLENO: SIDE NO: Layer no

Copper thickness

Etch back

Dielectric separation

Annular ring

Layer No

Copper thickness

Etch back


Annular ring

Remarks

01 1-2: 01 1-2: 02 2-3: 02 2-3: 03 3-4: 03 3-4: 04 4-5: 04 4-5:

05 5-6: 05 5-6: 06 6-7: 06 6-7: 07 7-8: 07 7-8: 08 8-9: 08 8-9: 09 9-10: 09 9-10: 10 10-11: 10 10-11: 11 11-12: 11 11-12: 12 12-13: 12 12-13: 13 13-14: 13 13-14: 14 14

HOLENO: SIDE NO: HOLENO: SIDE NO: Layer no

Copper thickness

Etch back


Annular ring

Layer No

Copper thickness

Etch back


Annular ring

Remarks

01 1-2: 01 1-2: 02 2-3: 02 2-3: 03 3-4: 03 3-4: 04 4-5: 04 4-5: 05 5-6: 05 5-6: 06 6-7: 06 6-7: 07 7-8: 07 7-8: 08 8-9: 08 8-9: 09 9-10: 09 9-10: 10 10-11: 10 10-11: 11 11-12: 11 11-12: 12 12-13: 12 12-13: 13 13-14: 13 13-14: 14 14 Unless otherwise specified the default values of inner layer Cu thickness is 65±5-micron sandpit shall not be less than 30 microns (for 12 or 14 layer MLBs). Preferred etch back 5 to 13 microns (100% desmearmandatory), minimum annular ring of 50 microns for inner layer and annul arring of 130 microns for outer layer. For half flounce basic coper thickness, total copper thickness shall be between 52.5±10 microns. Minimum dialect tic thickness shall be generally 150 microns. Unless otherwise supported by requirement specifications dielectric thickness less than 100 microns shall be referred to appropriate forum for disposition. However, in case it shall be less than 90 microns. Negative etch back beyond 5 microns shall not be accepted.

Annexure 8: Coupon Test Result Format

Card No: Batch No: Panel No: Layers Qty/Panel

INSULATIONRESISTANCE(INTRALAYER) SPEC.:>1 x 1010ohms

INSULATIONRESISTANCE(INTERLAYER) SPEC.:>1 x 10 11ohms

INTERCONNECTIONRESISTANCE SPEC.:< 3 mΩ per layer for 2 ounce; < 6 mΩ per layerfor 1 ounce

1-1 1 1-2 1-2 2-2 1 2-3 2-3 3-3 1 3-4 3-4 4-4 1 4-5 4-5 5-5 1 5-6 5-6 6-6 1 6-7 6-7 7-7 1 7-8 7-8 8-8 1 8-9 8-9 9-9 1 9-10 9-10 10-10 1 10-11 10-11 11-11 1 11-12 11-12 12-12 1 12-13 12-13 13-13 1 13-14 13-14 14-14 1 PLATED THROUGH HOLE BOND STRENGTH AFTER 5TIMES REWORK SIMULATION at 300 oC soldering temperature SPEC.;>7.12 Kg/mm2 (9kg pull force )

TRACK PEEL STRENGTH SPEC.; minimum1.2kg/cm

SOLDERABILITY SPEC. :>95% Wetting on conductor surface

Observations Values To Be Recorded



Solder Di Ptest Icrbeforeandaftr Solderdipat288oc,2 Cycles With 120secondsbreakbetweendips. (3 Dips For Tg >180oc) Spec.: Icr Shall Not Increase> 10% W.R.T. Initial reference value.

M/Saftersdt Pthwall & Inner Layer Interface With Wall Integrity After Solder Dip SPEC.:Microsectioned samples shall not have barrel separation, cracks, thick demarcation line between plated copper and inner layer copper presence of crack, smear, discontinuity are not allowed.

Dielectric With Standing Voltage SPEC.:With350V-AC for 30 seconds Leakage current < 100µA

Observations / Values To Be Recorded



Rework Simulation Icr Measurement Prior To Rework Simulation And Icr Measurement After Rework Simulation Spec.: Icr Shall Not Increase> 10% W.R.T .Initial reference value.

M/S AFTER R/W SIMULATION Microsectioned samples shall not have barrel separation, cracks, thick demarcation line between plated copper and inner layer copper presence of crack, smear, padlift, discontinuity not allowed.

HIGH TEMPERATUREICR ICR Measurement shall be doneat Tg+10o C and % increase from ambient shall be less than +90% (<1.9times) of initial value. (Optional Test : when any one of the board fails in open mode BBT after hot air evening)

Observations Values To Be Recorded Observations Values To Be Recorded Observations Values To Be Recorded

NONCONFORMANCE REPORTS/DETAILS, IFANY: ACCEPTED/REJECTED

M/S: Micro section SDT: Solder Dip Test

Annexure 9: Final Inspection Report Format Every card inspected shall be accompanied by a visual inspection report. The report format is enclosed.

Card No: Week-Year Panel No: Layers Qty/Panel Weighting

Centre ISAC/VSSC/IISU/SAC Project Tobe filled by PCB project allocating agency

Batch No: QA code:

S. No PARAMETER SPECIFICATION/Ref. Para. OBSERVATION 1.0 BOARDQUALITY 1.1 Material IPC4101complied 1.2 Board dimension LxW as specified in Layout± 0.2 mm 1.3 Stacking hole pitch As specified in layout ± 0.1 mm 1.4 Stacking hole diameter As specified in layout ± 0.1 mm 1.5 Board Thickness(metal- to-

metal) 1.6mmto2.2mm+0.15mm

1.6 Board Warpage <1%ofthelength 1.7 Edge trimming Smooth finish, haloing/chipping

<0.25mm

1.8 Visual cleanliness of PCB Presence of dirt, grease, fingerprints, oils, chemicals, Solvent residues not allowed.

1.9 Laminate materials defects Crack/Chipping/Discolorations/EpoxyStarvation/Crazing/Blistering/WeaveExposure/Delamination/Measling/foreignmaterials/Weavetexturenotallowed.

1.10 Laminate materials defects Mea sling

< 10 Sq. mm continuous, should not bridge > 25% Between pad & conductor

2.0 PAD/hole 2.1 Location & dia As per Master pattern 2.2 PTH & NPTH drilling Extra PTH/NPTH not allowed.

2.3 PTH Hole diameter +0.05/-0.00 mmupto1mm holes +0.10/-0.00 mm beyond1mm

2.4 Annular ring PTH NPTH

External layers > 0.13 mm > 0.25 mm

2.5 PTH defect Chipping /Torn cladding /Burrs/ voids> 80 microns/ Nodules/de-lamination,Laminateexposurearoundthehole-Nottobepresent

2.6 PTH in place of NPTH and vice versa

Not allowed

2.7 PTH hole block Allowed for the rmalviasa not allowed for regular vias.

3.0 CONDUCTOR As per Master pattern 3.1 Width 0.2mm(minimum)

0.15 mm(minimum)for fine pitch SMD/CCGA/BGA. Oras specified in layout; +0.00 mm: -0.03 mm for ½ oz. Copper +0.00mm: -0.05mmfor1ozCopper +0.00mm:-0.10mmfor2ozCopper

3.2 Spacing 0.2 mm [0.1 mm special cases] or as specified in layout+10%

Signature of the Inspector Name: & Date: Auditor/Reviewer comments: Auditor/Reviewer signature

3.3 Defect sin conductor pinhole/pits/void/cut/scratch/ dent/line definitions

Defects shall not reduce the width by more than10%inanycombination

3.4 Copper visibility Nilunder10X

4.0 PROTECTIVECOATING/PLATING

Solder Nickel-Gold or Gold Fused Not fused

4.1 Plating Defects Porosity/Blisters/Wrinkles/granularsurface/dewettingnottobepresent

4.2 Micro sectioning[ test coupon result]

As per given format PASS/FAIL

4.3 Solder Masking Defects Soldermaskoverlappingonpads/scratches,peeloffs,contamination,non-uniform colour, tackiness, ragged edges not allowed

4.5 Solder Mask thickness 17-25microns.Refer Micro section data.

4.6 BBT Results Ensure BBT is conducted and BBT OK tag is enclosed

PASS/FAIL

5.0 ACCEPTANCETESTS As per para 7.10.3

PASS/FAIL

5.1 Peel strength

5.2 Rework simulation [5times]

5.3 PTH bond strength

5.4 Interconnection resistance

5.5 Insulation resistance

5.6 Dielectric withstanding voltage

5.7 Solderability

5.8 Solder dip test

5.9 High temperature ICR

REMARKS IF ANY: ACCEPTED/REJECTED/ACCEPTEDBYAPPROPRIATEFORUM

Annexure 10: Non Conformance Report

NON-CONFORMANCE REPORT NCR No. DATE:

PROJECT

ORIGINATOR DRAWING No. ITEM NO MENCLATURE MODEL

SUBSYSTEM

NON-CONFORMANCEDESCRIPTION

PROBABLECAUSE DESIGN PARTS MATERIALS MANUFACTURING HANDLING TESTEQUIPMENT SOFTWARE OTHERS

REPERCUSSION AFFECTSASSEMBLY AFFECTS FUNCTION AFFECTSRELIABILITY AFFECTS INTERCHANGEABILITY AFFECTSWEIGHT AFFECTSSAFETY OTHERS(SPECIFY)

CLASSIFICATION MINOR MAJOR

REFERREDTOMRBON: DISPOSITION ON: ACTIONCOMPLETED ON:

*MRB No.

Annexure 11: Typical Micro Section Defects

Figure: 13-5: Typical PCB Microsection Defects

A Undercut

B Outgrowth

C Overhang 1. (Resin) Blistering 2. Laminate Void 3. (Resin) De-lamination 4. Pad Cratering 5. Lifted Land Crack 6. Burr 7. Bond Enhancement Removed-

“Pink Ring” 8. Negative Etch back 9. Foil Crack 10. Hole Plating Void 11. Wedge Void 12. Glass Fiber Void

13. Glass Bundle Void 14. Severe Etch back 15. Nail Heading 16. Drill Wall Tear / Wicking 17. Negative etch back 18. Hole Wall Pull Away 19. Corner Crack 20. (Copper) Blistering 21. Glass Fiber Protrusion 22. Inner layer (Post) Separation 23. Wicking 24. Over Plating Resist Void 25. Positive Etch back 26. Barrel Crack 27. Shadowing 28. Nodule

29. Resin Smear 30. Copper & Over Plate Void 31. Burned Plating 32. Copper Foil Contamination 33. Lifter Land 34. Resin Crack De-lamination 35. Crazing 36. Foreign Inclusion 37. Prepreg Void 38. Copper Clad Laminate Void 39. Measling 40. Resin Recession 41. Glass-Weave Texture 42. Glass-Weave Exposure