tutorial upf 026261

1

Multivoltage IEEE P1801 (UPF)

Methodology Update for B-

2008.09 Release of Design

Compiler and IC Compiler

2

Agenda

Galaxy IEEE P1801 (UPF) Low-Power Overview

Implementation Using Design Compiler

Design Compiler to IC Compiler Interface

IC Compiler IEEE P1801 (UPF) Methodology Overview

Design Planning

Physical Implementation

3

Agenda


Implementation using Design Compiler



Design Planning


4

UPF

RTL

PG

Netlist PrimeRail

Formality

Ref

Impl

Formality

Ref

Impl

Synopsys IEEE P1801 (UPF) Flow

PrimeTime

PrimeTime PX

UPF”

Gate

IC Compiler

VCS+MVSIM

MVRC

PrimeTime

PrimeTime PX

UPF’

Gate

Formality

Ref

Impl

Design Compiler

Power CompilerVCS+MVSIM

MVRC

5

Agenda


Implementation Using Design Compiler



Design Planning


6

IEEE P1801 (UPF) Methodology in

Design CompilerSetup Libraries

Read the RTL

Read the Power Intentload_upf

Apply Design Constraints

compile_ultra -scan

insert_dft

compile_ultra –scan -incr

Write the Design (DDC/ASCII/MW)

• UPF constraints are

honored during compile_ultra

• Power management

cell insertion

• Test follows UPF

constraints used during compile_ultra -scan

7

Always-on SynthesisDefinition

• Control signals for

power management

cells have to be live

while the logic around

are shut down

– Optimizing such

control signals with

special cells having

secondary power

(back-up power) is

always-on synthesis

PD_A 0.8V

PD_B 0.8V, OFF

RR

save

restore

ao

ao

ao

ao

8

Always-on Inference

• Automatic always-on inference

– Enable pins of enable level shifter

and isolation cells; save and

restore pins of retention registers

and control pin of switch cells are

automatically treated as always-

on anchor points

– Always on marking is done by

tracing back from always-on pins

• Control signals of special

cells such as isolation cells,

retention registers, enable

level shifters and switches are

treated as always on nets

• Always-on inference based on user

defined attributes

– Pins that have been marked as always on by the user using set_attribute

set_attribute my_cell/a

always_on true

– Always-on tracing stops at a multi input

cell

– Traces through buffers and inverters only

PD_B

PD_A 0.8V

PD_B 0.8V, OFF

RR

save

restore

ao

ao

ao

ao

9

Always-on Synthesis Feedthrough Nets

• Always-on power or ground

connections for buffers and

inverters are determined by

– The fanout of the net in the

domain

– Feedthrough nets do not have

any fanout in the domain

• Such always-on nets will be marked as dont_touch

VD

DB

Backu

p p

ow

er

PD_B0.8V, OFF

RR

save

restore

ao

ao

ao

aoAO

VD

DP

Pri

mary

po

wer

AO

10

Always-on SynthesisFeedthrough Net Example 1

• PD_TOP, PD_A are shutdown

domains

• PD_B is an always on domain

• iso_en drives the enable pin

of the isolation cells in PD_A

• The segment of net iso_en in PD_A will be marked always-

on

• Always-on buffers inserted will have their power and ground

pins connected based on the load of this net, i.e. the enable pin

of the isolation cell

PD_TOP0.8V, OFF

PD_A0.8V, OFF

PD_B1.0V

ISO

iso_enaoao, d

11


• PD_TOP, PD_A are shutdown

domains

• PD_B is an always-on domain

• iso_en drives the enable pin

of the isolation cells in PD_A

• The segment of net iso_en in PD_TOP will also be marked

always-on

• There is no load in PD_TOP. So the tool cannot derive the

power and ground connections required for always-on

buffering

• The segment is also marked dont_touch

• If this is a long wire, it could have max transition and/or max

capacitance violations

PD_TOP0.8V, OFF

PD_A0.8V, OFF

PD_B1.0V

ISO

iso_enaoao, d

12

• Manually insert an always-on buffer on the iso_en net in PD_TOP

• Mark its input pin as always-onset_attribute ao_buff/a always_on true

• Connect its power and ground pins to the proper always-on power

and ground suppliesconnect_supply_net –port ao_buff/VDDB VDDON

connect_supply_net –port ao_buff/VSS VSS


PD_TOP0.8V

PD_A0.8V, OFF

PD_B1.0V

ISO

• The net driving this buffer will now

be always-on, and be bufferable

by the always-on synthesis

• The net driven by this buffer will still be marked dont_touch

• Place the always-on seed buffer

close to the port to avoid DRC

violations on this net segment

AOAOAO

13


• PD_TOP is a shutdown domains

• iso_en is a top level feed through

net that needs to be always on

(drives an always-on cell at the full

chip level)

• To force the tool to perform always-on synthesis on net iso_en :

• Set the always-on attribute on the port iso_enable

set_attribute [get_ports iso_enable] always_on true

• Set the related supply nets for this port to the required always-on

power and ground supply netsset_related_supply_net –power VDD_ON –ground VSS –

object_list [get_ports iso_enable]

PD_A1.0V, OFF

PD_TOP0.8V, OFF

iso_en

set_attribute

set_related_supply_net

14

• Multivoltage designs require level shifters to

correct the voltage violations

– For some users, there are very specific locations that

are valid for level-shifter insertion

• e.g. Level shifter can only reside inside the blocks and not in

the top-level hierarchy

– Only want to use level shifters of a certain type in the

design or block

• For example, only low-to-high type level shifters are

necessary as all cells in the design can be over-driven

Level-Shifter Insertion

15

• Level shifter constraints from the UPF are soft constraints– The location argument reduces the solution space for

level-shifter insertion

• The power state table, PST, is used for level-shifter insertion decisions– If the PST is defined, only valid PST states are taken

into consideration for voltage violations

– If the PST is not defined, all port state combinations are considered for voltage violations

Level-Shifter InsertionVoltage Violations on Global Nets

16

• Paths from PD_Top to PD_B do not require level shifters as they both operate at the same voltage

• Paths from PD_Top to PD_A and from PD_A to PD_B need level-shifter cells as PD_A operates at a different voltage

Level-Shifter InsertionVoltage Violations on Global Nets

PD_Top 1.1V

PD_A

0.8V

PD_B

1.1V

?

?

? ? ? ?

Valid location for level-shifter insertion?

17

• The UPF set_level_shifter constraint is a

soft constraint

– Location specification is used to figure out valid level-

shifter insertion locations if level shifters were inserted

• -location self allows insertion inside power domain

• -location parent allows insertion outside power

domain

– All power domains have a default level-shifter strategy

that allows insertion anywhere to resolve voltage

violation

set_level_shifter <domain_name> -location

automatic -applies_to both -rule both

Level-Shifter InsertionHow to Reduce the Solution Space

18

set_level_shifter PD_A

-location self

-applies_to inputs

set_level_shifter PD_A

-location parent

-applies_to outputs

Level-Shifter InsertionReducing the Solution Space

PD_Top 1.1V

PD_A

0.8V

PD_B

1.1V

X

?

X ? ? ?

Valid location for level-shifter insertion?

Invalid location for level-shifter insertionX

19

• This design should use only low-to-high level shifters

• Will the following be sufficient for PD_A & PD_B?

set_level_shifter \

-applies_to inputs \

-rule low_to_high \

-location self

Level Shifter-InsertionOnly Insert Low-to-High Level Shifters

PD_Top 1.1V

PD_A

0.8V

PD_B

1.1V

Test Decompressor

20

• Every power domain

has a default level-

shifter strategyset_level_shifter \

-applies_to both \

-rule both \

-location automatic

• Need to override

default strategyset_level_shifter \

-applies_to both \

-rule low_to_high

Level Shifter-InsertionOnly Insert Low-to-High Level Shifters

PD_Top 1.1V

PD_A

0.8V

PD_B

1.1V

LS

LS

Test Decompressor

LS

H2L

H2LL2H

21

• Isolation cells are used to prevent dead logic

from driving live logic

– Support for more isolators

• Able to support having isolators whose primary

power and back-up power are different

– Support for pre-instantiated methodologies

• Able to associate manually instantiated isolators in

their own hierarchical wrappers to UPF isolation

constraints

Isolation Cells

22

• Isolation power for an

isolation cell can be

different than the primary

power of the power domain

– Power Domain operates at

1.08V

– Isolation Power runs at 0.8V

– Any buffers or inverters

inserted on the control signal

will operate at the voltage of

isolation power

Support for Isolation Cells with

Different Primary and Isolation Power

PD_A

1.08V

ISO

ISO Power

0.8V

0.8V

Data

@1.08V

Ctrl

@0.8V

Primary Power

1.08V

23

Support for Isolation Cells in WrappersB-2008.09-SP1

• Pre-instantiated isolators can be in self or parent

– Will trace from port inwards or outwards through

hierarchical boundaries until either a cell or a power

domain boundary is encountered

– If cell is isolator, will be associated to the UPF

isolation constraint

• Design Compiler or IC Compiler can determine the power

and ground connections for the isolator based upon isolation

constraint

• UPF-75 messages during check_mv_design reports that

a specific isolator has been associated with a specific

isolation strategy

24

Support for Isolation Cells in WrappersB-2008.09-SP1

• Pre-instantiate ISO cells placed in their own hierarchical

wrappers can be matched to UPF isolation constraints

– These isolators are output isolators of PD_A with a

location of self

PD_A

ISO

ISO

ISO

ISO

25

• Isolation constraints initially honored using GTECH cells

– Mapping will convert the GTECH cells to technology isolators, either ISO or ELS as necessary

• 6 flavors of GTECH isolators are available

– Clamp values: 0, 1, latch

– Enable sense: 0, 1 for each clamp value

Isolation CellsWhy Do I Have GTECH in my Netlist?

26

• Will see a TRANS-11 warning if Design

Compiler cannot convert GTECH isolator to

technology isolator

Warning: Target library contains no

replacement for isolation cell '%s'

(%s); it was not translated. (TRANS-11)

– Are your isolation cells marked as dont_use?

– Do your isolation constraints match your technology

isolators?

– Can your isolation cells be used where you are

specifying them?

– Do you have always-on inverters?

Isolation CellsTRANS-11

27

• Combines semantics of an isolation cell and a

level shifter in a single cell

– Cell needs to match the isolation constraint, and

– Cell needs to be able to shift all possible voltages as

defined in PST

• How do you infer an enable level shifter?

Enable Level Shifters

28

• Conceptually, Design Compiler needs to see an

isolation cell directly connected to a level shifter

on the same side of the power domain boundary

Enable Level ShiftersHow Do I Infer Enable Level Shifters?

PD_A

ISOLS

• Level shifter + Input isolation

cell is a candidate for

replacement with an enable

level shifter.

• Isolation power of isolation

cell becomes the driving

power of enable level shifter

For illustrative purposes only

29

• Design Compiler attempts to map the GTECH

isolation cell directly to an enable level-shifter

based upon voltage violations

– Isolation power of isolation cell becomes driving

power of enable level shifter

– Pwr 2 is the switched version of ISO Power

Enable Level Shifters Enable Level-Shifter Mapping

ISOLSELS

ISO Power ISO PowerPwr 1 Pwr 1Pwr 2 Pwr 2

30

• Isolation cell and level shifter are separated by a

hierarchical or power domain boundary

Enable Level Shifters Mapping Example 1

Isolation cell belongs to PD_A

Level shifter is shifting to the

voltage of PD_A

Solution:

• Move the isolation constraint

from self to parent, or

• Move the level shifter from

parent to self

PD_A

ISOLS

31

PD_B

• Isolation cell and level shifter are separated by a

hierarchical or power domain boundary

Enable Level Shifters Mapping Example 2

Isolation cell belongs to power

domain, PD_A

Level shifter is inserted inside of

PD_B

Solution:

• Force the level shifter from

self in PD_B to self in PD_A

• no_shift for PD_B, and

• self for PD_A

PD_A

ISOLS

32

• Retention registers are useful for designs

that have to recover the state of their block

after coming back from shutdown

– Ability to use retention registers whose

retention power differs from the primary power

of the power domain

– Getting GTECH in your designs instead of

retention registers

Retention Registers

33

Specification in the UPF:set_retention mult_ret -domain PD_A -retention_power_net VDDB

-retention_ground_net VSS

map_retention_cell mult_ret -domain PD_A -lib_cell_type RSDFC

Support for Retention Registers with

Different Primary and Backup Powervoltage_map(VDD, 0.8);

voltage_map(TVDD, 0.6);

voltage_map(VSS, 0.00);

.

.

cell (RRFF) {

retention_cell : "RSDFC" ;

pg_pin(VDD) {

voltage_name : VDD;

pg_type : primary_power;

}

pg_pin (TVDD) {

voltage_name : TVDD;

pg_type : backup_power;

}

PD_B1.0V, OFF

RR

save

restore

AO

AO

AO

AOAO

AO

34

• Check if you have correctly specified the retention library cell or cell type to be used– In B-2008.09, map_retention_cell accepts only simple cell

names with the lib_cells option. For example:• map_retention_cell ret_strategy –domain PD_A -lib_cells

{SDRFFX1 SDRFFX2}

• map_retention_cell ret_strategy -domain PD_A -lib_cells

{SDRFF*}

– The target library, or target library subset, if specified, should have the specified library cells

– Ensure that they do not have a dont_use or dont_touch attribute

– Check that the specified cells are modeled correctly

Retention RegistersWhy Mapping Did Not Occur

35

• Check if the specified retention library cells correspond to the RTL

For example:

The above RTL requires a retention register with a reset.

If the target library does not have a retention register that satisfies this requirement, you will see the following TRANS-4 warning message during the compile_ultra command

Warning: Target library contains no replacement

for register 'S0/y_reg[0]' (**FFGEN**). (TRANS-4)

Retention RegistersWhy Mapping Did Not Occur

always @(posedge clk or posedge rst)

if(rst == 1) y <= 1'b0;

else if(ena && enb) y <= data;

36

Reporting & Querying Commands

UPF Construct Reporting Command Querying Command

create_power_domain report_power_domain get_power_domains

create_supply_port report_supply_port get_supply_ports

create_supply_net report_supply_net get_supply_nets

create_power_switch report_power_switch get_power_switches

37

Special Cell Reporting Commands

UPF Construct Reporting Command

set_level_shifter report_level_shifter

set_isolation

set_isolation_control

report_isolation_cell

set_retention

set_retention_control

map_retention_cell

report_retention_cell

38

Multivoltage Methodology With

IEEE P1801 (UPF) Checklist

• Requirements for implementing UPF designs in Design Compiler

UPF file to describe power intent

Libraries for Implementation

Power management cells are properly modeled

Rich set of power management cells Power management cells have the appropriate enable

Always-on buffers and inverters

Level shifters that can exist on either side of the power domain boundary

Characterization data for each voltage, for which the design will be optimized

39

Agenda


Implementation using Design Compiler



Design Planning


40

Input and Output to IC Compiler

Recommendation

Physical

Implementation

(IC Compiler)

Netlist + UPF

(Design Compiler)

Netlist + UPF

PG Netlist

Input to IC Compiler• Synthesized netlist with

UPF

– Binary format

– ASCII format

Output from IC Compiler• Netlist with UPF

• Fully realized netlist with power and ground connections

41

Agenda


Design Planning

• Voltage Area Creation

• Switch Cell Insertion and Sleep Net Synthesis

• Power Network Synthesis


• Multivoltage Aware Placement & Optimization

• Power and ground (PG) Connection

• Chipfinishing

• Netlist Editing and ECO

• Checking and reporting

• Multivoltage Checklist

42

Agenda

IEE P1801 (UPF) Methodology Overview In IC Compiler

Design Planning





• Multivoltage Aware Placement and Optimization

• Power and ground (PG) Connection

• Chipfinishing

• Netlist Editing or ECO



43

IEEE P1801 (UPF) Methodology in IC Compilercheck_mv_design

Power and

Ground

network

connection

through out

the flow

Netlist for Sign-Off

route_opt

chip finishing

Read the Design

clock_opt

place_opt

Design Planning

44

Agenda


Design Planning






• Power and Ground (PG) Connection

• Chipfinishing




45

Design PlanningVoltage Area Creation

• Map voltage area

to power domain

defined in UPF

– Rectilinear shapes

are allowed

create_voltage_area

MY_VA

-power_domain PD1

-coordinate ...

UPF Construct To Create Power Domaincreate_power_domain PD1...

46

Design PlanningSwitch Cell Insertion

create_power_switch_array

-lib_cell “MY_SW"

-voltage_area MY_VA

-x_increment ..

-y_increment ..

• Insert switches (header or footer) in floorplan

– -lib_cell option accepts mapped power switch

UPF Constructs For Power Switch

create_power_switch MY_SW

–domain ...

map_power_switch –domain ..

-lib_cell ... <MY_SW>

47

Design PlanningSleep Net Synthesis (1/3)

Daisy Chain Mode

connect_power_switch

-source SLEEP –mode daisy

–direction ..

-port_name ...

-voltage_area ....

48

Design PlanningSleep Net Synthesis (2/3)

connect_power_switch –source..

-port_name.. -mode daisy

–direction ...-voltage_area ..

-lib_pin [list \

<lib>/<cell>/sleepin1 \

<lib>/<cell>/sleepout1] ..

connect_power_switch –source..

-port_name.. -mode daisy

–direction ...-voltage_area ..

-lib_pin [list \

<lib>/<cell>/sleepin2 \

<lib>/<cell>/sleepout2] ...

Dual Input Daisy

Chain Connection

sleepout1Sleepin1

Sleepin2 sleepout2

49

Design Planning

Sleep Net Synthesis (3/3)

High Fanout Mode

connect_power_switch

–source SLEEP -port_name..

–mode hfn -voltage_area ..

50

Power Network Synthesis For

Multiple Voltage Areas

• Setup mesh constraints for each voltage area

• In one pass, power network synthesis creates all meshes to meet target voltage drop requirement

• Power network synthesis for power switch array

• Commit power mesh to floorplan

set_fp_rail_voltage_area_constraints

-voltage_area -nets –layer –global

–ring_nets

synthesize_fp_rail

-synthesize_voltage_area -power_budget

synthesize_fp_rail

-synthesize_power_switch_array

-power_budget

commit_fp_rail

51

Power Network Synthesis Constraints

Application For Multiple Voltage Areas

?

Select a voltage area

Specify synthesis constraints

Specify layer, ring, and global

constraints

Run power network synthesis

Analyze results

Commit power routes

OK?

yes

no

All Voltage Area synthesizedyes

TCL Commands: synthesize_fp_rail; commit_fp_rail

52

Power Network Synthesis GUI

53

Synthesis Constraints

a

b

c

d

e

a. Power and ground

net name

b. Voltage value

c. Power budget

(optional)

d. Target IR drop

e. Set the constraint

54

Voltage Area Layer Constraints

a

b

c

d

e

a. Layer and

direction

b. Number of straps

range or pitch

range

c. Strap width range

d. PG spacing


55

Ring and Strap Constraints

a. Specify if core ring

for DEFAULT_VA

should be generated

b. Nets and Layers to

use

c. Width, Offset, and

Spacing

d. Strap extension

control


a

b

c

d

e

56

Voltage Area Global Constraints

a

b

d

c

a. Choose a

voltage area

b. Select

global

constraints

c. Specify

individual

constraints

d. Set the

constraintssynthesize_fp_rail

-synthesize_voltage_area -power_budget

Commit_fp_rail

57

Agenda


Design Planning






• Power and Ground (PG) Connection

• Chipfinishing

• Netlist Editing or ECO



58

• Adaptive Leakage Optimization

• Concurrent Multicorner-

Multimode Optimization

• Hierarchical Methodology

• Timing-SI-Fixing

• Clock Tree Synthesis &

Optimization

• Routing

• Power and ground pin connection

based on UPF

• Secondary power pin routing of

special cells

IC Compiler Physical ImplementationAll Features and Methodologies are Supported with UPF

ICC

Concurrent

OptimizationYield

Opt Signoff

Driven

XPS

PhysicalPower

DesignPlanning

Milkyway

Tcl

PhysicalDFT

GUI

59

Multivoltage Aware Placement

• Placement respects

voltage area boundary

• Special level shifter and

isolation cell placement

– Special cells placed

closer to voltage area

boundary

• Voltage area-aware

physical scan reordering

• High fanout net synthesis

• Routing estimation detours

around voltage area

Isolation cells

place_opt

Lever shifter

60

Multivoltage Aware Optimization

• Automatic High Fanout Net Synthesis

• Automatic Always-On Synthesis

– Always-on inference based on UPF

– Dual power (default) and single power always-on

strategy supported

– User defined always-on attribute based synthesis

61

Always-on Synthesis Definition

• Control signals for

power management

cells need to be live

while the logic around

are shut down

– Optimizing such

control signals with

special cells having

secondary power

(backup power) is

always-on synthesis

PD_A 0.8V

PD_B 0.8V, OFF

RR

save

restore

ao

ao

ao

ao

62

Always-on inference

• Automatic always-on inference

– Enable pins of enable level shifter

and isoaltion cells; save and

restore pins of retention registers

and control pin of switch cells are

automatically treated as always-

on anchor points

– Always-on marking is done by

tracing back from always on pins

• Control signals of special

cells such as isolation cells,

retention registers, enable

level shifters and switches are

treated as always-on nets

• Always-on inference based on user

defined attributes

– Pins that have been marked as always-on by the user using the set_attribute

command

set_attribute my_cell/a

always_on true

– Always-on tracing stops at a multi input

cell

– Traces through buffers and inverters only

PD_B

PD_A 0.8V

PD_B 0.8V, OFF

RR

save

restore

ao

ao

ao

ao

63

Power and Ground (PG) Connection

• PG network connection with derive_pg_connection

• PG pins of standard cells hooked up to PG nets

• Use -create_net/-reconnect options after linking

•–all option completes incremental tie and PG connections

• Always-on cells are hooked up to correct PG net

• Check for any PG connection violations

derive_pg_connection

check_mv_design –power_nets

64

Chip Finishing

• Chipfinishing commands recognize supply nets

in UPF

– insert_stdcell_filler

– add_tap_cell_array

– insert_tap_cell_by_rule

• PG connections for physical only cells using derive_pg_connection command:

• derive_pg_connection -power_net VDDVA

-power_pin VDDC –cells ...

65

Netlist Editing and ECO Commands

• To connect or disconnect signal, power, and tie netsconnect_net <net> <object_list>

disconnect_net <net> <object_list>

• To create new hierarchical power and ground network, update and report existing power and ground network create_pg_network...

remove_pg_network ...

• Multivoltage aware ECO capability in eco_netlist– Use the -by_verilog_file option to specify verilog ECO file

– Use the –compare_pg option to perform ECO changes on PG ports and nets

– Use the –physical option to perform ECO changes on physical only cells

66

Mulitvoltage Checking Commands

check_mv_design

After each major step in the flow run these checks:

• Power domain and voltage area checking

• Power pin and connection checking

• Always-on synthesis checking

• Special cell checking

check_mv_design \

-power_nets \

-connection_rules \

-level_shifters \

-isolation ....

67

Multivoltage Checking Command check_physical_design

• Checks the design readiness for IC Compiler

• The –stage pre_place_opt option checks and analyzes multivoltage design constraints and setup

check_physical_design –stage pre_place_opt

68

Reporting & Querying Commands

UPF Construct Reporting Command Querying Command

create_power_domain report_power_domain get_power_domains

create_supply_port report_supply_port get_supply_ports

create_supply_net report_supply_net get_supply_nets


69

Special Cell Reporting Commands

UPF Construct Reporting Command

set_level_shifter report_level_shifter

set_isolation

set_isolation_control

report_isolation_cell

set_retention

set_retention_control

map_retention_cell

report_retention_cell

70

Power Switch

IC Compiler Query & Report Log

icc_shell>report_power_switch******************************Report : Power Switch******************************Power switch name: new_swCurrent Scope: BLK1Power domain: DOMAIN1Lib Cell Name: sw_lib1/hdr1 Input port net: {in VDD}Output port net: {out VDDI}

icc_shell> get_power_switches{new_sw }

UPF constructs Reporting Command Querying Command


71

IEEE P1801 (UPF) Browser

• GUI equivalent for all IEEE P1801 (UPF) constructs

• Easy to analyze & report power domain contents – Supply nets

– Supply ports and so on

• Enables debugging and analyzing design in layout window

72

Agenda


Design Planning






• Power and Ground Connection

• Chipfinishing




73

Multivoltage Methodology With IEEE P1801

(UPF) Checklist (1/5)

• Requirements for implementing UPF designs in Design Compiler

UPF file to describe power intent

Libraries for Implementation

Power management cells are properly modeled

Rich set of power management cells Power management cells have the appropriate enable

Always-on buffers and inverters

Level shifters that can exist on either side of the power domain boundary

Characterization data for each voltage for which the design will be optimized

74

MV Methodology With IEEE P1801 (UPF) Checklist (2/5)

• Requirements for implementing UPF designs in IC Compiler

Bring in design and UPF from Design Compiler to IC Compiler via binary or ASCII format Isolation cells and retention registers must be inserted

in Design Compiler Run the check_mv_design –verbose command

with relevant options to ensure special cell insertion is complete

If floorplan is read via DEF PG port names in DEF and UPF must be consistent run derive_pg_connection after reading in DEF

Command map_power_switch should be applied for all created power switches

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Use the set_operating_condition for top-level and use the set_voltage for all supplies of design Top level operating conditions

set_operating_condition <opcond_name>

Current operating voltage of supply netsset_voltage <floating_point_value>

-object_list <supply_nets>

Run check_mv_design –verbose throughout the flow

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Ensure placement and legalization steps are

done before clock tree synthesis and routing

Run check_legality to ensure placement is legal

Run legalize_placement to fix any illegal

placement

77



Secondary Power Pin Routing

– Use preroute_standard_cell –nets for

special cells

– Use signal router to route secondary power pins of

always-on cells inserted during optimization and clock

tree synthesis

To write PG netlist of a design with UPF loaded

into IC Compiler use

write_verilog –pg outputfilename.v

78

UPF

RTL

PG

Netlist PrimeRail

Formality

Ref

Impl

Formality

Ref

Impl

Synopsys IEEE P1801 (UPF) Flow

PrimeTime

PrimeTime PX

UPF”

Gate

IC Compiler

VCS+MVSIM

MVRC

PrimeTime

PrimeTime PX

UPF’

Gate

Formality

Ref

Impl

Design Compiler

Power CompilerVCS+MVSIM

MVRC

79


(UPF)Summary

• IEEE P1801 (UPF) commands supported

• Power and ground network connection based

on UPF

• Automatic always-on inference and synthesis

throughout the flow

• Fully realized netlist with power and ground

information + UPF from IC Compiler for

verification and sign-off analysis

80

Appendix

81

##open design ddcread_ddc design.ddclink

check_mv_design –verbose

## power and ground connectionsderive_pg_connection –create_net/reconnect

## floorplan stepsread_io_constraints design.iosinitalize_floorplancreate_voltage_area –power_domain PD1 –guard_band_x 1

–guard_band_y 1check_mv_design –verbose

A Sample IC Compiler Script For

IEEE P1801 (UPF) Methodology (1/3)

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## Switch cell mapping and insertionmap_power_switch –domain top –lib_cell HDRS1<name_of_switch> create_power_switch_array –lib_cell \“name_of_switch”-orientation N =x 4.2 –y 3.6 –prefix “inst_header”

##Connect switch cells in daisy/hfn modeconnect_power_switch –source inst_on –port_name on –mode hfn –verbose

##Power network synthesis and secondary power pin routing steps

create_fp_virtual_pad -net VDD108 -layer ME2...

set_fp_rail_voltage_area_constraints -voltage_area ...

synthesize_fp_rail -synthesize_voltage_areas -voltage_area ....

commit_fp_rail

report_fp_rail_voltage_area_constraints –all

preroute_standard_cells -mode net-net VDDG -h_layer M5

-v_layer M6 -h_width 0.38 -v_width 0.3



83

##Implementation stepsplace_optclock_optroute_opt

derive_pg_connection –all

##Chip finishinginsert_stdcell_filler –cell_without_metal......check_mv_design

## Write results outsave_upf out2.upfwrite_verilog –pg out.v (pg netlist)



tutorial upf 026261

Documents

design compilerdesign

release of design compiler

power management cells

power intentload

secondary power

isolation cells

shutdown domains pd

control pin of switch