UPF-Based Power-Aware

Design Flow

Version 1.1

Stephen BaileyChair, UPF Working Group

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Agenda

UPF-Based PA Design Flow— System-level power specification— Reusable IP block power specification— RTL power design— Implementation flow— Gate-level power verification

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System Power View of Interleaver

Simple power architecture

Simple for education purposes

Power domains:— PD_fifo => PD_tx

PD_pktcnt =>PD_rx

TestBench

interleaver

in2wire

pktcntr FIFO

out2wire

RAM

Logic HierarchyView PD_Interleaver

Power Domain View

PD_rx

in2wire pktcntr

PD_tx

out2wire

fifo

ramPD_tx

PD_rx

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Defining the System Power StatesPD_tx_vdd PD_tx_vss PD_rx_vdd PD_rx_vss

Duplex On On On On

Transmit On On Off On

Receive Off On On On

Sleep Off On Off On

State

PDSupply

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Interleaver Power State SpecificationPD_tx_vdd PD_tx_vss PD_rx_vdd PD_rx_vss

Duplex On On On On

Transmit On On Off On

Receive Off On On On

Sleep Off On Off On

create_pst \interleaver_pst PD_tx_vdd vss PD_rx_vdd vss

add_pst_state Duplex PD_tx_vddon vsson PD_rx_vddon vsson

add_pst_state Transmit PD_tx_vddon vsson PD_rx_vddoff vsson

add_pst_state Receive PD_tx_vddoff vsson PD_rx_vddon vsson

add_pst_state Sleep PD_tx_vddoff vsson PD_rx_vddoff vsson

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What’s Wrong/Missing So Far?

1. We haven’t defined any power domains yet— Easy to do without over-specifying at this level:

2. No supply states defined anywhere yet— We discussed using placeholders

3. Incomplete nature of the power state specification— No transitions specified

No syntax for it, yet— No references to logic net states

Easy enough to add

set_scope .create_power_domain PD_interleaver –include_scopecreate_power_domain PD_rx –elements {in2wire pkt_counter}create_power_domain PD_tx –elements {out2wire fifo}# NOTE: -elements can be incomplete; but can’t have 3 PDs all with current scope as the default elements list

create_pst \interleaver_pst use_pp(PD_tx) use_pg(PD_tx) use_pp(PD_rx) use_pg(PD_rx)

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Agenda

UPF-Based PA Design Flow— System-level power specification— Reusable IP block power specification— RTL power design— Implementation flow— Gate-level power verification

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Reusable IP Power SpecificationInterleaver Contains Reusable IP Block

In2wire and out2wire blocks are instances of the same module

Rdyacpt is the reusable IP moduleTestBench

interleaver

in2wire

pktcntr FIFO

out2wire

RAM

Logic HierarchyView

rdyacpt #(8) in2wire ( .upstream_rdy(di_rdy), .upstream_acpt(di_acpt), .upstream_data(di_data), .downstream_rdy(in_rdy), .downstream_acpt(in_acpt), .downstream_data(input_down_data), .reset_n(reset_n), .clk(clk) );

rdyacpt #(8) out2wire ( .upstream_rdy(out_rdy), .upstream_acpt(out_acpt), .upstream_data(do_reg), .downstream_rdy(do_rdy), .downstream_acpt(do_acpt), .downstream_data(do_data), .reset_n(reset_n), .clk(clk) );

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What to Specify for IP to Keep RTL & UPF Reusable

Only specify how IP is used in a low power context Finest granularity of power domains for the IP What state must be saved on power down; restored

on power up Safe isolation values for inputs to the IP

— For when the source domain for those inputs is powered down while the IP is up and running

Any required isolation output values for the IP

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Finest Granularity of Power Domains

Sets of logic that can be shutdown or run at different voltage levels inside the domain

For rdyacpt:— Simple logic all on at same time and all operating at

same voltage level— Could specify no power domain and let it be

subsumed into the parent instance’s power domain— But, that would not allow us to specify isolation and

retention strategies— Therefore, create one power domain to allow

specification of IP’s retention and isolation strategies

# Assumes the caller of the UPF file containing this sets the scope# to the rdyacpt instance (in2wire or out2wire)create_power_domain pd_rdyacpt –include_scope

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Specify IP State Requiring Retention

rdyacpt requires state of all registers to be retention registers— Likely scenario for most IP blocks— If register values aren’t saved, they need to be reset on

power up

set_retention rdyacpt_ret –domain pd_rdyacpt

# Default is strategy applies to all elements of the domain# Defer retention logic and implementation specifics to IP# integrator

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Specify Safe Isolation Values for IP

For inputs:— Safe values when the source domain is shutdown and

the IP’s domain is on For outputs:

— Safe values for outputs (inactive) where relevant— Otherwise defer to sink domain to define

RTL code:always @(posedge clk or negedge reset_n) …

set_isolation rdyacpt_clk_iso –domain pd_rdyacpt -elements {clk} -clamp_value 0set_isolation rdyacpt_rst_iso –domain pd_rdyacpt -elements {reset_n} -clamp_value 1

# Other inputs do not trigger activity; no iso required for other inputs

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IP Integrator Will:

Create the supply nets – primary, retention and isolation required

Refine the power domain, retention and isolation strategies to specify the appropriate supplies

Add any implementation details required— Map retention cells— Add level shifting strategies

Alternative IP power specification strategy:— Create supply ports and local supply nets for all supplies— Reference those supplies in the IP’s UPF— Pros: Hide more information internal to IP— Cons: If IP will not be power gated, extra work not used

May confuse implementation tool; creating unneeded objects

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What’s Wrong/Missing for Reusable UPF for IP Blocks?

Can already get a sense of how important merge_power_domains will be for IP reuse when the IP comes with reusable UPF specification

Isolation is specified in the example— What if the ports for which an isolation strategy is specified are

not ports on the PD’s interface?— They are as initially specified— After merging, they may not be— merge_power_domains needs to address this semantic issue – we

don’t want isolation where it isn’t needed Retention is specified in the example

— If the IP cannot be power gated (is always on), then the retention strategy must be ignored

— Same could be true for isolation (depending on what is being isolated)

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Agenda

UPF-Based PA Design Flow— System-level power specification— Reusable IP block power specification— RTL power design— Implementation flow— Gate-level power verification

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Quick Review

We have already defined:— The system power states

In terms of supply port states

— Defined the IP low power design requirements

Before we can do an RTL power aware simulation:— Need to define chip power domains— Chip supply network— Chip retention and isolation strategies

In sufficient detail that the simulator can simulate behavior

— May define level shifting strategies Required before synthesis May defer to later RTL sign-off verification stage

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Chip Power Domain Definition

Power domains:— PD_Interleaver— PD_tx— PD_rx

PD_Interleaver

Power Domain View

PD_rx

in2wire pktcntr

PD_tx

out2wire

fifo

ram

set_scope .create_power_domain PD_Interleaver -include_scopecreate_power_domain PD_rx -elements {in2wire pkt_counter}create_power_domain PD_tx -elements {out2wire fifo}

NOTE: Most likely the PDs will be already createdas indicated earlier. However, as the RTL implementa-tion is refined, there will be a need to refine (additively) a domain’s elements

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Create the Supply Network

Common ground for chip Switched VDD for PD_rx and PD_tx Retention & isolation supplies

PD_Interleaver

PD_rx

in2wire pktcntr

PD_tx

out2wire

fifo

ram

create_supply_port vss_pad –direction increate_supply_port vdd_pad –direction increate_supply_net vssconnect_supply_net vss –ports {vss_pad}create_supply_net vddconnect_supply_net vdd –ports {vdd_pad}create_supply_net PD_rx_vddcreate_supply_net PD_tx_vdd

vdd_pad

vss_pad

NOTE: Feedback from Minh is that RTL designersshould not need to specify the supply network.This is too early in the flow for most. But, it is currently required now to simulate.Placeholder supply refs with predefined “logic” states of on/off/partial/don’t care.

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Create the Power Switches for the Chip

Switch PD_rx primary supply Switch PD_tx primary supply

create_power_switch rx_prim_pwr -output_supply_port {rx_vdd_out PD_rx_vdd} -input_supply_port {rx_vdd_in vdd} -control_port {rx_en rx_iso_en} -on_state {PD_rx_vddon rx_vdd_in {~rx_iso_en}}

create_power_switch tx_prim_pwr -output_supply_port {tx_vdd_out PD_tx_vdd} -input_supply_port {tx_vdd_in vdd} -control_port {tx_en tx_iso_en} -on_state {PD_tx_vddon tx_vdd_in {~tx_iso_en}}

PD_Interleaver

PD_rx

in2wire pktcntr

PD_tx

out2wire

fifo

ram

vdd_pad

vss_pad

rx_iso_en

tx_iso_en

NOTE: To continue with Minh’s objection of over-specifying too early, switch creation can be optional.If PSTs can reference logic signal states, then that can be the “check” for a supplystate.

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Relate the Supplies to the Domains

Switch PD_rx primary supply Switch PD_tx primary supply

create_power_domain PD_Interleaver -primary_power_net vdd -primary_ground_net vsscreate_power_domain PD_rx -primary_power_net PD_rx_vdd -primary_ground_net vss -default_iso_power_net vdd -default_ret_power_net vddcreate_power_domain PD_tx -primary_power_net PD_tx_vdd -primary_ground_net vss -default_iso_power_net vdd -default_ret_power_net vdd

PD_Interleaver

PD_rx

in2wire pktcntr

PD_tx

out2wire

fifo

ram

vdd_pad

vss_pad

rx_iso_en

tx_iso_en

NOTE: If supply nets do not yet exist, this stepwould not occur at this point in time.

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Logic Control of Isolation & Retention

Logic control signals that enable isolation for PD_rx and PD_tx

Logic control signals for save/restore of retention registers for both domains

set_retention PD_rx_ret –domain PD_rx -save_signal {rx_sleep posedge} -restore_signal {rx_sleep negedge}set_isolation PD_rx_iso –domain PD_rx -isolation_signal {rx_iso_en posedge}

set_retention PD_tx_ret –domain PD_tx -save_signal {tx_sleep posedge} -restore_signal {tx_sleep negedge}set_isolation PD_tx_iso –domain PD_tx -isolation_signal {tx_iso_en posedge}

PD_Interleaver

PD_rx

in2wire pktcntr

PD_tx

out2wire

fifo

ram

vdd_pad

vss_pad

rx_iso_en

tx_iso_en

rx_sleep

tx_sleep

NOTE: Part of “logic configuration” step. So, wouldbe required prior to RTL simulation.

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Don’t Forget Logic Configuration of IP Block! Both instances of rdyacpt’s domains require supply

associations Should be accomplished by merging power domains

— If we were confident in the completeness and quality of the semantics

set_scope in2wireload_upf rdyacpt.upfcreate_power_domain PD_rdyacpt -primary_power_net .PD_rx_vdd -primary_ground_net .vss -default_iso_power_net .vdd -default_ret_power_net .vddset_scope .out2wireload_upf rdyacpt.upfcreate_power_domain PD_rdyacpt -primary_power_net .PD_tx_vdd -primary_ground_net .vss -default_iso_power_net .vdd -default_ret_power_net .vdd

NOTE: This slide and the nextdemonstrate how important themerge_power_domain commandis.For this specific example, we would want the in2wire and out2wire instances to simply be subsumed into its parent’s power domain and all the logic configuration and implementation.But, without merge_power_domain, the work required is significantly more.

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IP Block Retention & Isolation Logic Configuration

Specify the logic control signals for isolation and retention of both instances of rdyacpt

set_scope .in2wireset_retention rdyacpt_ret –domain pd_rdyacpt -save_signal {rx_sleep posedge} -restore_signal {rx_sleep negedge}set_isolation rdyacpt_clk_iso –domain pd_rdyacpt -isolation_signal {rx_iso_en posedge}set_isolation rdyact_rst_iso –domain pd_rdyacpt -isolation_signal {rx_iso_en posedge}

set_scope .out2wireset_retention rdyacpt_ret –domain pd_rdyacpt -save_signal {tx_sleep posedge} -restore_signal {tx_sleep negedge}set_isolation rdyacpt_clk_iso –domain pd_rdyacpt -isolation_signal {tx_iso_en posedge}set_isolation rdyact_rst_iso –domain pd_rdyacpt -isolation_signal {tx_iso_en posedge}

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Do We Have Enough for RTL Simulation?

Yes But

— Retention functionality is generic— If you know your implementation technology

Then you should map to a retention simulation model Ensure accurate verification of save & restore protocols Relative to other register control signals

— We still need to work on the retention specification Synthesizable & LEC friendly? Or always a mapping to specificy technology cells?

Example:map_retention_cell PD_rx_ret –domain PD_rx -lib_model_name CFRFF

# Note: Questa does not require the port map specified by UPF# as Questa knows which signals to connect to the ports

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Do We Have Enough for RTL Simulation?

Yes But

— Could specify level shifting strategies— If multi-voltages employed and operating voltages are

specified this early

Example:set_level_shifter PD_rx_lss –domain PD_rx -threshold 0.2 -applies_to inputs -rule low_to_high

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Agenda

UPF-Based PA Design Flow— System-level power specification— Reusable IP block power specification— RTL power design— Implementation flow— Gate-level power verification

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Implementation Flow

Need the implementation folks to fill in this section

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Agenda

UPF-Based PA Design Flow— System-level power specification— Reusable IP block power specification— RTL power design— Implementation flow— Gate-level power verification

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Gate Level VerificationDefer after Implementation Flow Complete

Simulation: 2 options— Fully P/G connected gate-level netlist

Unlikely or at minimum rare in near term No UPF required as gate models are power-aware & supply

network is fully modeled

— Implementation tool(s) will generate UPF file(s) that correspond to the generated gate netlist

— Run simulations as you would for RTL power-aware verification Logic & Power Equivalency Checking

— Ensure what was verified at RTL has been equivalently implemented

— Mentor’s FormalPro performs LEC with power-aware features for PCF and, coming soon, UPF

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Voltage (threshold) ScalingInclude in example or separate example

Ain changes corrupt through inverter chain Cin & Bin changes corrupt through AND output

— If CK gated, corruption does not propagate further Din changes do not corrupt Din->Q as long as CK is

gated If CK not gated, CK changes result in FF & Q

corruption

At “normal” power— Switching with

determinate performance

With reverse biasing (raised Vth)— Switching occurs with

unknown performance— Corruption simulates

results of unknown performance

Vth Scaled Power DomainD

Q

D

Q

VDD VSS N-Well P-Well

CKEN

Ain

BinCin

Din