UNIVERSITI TEKNOLOGI MARA

MEMRISTOR SWITCHING MODEL FOR DIGITAL AND ANALOG

CIRCUITS

SITI MUSLIHA AJMAL BINTI MOKHTAR

Thesis submitted in fulfillment of the requirements for the degree of

Master of Science

Faculty of Electrical Engineering

April 2016

CONFIRMATION BY PANEL OF EXAMINERS

I certify that a Panel of Examiners has met on 13 January 2016 to conduct the final examination of Siti Musliha Ajmal Binti Mokhtar on her Master of Science thesis entitled "Memristor Switching Model for Digital and Analog Circuits" in accordance with Universiti Teknologi MARA Act 1976 (Akta 173). The Panel of Examiners recommends that the student be awarded the relevant degree. The panel of Examiners was as follows:

Muhammad Murtadha Othman, PhD Associate Professor Faculty of Electrical Engineering Universiti Teknologi MARA (Chairman)

Rosalena Irma Alip, PhD Senior Lecturer Faculty of Electrical Engineering Universiti Teknologi MARA (Internal Examiner)

Nasri Sulaiman, PhD Senior Lecturer Department of Electrical & Electronic Engineering Universiti Putra Malaysia (External Examiner)

SITI HALIJJAH SHARIFF, PhD Associate Professor Dean Institute of Graduates Studies Universiti Teknologi MARA Date: 18th April, 2016

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AUTHOR'S DECLARATION

I declare that the work in this thesis was carried out in accordance with the regulations

of Universiti Teknologi MARA. It is original and is the results of my own work unless

otherwise indicated or acknowledged as referenced work. This thesis has not been

submitted to any other academic institution or non-academic institution for any degree

or qualification.

I, hereby, acknowledge that I have been supplied with the Academic Rules and

Regulations for Post Graduate, Universiti Teknologi MARA, regulating the conduct of

my study and research.

Name of Student : Siti Musliha Ajmal Binti Mokhtar

Student I.D No. : 2012193775

Programme : Master of Science (Electrical Engineering) -

EE750

Faculty : Electrical Engineering

Thesis Title : Memristor Switching Model for Digital and

Analog Circuits

Signature of Student : /\if.

Date April 2016

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ABSTRACT

Scaling of complementary-metal-oxide-semiconductor (CMOS) transistor for higher performance device is nearly reaching its limit due to technology limitation issues. In this research, main objective is to incorporate a nanodevice called memristor into CMOS circuit as one alternative to overcome scaling limitation due to memristor fabrication is compatible with CMOS. The first requirement in this research is to develop SPICE model for memristor in circuit simulation. Research starts with model selection and validation through comparison with fabricated memristor sample followed by model development in LTSPICE. In this research, memristor applications are investigated from both digital and analog memristor resistance switching. For digital, memristor-based logic modules are invested. For analog, a novel design of programmable delay element (PDE) using memristor is proposed. A case study of implementing the proposed PDE in delay locked loop (DLL) is also discussed. For model development, OSM model is validated and has most comparable behavior with sample. Next, hybrid memristor-based logic gates (AND, NAND, OR, NOR) designs and operation results are discussed. They showed similar operation with CMOS logic. Hybrid XOR shows 88% less area consumption compared to fully CMOS XOR thus supports the main objective. However, hybrid logics have dynamic behavior at output caused by slow memristor switching speed. Speed can be increased through thinner thin film and higher voltage supply. Finally, the proposed PDE showed delays that are programmed by adjusting memristor resistance. Case study of DLL proved proposed design functionality in more complex system. However, it consumes more area than CMOS DLL.

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TABLE OF CONTENTS

CONFIRMATION BY PANEL OF EXAMINERS

AUTHOR'S DECLARATION

ABSTRACT

ACKNOWLEDGEMENT

TABLE OF CONTENTS

LIST OF TABLES

LIST OF FIGURES

LIST OF SYMBOLS

LIST OF ABBREVIATIONS

CHAPTER ONE: INTRODUCTION

1.1 Research Background

1.2 Problem Statement

1.3 Research Objectives

1.4 Research Scope

1.5 Structure of Thesis

CHAPTER TWO: LITERATURE REVIEW

2.1 Introduction

2.2 Theory: Memristor Fundamentals

2.2.1 Memristor Properties

2.2.2 Current-Voltage Behaviour in Memristive Devices

2.3. Literature Review: Memristor Discovery and Development

2.3.1 Alternatives Approaches For Scaling Limitation

2.3.2 First Physical Memristor

2.3.3 Development of Memristor Models

2.3.3.1 Models Using Linear Resistive Theory

2.3.3.2 Models Using Tunnelling Resistive Theory

2.4 Literature Review: Memristor Applications

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