use of robust predictive method for nano-cmos process: application to basic block analog circuit...
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USE OF ROBUST PREDICTIVE METHOD FOR NANO-CMOS
PROCESS. APPLICATION TO BASIC BLOCK ANALOG
CIRCUIT DESIGN¤
HOUDA DAOUD†, SAMIR BENSELEM‡, SONIA ZOUARI§
and MOURAD LOULOU¶
University of Sfax, Tunisia,
National Engineering School of Sfax,
Information Technologies and Electronics Laboratory,BP W 3038 Sfax, Tunisia†[email protected]
‡[email protected]§[email protected]
Received 8 June 2011Accepted 18 May 2012
Published 21 December 2012
This paper deals with the prediction of primary parameters of CMOS transistor for upcoming
process using the robust Bisquare Weights method which is able to provide solutions to thechallenges of some parameters of Nanoscale CMOS. Predicted parameters for 45 nm to 22 nm
process nodes are obtained in order to solve design challenges generated by Nanoscale process.
These predicted primary parameters are helpful to estimate the performance of a basic element
circuit having a key role in the design of upcoming analog systems. Comparisons betweenpredictive technology model data and predicted parameters are used to check the validity of the
used method. As a study case, we will detail the behavior of optimized telescopic operational
transconductance ampli¯er performance with process scaling.
Keywords: Process scaling; least squares; bisquare weights; predictive primary parameters;
predicted and optimized OTA performance.
1. Introduction
Mobile Telecommunication has experienced tremendous development since the
progressive growth of wireless communication systems. In order to reach higher data
rates and permit the introduction of new services, the standards for wireless com-
munication systems have been widely developed. The incessant growth of wireless
mobile systems continuously causes new challenges that consist of the development
*This paper was recommended by Regional Editor Piero Malcovati.†Corresponding author.
Journal of Circuits, Systems, and ComputersVol. 21, No. 7 (2012) 1250061 (22 pages)
#.c World Scienti¯c Publishing Company
DOI: 10.1142/S0218126612500612
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of new architectures and circuit techniques. Since CMOS is the preferred process for
integrating systems on a chip, designers make enormous e®orts to implement new
systems with the new emerging CMOS process.1 The number of transistors on chips
has grown at a faster rate in recent years.2 Moore's law is the fundamental guideline
for the semiconductor industry with respect to the features of the future generations.
The international technology roadmap for semiconductors (ITRS) is based on
Moore's rule, describing the technical challenges and the requirements that the
semiconductor industry will face over the next 15 years.3 Device engineers and circuit
designers devote their e®orts to Nanometer design ¯eld. More than 100 parameters
are available in a modern transistor model, but only 10 are crucial to identify the
main behavior of a MOSFET throughout scaling. An initial e®ort in this issue was
Berkeley predictive technology model (BPTM). It uses the published values (Leff ,
Tox, Vth, Rdsw and Vdd), then computes the process and physical parameters (Nch,
Esat, K , �0 and Vsat) and ¯nally generates the corresponding predictive technology
model (PTM) model ¯les for 130 to 32 nm process nodes.4 This strategy was suc-
cessfully checked and has proved its e±ciency.5 Moreover, the metal oxide semi-
conductor implementation service (MOSIS) provides access to a wide variety of
semiconductor process for di®erent process nodes o®ered by several foundries: IBM,
TSMC, AustriaMicroSystems (AMS), ON SEMIconductor, Globalfoundries, Tez-
zaron and Peregrine.6 The main objective of this work was to evaluate the capacities
of analog basic blocks when designed using future upcoming Nano-CMOS process. In
fact, upcoming generations of communication systems require high performance and
features di±cult to reach using available process. So, predicting the potentialities of
future nanoprocess to improve the performance of commonly used analog blocks and
how they broaden the spectrum of their use is considered as a primary objective of
analog designers. In this context, we focused on the use of the operational trans-
conductance ampli¯er (OTA) to design high speed data converters for wideband
wireless systems, and estimated the telescopic OTA performance with process scal-
ing. This paper presents the development of a robust method that provides the
prediction of primary parameters of CMOS device for future process. Thus, the
predictive Nano-CMOS performance of telescopic OTA is ful¯lled. The remaining of
this paper is organized as follows: Bisquare Weights (BW) method is presented in
Sec. 2. Section 3 details the procedure of predictive CMOS device parameters for
45 nm to 22 nm process nodes. The predicted performance of telescopic OTA for
future process and the impact of the CMOS scaling-down to OTA design are de-
scribed in Sec. 4. Finally, the conclusion drawn from this work and possible future
works are presented.
2. Bisquare Weights Method
The adjustment problem of a set of points that are presented by a line or generally by
a curve is compulsory in statistic growth. Previously, hand calculation techniques
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were used for curve ¯tting. In fact, Roger Boscovich discovered a method for drawing
a line passing as close as possible to all points.7 However, the obtained results are
approximate and do not enable scientists to establish an accurate prediction. For
automated curve ¯tting, Leonhard Euler and Tobias Mayer developed the mean
method or Mayer's method which allows to adjust the points by a line.8 The most
commonly used technique is the least-squares method (LS). It is a standard approach
elaborated by Legendre and Gauss.9 It has broad applications in linear regression,
signal processing, statistics and curve ¯tting. This method aims to ¯nd a smooth
curve that ¯ts the data points, x1 . . .xn. Along with the appearance of normal dis-
tribution, the LS is still considered as the most accurate method of adjustment. In
order to ¯t a set of data, the LS method minimizes the sum of squared residuals and
processes data that has Gaussian-distributed noise.10 It is characterized by two
categories, linear and nonlinear. The graphic form usually remains the directive
choice of the nature of LS. In the linear LS method, we assume that the data points
are ðxi; yiÞ, where x is the independent variable, y is the dependent variable and
1 � i � n. The linear LS method assumes that the data set falls on a straight line
taking into account a linear combination of x and y parameters, yielding
fðxÞ ¼ axþ b. After giving (xi; yi) data points, the unknown coe±cients \a" and \b"
are consequently computed below:
a ¼ Covðx; yÞV ðxÞ where Covðx; yÞ ¼ 1
n
Xni¼1
ðxi � �xÞðyi � �yÞ and
V ðxÞ ¼ 1
n
Xni¼1
ðxi � �xÞ2 ; ð1Þ
b ¼ �y � a�x where �x ¼Pn
i¼1 xi
nand �y ¼
Pni¼1 yin
: ð2Þ
Cov(x; y) and V ðxÞ are respectively the covariance of x and y and the variance of x. If
x and y present a nonlinear combination, we use the nonlinear LS method, so we have
to choose the curve form. Nonlinear statistical mathematical models are expressed in
a wide variety of functions such as exponential, logarithmic, quadratic, cubic, etc.
We should make a variable change in order to obtain the linear function y ¼ axþ b
and reuse the linear LS method on (xi; yi) points.11 The disadvantages of the linear
LS method reside in the shapes that linear models can assume and its sensitivity to
outliers which do not follow the pattern of the other observations. This means that it
becomes di±cult to ¯nd a linear model that ¯ts the data, therefore, the extrapolation
of the process results is potentially poor when data cannot be collected in the region
of interest.12 From simpler modeling techniques like linear LS, nonlinear LS method
requires the use of iterative optimization procedures to compute the estimated
parameters and obtain accurate results. As in a linear LS analysis, one or two outliers
can seriously skew the results of a nonlinear analysis and result in large squared
errors. One e®ective solution to these problems is to use \robust LS" regression which
Use of Robust Method for Nano-CMOS Process
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is able to alleviate the in°uence of outliers by iteratively assigning small weights to
the outliers during the regression process.13 In fact, using MATLAB, Curve Fitting
Toolbox which is a graphical user interface (GUI), allows us to explore ¯ts as scatter
plots and access additional interfaces for di®erent tasks, in particular interpolating
and extrapolating ¯ts. A library of available linear and nonlinear regression models
can be used. All of these standard models contribute to improve the ¯t quality by
including optimized solver parameters and starting conditions. In this context, we
can specify our own regression model. The toolbox enables us to perform data ¯tting
and remove outliers through the choice of one of the two types of robust regression:
(BW) or least absolute residual (LAR). In most cases, the BW is preferred over the
LAR for the reason that it simultaneously looks for ¯tting the bulk of the data by a
curve using the known LS approach, and minimizes the e®ect of outliers. The BW
method uses an iteratively reweighted LS algorithm.10 In this algorithm, lower
weights are given to points that do not ¯t well while data points which belong to the
scatter acquire higher weights. When compared to ordinary LS method, the results
are less sensitive to outliers, hence, the BW method is more accurate and more
e±cient, yielding better predictions on the environmental performance. Nonlinear
models are more di±cult to ¯t than linear models. To solve di±cult nonlinear pro-
blems, the toolbox provides di®erent ¯tting algorithms where the Trust-region one is
the most used for a performed ¯t.14 To evaluate the accuracy of the curve ¯tting
results, the toolbox supports goodness of ¯t statistics for both linear and nonlinear
parametric ¯ts. In fact, we should examine these goodness of ¯t statistics including
the sum of squares due to error (SSE), the Root mean squared error (RMSE) and the
R-square. The SSE and RMSE show the di®erence between the data set and the
¯tted model. Both equations of the SSE and RMSE are given respectively by:
SSE ¼Xni¼1
wiðyi � y 0iÞ2 ; ð3Þ
RMSE ¼ffiffiffiffiffiffiffiffiffiffiffiMSE
pwhere MSE ¼ SSE
DOFð4Þ
yi, y0i, wi and DOF are, respectively the observed value in the scatter, the adjusted
value, the speci¯ed weights and the degree of freedom. SSE and RMSE values closer
to 0 indicate that the model has a smaller random error component and that the ¯t
will be more useful for prediction. The R-square is the square of the correlation
between the response values and the predicted response values. Given the de¯nitions
of SSE and SST, the R-square is expressed as:
R-square ¼ 1� SSE
SSTwhere SST ¼
Xni¼1
wiðyi � �yiÞ2 : ð5Þ
A high R-square close to 1 means a better ¯t between the ¯tting model and the data
set. Curve Fitting Toolbox software creates prediction bounds for the ¯tted function
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or for new observations. The prediction bounds or intervals de¯ne upper and lower
values according to an already set con¯dence level.
3. Prediction of Parameters for 45 nm to 22 nm Process Nodes
Modern device parameters depend mainly on critical primary parameters including
supply voltage (Vdd), threshold voltage (Vth), electrical oxide thickness (Tox), drain
and source parasitic resistance (Rdsw), e®ective gate length (Leff), mobility (�0),
channel doping concentration (Nch), saturation velocity (Vsat) and DIBL e®ect
(Eta0). During technology scaling, the transistor performance is less sensitive to other
secondary parameters. Therefore, the objective is to predict the primary parameters
of a bulk device.
3.1. Process data base
For the literature, some primary parameters are provided from several sources. First,
the ITRS presents the future needs of semiconductor industries for the next
15 years.15 Second, process descriptions access for the ON-SEMI, AMS, IBM, TSMC,
Globalfoundries, Tezzaron and Peregrine fabrication process are available through
MOSIS (Table 1).6 Third, BPTM shows di®erent models for bulk CMOS that have
already been achieved from 180 to 32 nm process nodes.4
3.2. Procedure of BW predictive method
In order to reach a smooth scaling, the used BW method needs (xi; yi) scatter as long
as a monotony combination of x and y parameters is set. x and y parameters de¯ne
respectively the process nodes and device parameters. We opt for the parameters
summarized in Table 2,16,17 that show a monotony combination between x and y.
Our purpose consists of ¯tting linear or nonlinear models to data using the robust
BWmethod from 45 nm to 22 nm process nodes. Correct data sources have to lead to
an accurate ¯tting for future process. Some unavailable parameters in data sources
are computed. In fact, the model ¯les for process nodes starting from 130 nm to 65 nm
Table 1. MOSIS CMOS process.
Foundries
Process nodes (nm) ON SEMI AMS IBM TSMC Globalfoundries Tezzaron
500 � �350 � � �250 � �180 � � �130 � � � �90 �65 � �
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do not involve the mobility. Therefore, to consider this e®ect, the following
formulas are adopted in the LSM to estimate the mobility �0 for NMOS and PMOS
devices18,19:
NMOS: �0 ¼ 1150� expð�5:34� 10�10ffiffiffiffiffiffiffiffiNch
pÞ ; ð6Þ
PMOS: �0 ¼ 317� expð�1:25� 10�9ffiffiffiffiffiffiffiffiNch
pÞ ; ð7Þ
where Nch is the channel doping concentration. Moreover, to estimate the saturation
velocity, the following formulas are respectively adopted20:
Vsat ¼ Vsat0 þ 0:13�eff
ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi��effkT=q
pðVdd=L
2effÞ ; ð8Þ
�eff ¼�0
1þ 1:7Vgs � Vth
Tox
� �0:25
þ 31:5Vgs � Vth
Tox
� � ð9Þ
T , Vsat0, � ,K , q, Vdd, Leff , �0, Vgs, Vth and Tox represent, respectively the temperature,
the saturation velocity at T ¼ 0�C, the intrinsic transistor delay, the Boltzmann's
constant, the magnitude of the electrical charge on the electron, the supply voltage,
the e®ective gate length, the mobility, the gate-source voltage, the threshold voltage
and the electrical oxide thickness.
We start with opening the Curve Fitting Tool using the \cftool" command.
Before ¯tting the scatter set (xi; yi), we are often confronted with the task of
choosing the best model among several proposed alternatives. Exploring various ¯ts
provided from the library to the current data set, we then compare ¯t results
including the ¯tted coe±cients and goodness of ¯t statistics before deciding on the
best ¯t. Both the graphical and numerical ¯t results should be examined. The resi-
duals and prediction bounds are graphical measures, whereas the goodness of ¯t
statistics and con¯dence bounds are numerical measures. Next, once the ¯t model is
¯xed, we extrapolate it to predict the parameter from 45 nm to 22 nm process nodes.
Table 2. List of parameters from PTM07�09 for NMOS transistor.
Process nodes (nm) 65 90 130 180 250
Vdd (V) 1.1 1.2 1.3 1.5 1.8
Vth (V) 0.281 0.284 0.288 0.3 0.38Tox (nm) 1.25 1.3 1.62 2.3 4
Nch(e18 cm�3) 5 3.8 2.8 1.7 1
�0 (�A/V2) 348.4 406 470.6 573.2 674.2
Rdsw (Ohms/�m) 175 190 225 280 400
Leff (nm) 25 35 50 70 120
Vsat (103 m/sec) 130 115 100 97 90
Eta0 (10�3) 6 7.5 9 12.2 19.5
Ion (�A/�m) 1180 1105 1010 900 650
Ioff(nA/�m) 150 100 52 19 18
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Finally, we plot both the predictive results and the data. As an example, a graphical
display of residuals for di®erent model ¯ts is shown in Fig. 1. In fact, we ¯t (xi; yi)
data with polynomial, exponential and power model ¯ts. The residuals for expo-
nential and polynomial models appear randomly scattered around zero indicating
that the models ¯t the data well. Although, the power model is a poor ¯t for the data
because the residual is systematically negative for much of the data range. To choose
between polynomial and exponential models ¯ts, we should examine the numerical
¯t results given in Table. 3. The goodness of ¯t statistics enables us to determine
how well the curve ¯ts the data. From Table 3, the lowest SSE and RMSE values
are associated with the exponential model suggesting it is the best ¯t. The con¯dence
bounds on the coe±cients for this model con¯rm their accuracy. To compare the
BW to the LS methods, we are ¯tting the data with the chosen model (exponential)
using the LS and the BW methods (see Fig. 2). From this ¯gure, it is seen that the
use of BW method results in a smooth and accurate ¯tting. After applying the steps
0 50 100 150 200 250 300
1
2
3
4
5
6Data and models Fits
Process nodes (nm)
Nch
n (1
018 c
m-3
)
0 50 100 150 200 250 300
-0.4
-0.2
0
0.2
0.4
0.6
Res
idua
ls
Datapolynomial fitExponential fitPower fit
Fig. 1. Graphical ¯ts results.
Table 3. Numerical ¯ts results.
Coe±cients values Goodness of ¯t statistics
General model ¯t (with 95% con¯dence bounds) SSE R-sq Adj-R-sq RMSE
Linear polynomial: fðxÞ ¼ axþ b a ¼ �0:021½�0:032;�0:009� 0.81 0.92 0.89 0.52
b ¼ 5:84 [4.07, 7.61]
Power: fðxÞ ¼ axb a ¼ 415:5 [2.16, 829] 0.09 0.99 0.98 0.17
b ¼ �1:06½�1:27;�0:84�Exponential: fðxÞ ¼ a expðbxÞ a ¼ 8:84 [7.6, 10.02] 0.04 0.99 0.99 0.11
b ¼ �0:009½�0:01;�0:007�
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of estimation described previously, we summarize the predictive parameters listed in
Table 4.
Prediction bounds de¯ne the width of the interval which indicates how uncertain
you are about the predicted observation. The bounds are de¯ned with a speci¯ed
0 50 100 150 200 250 3000
1
2
3
4
5
6
Process nodes (nm)
Nch
n (1
018 c
m-3
)
DataFitting using the LS method
Fitting using the BW method
Fig. 2. Fitting using both of the LS and the BW methods.
Table 4. List of predictive parameters using BW method.
Parameters predicted for 95% prediction bounds
Process nodes (nm) 45 32 22
Vdd (V) 1 0.96 0.92
Prediction bounds [0.9, 1.1] [0.84, 1.06] [0.8, 1.05]Vth (V) 0.273 0.266 0.259
Prediction bounds [0.24, 0.3] [0.21, 0.32] [0.18, 033]
Tox (nm) 0.94 0.85 0.8
Prediction bounds [0.43, 1.4] [0.35, 1.36] [0.3, 1.3]
Nch (1018 cm�3) 6.5 8.1 10.1
Prediction bounds [5.1, 7.8] [5.4, 10.6] [5.3, 14.8]
�0 (�A/V2) 301.8 270 245.5
Prediction bounds [256.5, 347] [216.7, 324] [184.3, 306.7]
Rdsw (�/�m) 154 145 138.6Prediction bounds [139, 169] [130, 160] [123.6, 153.5]
Leff (nm) 19 15.7 13.45
Prediction bounds [12, 26] [7, 24] [4, 23]
Vsat (103 m/sec) 155.2 190 244
Prediction bounds [122.7, 187.6] [104, 274] [43, 445]
Eta0 (10�3) 5.3 4.9 4.6
Prediction bounds [4, 6.5] [3.7, 6] [3.4, 5.8]
Ion (�A/�m) 1241 1277 1305Prediction bounds [1134, 1347] [1166, 1387] [1191, 1418]
Ioff (nA/�m) 277.6 480 877
Prediction bounds [183, 372] [240, 721] [266, 1488]
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level of certainty. The level of certainty is often 95. Using the Curve Fitting Tool, we
have calculated a 95% prediction interval, this means that we want to take a 5%
chance of being incorrect about predicting a new observation. From Table 4, all
prediction bounds indicate that primary parameters considered as new observations,
can be predicted accurately throughout the entire data range. Prediction bounds for
new observations can be computed by the use of \Predint" function. All curves from
Figs. 3 to 13 present the trend of primary parameters scaling from 250 nm to 22 nm
process nodes for an NMOS device.
3.3. Discussions and interpretations
When determining the best ¯t to primary parameters, we decide on choosing linear
polynomial model for Vdd and Ion (Figs. 3 and 6), cubic polynomial model for Vth
(Fig. 4), exponential model for Eta0, Ioff , Tox, Nch and Rdsw (Figs. 5, 7�9 and 12),
quadratic polynomial model for �0 and Leff (Figs. 10 and 13) and power model for
Vsat (Fig. 11). Compared to PTM, ITRS and Fujitsu data, all primary parameters
values predicted from 45 nm to 22 nm process nodes are approximately close to those
predicted by PTM with an error less than 18%.4,15,21 Low power is the ¯rst challenge
that analog designers faced while moving into Nanometer CMOS process. In fact, the
voltage on the transistor is decreased to avoid the transistor breakdown and to
maintain the electric ¯eld constant inside the transistor. From Fig. 3, when the
channel length value is below 90 nm, it is seen that the supply voltage, whose value
varies between 1.2 and 0.92V, becomes a critical issue.22 The reduced supply voltage
decreases the input signal range, hence making the constraints on thermal noise and
o®set even more stringent. The deep-submicron CMOS process focus on maintaining
device and circuit speed improvements despite shrinking supply voltages. During
process scaling, the short channel e®ect (SCE) and the drain-induced barrier low-
ering (DIBL) are included in the Vth model as19:
Vth ¼ Vth0 ��VthðSCEþDIBLÞ ; ð10Þ
0 50 100 150 200 250 3000
0.5
1
1.5
2
Process nodes (nm)
Vdd
(V
olts
)
(250nm- 65nm) PTM, (45nm- 22nm) BWMLinear polynomial fit
(45nm- 32nm) PTM, (45nm) Fujitsu(45nm- 22nm) ITRS
250
2232
4565
90130
180
Fig. 3. The scaling of supply voltage.
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where Vth0 is the long channel threshold voltage. Taking into account the above
equation, Fig. 4 shows that the threshold voltage reduces from 0.38V to 0.259V,
when the channel length becomes shorter. Figure 5 presents the scaling of Eta0 which
is extracted from the Vth values. The smaller the value of Eta0, the stronger the DIBL
is. These trends reveal the state-of-the-art of upcoming technologies. As the drive
current Ion increases, as in Fig. 6, at a constant rate during technology scaling, the
leakage current Ioff rises exponentially and becomes a big design challenge (see
Fig. 7). In fact, as process geometries continuously shrink, threshold voltage leads to
a dramatic increase in leakage current.23 In fact, this current which represents the
one conducted by an MOS transistor in an o® state is modelled by24:
Ioff ¼ Io exp�Vth
nkT=q
� �; ð11Þ
where Io, n and kT=q are respectively the reverse saturation current, the sub-
threshold swing parameter and the thermal voltage. From \Eq. (11)", the leakage
0 50 100 150 200 250 3000
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
Process nodes (nm)
Vth
n (V
olts
)
(250nm- 65nm) PTM, (45nm- 22nm) BWMCubic polynomial fit(45nm- 32nm) PTM
(45nm) Fujitsu
250
22 32 45 65 90 130180
Fig. 4. The scaling of threshold voltage.
0 50 100 150 200 250 3000
5
10
15
20
Process nodes (nm)
Eta
on (
10-3
)
(250nm- 65nm) PTM,(45nm-22nm) BWMExponential fit(45nm-32nm) PTM(45nm) Fujitsu
250
2232 45
6590
130
180
Fig. 5. The scaling of DIBL e®ect.
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current increases exponentially when Vth decreases. Moreover, Io is inversely pro-
portional to L in this equation and kT=q is non-scaling thermal potential. The in-
crease of Ioff may lead to unacceptably high power consumption and a reduction of
device lifetime. Figure 8 shows that the oxide thickness has been scaled sharply from
4 nm to 0.8 nm when process node is scaling. A thinner oxide, a larger oxide capac-
itance Cox raises the gate leakage current described by:
Igate�leakage ¼ K1WVgb
Tox
� �exp
��Tox
Vgb
� �; ð12Þ
where K1 and � are ¯t factors, W and Vgb are respectively the size of the transistor
and gate-bulk voltage. Tunneling leakage current becomes the most serious limiting
factor making the power consumption and functionality at the circuit level more
impacted.25 Since the channel doping concentration Nch is proportional to Cox, it
increases exponentially, in Fig. 9, from 1 e18 cm�3 to 10.1 e18 cm�3. The mobility �0
decreases in Fig. 10. In fact, the higher the channel doping concentration related to
0 50 100 150 200 250 3000
200
400
600
800
1000
1200
1400
Process nodes (nm)
Ionn
(A
/µm
)
(250nm- 65nm) PTM, (45nm- 22nm) BWM
Linear polynomial fit(45nm- 32nm) PTM
(45nm) Fujitsu
250
22 32 4565
90130
180
Fig. 6. The scaling of drive current.
0 50 100 150 200 250 300
0
200
400
600
800
1000
Process nodes (nm)
Ioffn
(nA
/µm
)
(250nm- 65nm) PTM, (45nm- 22nm) BWMExponential fit(45nm-32nm) PTM(45nm) Fujitsu
250
22
32
45
6590
130180
Fig. 7. The scaling of leakage current.
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0 50 100 150 200 250 3000
1
2
3
4
5
Process nodes (nm)
Toxn
(nm
)
(250nm- 65nm) PTM,(45nm- 22nm) BWM
Exponential fit
(45nm- 32nm) PTM
(45nm- 22nm) ITRS
250
22 32 4565
90130
180
Fig. 8. The prediction of electrical oxide thickness.
0 50 100 150 200 250 3000
2
4
6
8
10
12
Process nodes (nm)
Nch
n (1
018
cm-3
)
(250nm- 65nm) PTM,(45nm-22nm) BWMExponential fit(45nm-32nm) PTMFujitsu
250
22
32
45
65
90130
180
Fig. 9. The prediction of channel doping concentration.
0 50 100 150 200 250 3000
100
200
300
400
500
600
700
800
Process nodes (nm)
Mob
ility
on
(µA
/V2 )
(250nm- 65nm) PTM,(45nm- 22nm) BWM
Quadratic polynomial fit(45nm- 32nm) PTM(45nm) Fujitsu
250
2232
4565
90
130
180
Fig. 10. The scaling of mobility.
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the need to control, the shorter the channel e®ect gives rise to more impurity scat-
tering and then lower mobility. Mobility degradation a®ects directly the device
performance. A few solutions exist to guarantee a reduced gate leakage current and
high device mobility. In fact engineers resorted to the development of high-k di-
electric process to replace SiO2.26�28 Short channel device geometries result in high
electric ¯elds where the saturation velocity e®ect becomes dominating (see Fig. 11).29
Therefore, device characteristics are drastically in°uenced. When scaling the device
sizes, the parasitic resistance Rdsw decreases from 400 to 138.6� (see Fig. 12). From
this ¯gure, the scaling of this resistance is quite slow from 90 nm to 22 nm nodes due
to the process limit. Figure 13 shows the decrease of Leff from 120 nm to 13.45 nm due
to the reduction of channel length.
As seen from all ¯gures, smooth and accurate predictions are acquired from
250 nm to 22 nm process nodes through BW method in order to make continuous
extrapolations. In fact, physical and estimated models are employed in the prediction
in order to perfectly capture the parameters [Eqs. (6)�(9)]. The prediction of
0 50 100 150 200 250 3000
50
100
150
200
250
300
Process nodes (nm)
Vsa
tn (
103
m/s
ec)
(250nm- 65nm) PTM, (45nm- 22nm) BWMPower fit(45nm- 32nm) PTM
250
22
32
45
6590
130 180
Fig. 11. The scaling of saturation velocity.
0 50 100 150 200 250 3000
50
100
150
200
250
300
350
400
450
Process nodes (nm)
Rds
wn
(Ohm
s/µm
)
(250nm- 65nm) PTM,(45nm- 22nnm) BWM
Exponential fit
(45nm- 32nm) PTM(45nm) Fujitsu
250
2232 45
6590
130
180
Fig. 12. The scaling of drain and source parasitic resistance.
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upcoming technologies is based on new PTM predictions which use accurate BSIM4
models from 250 nm to 65 nm process nodes.
3.4. Veri¯cation of bisquare weights method
Our objective consists of predicting primary parameters already estimated by
PTM and then comparisons are made to check the robustness of the method
(Tables 5 and 6). Using Curve Fitting Toolbox and according to the ¯tting models
chosen previously, we interpolate the primary parameters for 90 nm and 65 nm
process nodes.
The relative error given by Tables 5 and 6 is de¯ned by:
Relative error ¼ real value�measured value
real value: ð13Þ
The real value and the measured value represent respectively the values given by
PTM and BW methods. We conclude that the values of primary parameters pre-
dicted with the BW method are approximately close to those given by the PTM with
0 50 100 150 200 250 3000
20
40
60
80
100
120
140
Process nodes (nm)
Leffn
(nm
)
(250nm- 65nm) PTM,(45nm- 32nm) BWMQuadratic polynomial fit(45nm- 32nm) PTM(45nm) Fujitsu
250
22 32
45
6590
130
180
Fig. 13. The scaling of e®ective gate length.
Table 5. Veri¯cation of 90 nm BW method with PTM.
BW method PTM07�0917,18 Relative error (%)
Process nodes (nm) 90
Vdd (V) 1.2 1.2 0Vth (V) 0.285 0.284 0.3
Tox (nm) 1.3 1.4 7
Nch (e18 cm�3) 4 3.8 5
�0 (�A/V2) 400 406 1.4
Rdsw (Ohms/�m) 169 170 0.5
Leff (nm) 37 35 5.7
Vsat (103 m/sec) 112 115 2.6
Eta0 (10�3) 7.4 7.5 1.3
Ion (�A/�m) 1112 1105 0.6Ioff (nA/�m) 92 100 8
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a deviation of less than 12%. Therefore, a satisfactory agreement between predicted
and PTM data is achieved. Then, the robust BW method proves the physicality and
scalability of the performed extrapolation. Excellent optimized predictions have been
obtained due to the robust BW method.
4. Prediction of the Nano-CMOS Telescopic OTA Performance
Through BW Method
As a major building block, the OTA is broadly used in mixed-signal designs. This
section addresses the impact of Nanometer CMOS process on analog IC designs,
especially for an OTA design.
4.1. Telescopic OTA analysis
Telescopic OTA is used for high speed applications; thanks to its large gain and high
bandwidth (see Fig. 14). It consumes less power and has low noise. Both of open-loop
voltage gain and gain-bandwidth ¯rst order expressions are given below:
AV ¼ gm1RL ; ð14ÞGBW ¼ gm1
CL
; ð15ÞWhereRL ¼ ðgm5r05r07Þ==ðgm3r03r01Þ ; ð16Þ
where, gm1, gm3 and gm5, are respectively the transconductances of transistors M1, M3
and M5. r01, r03, r05 and r07 are respectively the drain-source resistances of transistors
M1, M3, M5 and M7. CL is the capacitance at the output node. The Slew rate is
expressed as:
SR ¼ GBWIbiasgm1
: ð17Þ
Table 6. Veri¯cation of 65 nm BW method with PTM.
BW method PTM07�0917,18 Relative error (%)
Process nodes (nm) 65
Vdd (V) 1.09 1.1 0.9
Vth (V) 0.28 0.281 0.35
Tox (nm) 1.1 1.25 12
Nch(e18 cm�3) 5.16 5 3.2
�0 (�A/V2) 348 348.4 0.1
Rdsw (Ohms/�m) 161 160 0.6
Leff (nm) 26 25 4
Vsat (103 m/sec) 127 130 2.3
Eta0 (10�3) 6.1 6 1.6
Ion (�A/�m) 1176 1180 0.3
Ioff (nA/�m) 154 150 2.6
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The common mode rejection ratio (CMRR) expression is given by:
CMRR ¼ Ad
AC
where Ad ¼ gm1RL and AC ¼ r072r09
; ð18Þ
where r09 is the drain-source resistance of transistor M9. The DC power consumption
is expressed as:
P ¼ ðVsupply � IbiasÞ ; ð19Þwhere Vsupply ¼ Vdd � Vss and Ibias is the bias current.
4.2. Procedure of performance prediction
Our objective is to predict the performance of a telescopic OTA during process
scaling. Figure 15 summarizes the overall work. First, we begin by specifying the
process node. Then, we check the accessibility of primary parameters useful for OTA
design. If all or some of primary parameters are not available, we predict them
through the BW method. After that, the characterization of telescopic OTA in-
cluding Nanoscale technological parameters is used to apply the optimization process
through Heuristic algorithm.30 This algorithm, programmed with Cþþ software, is
used to maximize and minimize an objective function. In fact, we start by setting the
parameters to optimize and indicating their variation ranges. Next, random variables
vectors are generated followed by a veri¯cation of preliminary conditions. After a
series of trials with the randomly chosen parameters, the computation of the
ddV
ssV
7M
2M
V2
V3
V1
biasV
8M
5M6M
3M 4M
1M
+oV -
oV
-inV
+inV
9M
biasI
Fig. 14. Telescopic OTA.
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objective function yields to optimal width and length values of the used devices. An
optimal bias current is also obtained. This optimization tool gave promising results
in analog circuits design for 0.35�m CMOS process.31�33 Eventually, the perfor-
mance of telescopic OTA such as Av, GBW, CMRR, gm, SR and P are optimized
when using the predicted primary parameters of CMOS transistor. The curves from
Figs. 16 to 21 show the trend of telescopic OTA performance scaling for constant
polarization current Ibias set to 1mA.
4.3. Impact of moving into nanometer CMOS to OTA design
When analog designers move into Nanometer CMOS process, high speed transistor
can be provided. As the process is scaled below 180 nm, the gain-bandwidth product
0 100 200 300 4000
1
2
3
4
5
6
7
8
Process nodes (nm)
GB
W (
GH
z)
22
32
4565
90130
180250
350
Fig. 16. The scale of GBW.
Nanoscale CMOS process node
Capture of primary parameters
If primary parametersare not available
Introduction of primaryparameters in OTA modeling
Optimization via HeuristicAlgorithm
Predicted and optimized OTAperformances
Prediction of primaryparameters via BWM
Setting of parameters variation ranges
Generation of a testing vector
Objective functions computation
Memorized new testing vector
If not
If not Specifications are satisfied
Test of the constraints
Constraints are satisfied
Yes
Fig. 15. (a) Synoptic of prediction of NanoCMOS OTA performance (b) Optimization algorithm
procedure.
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varies between 1.8GHz and 7GHz, it was noticed that the speed of the basic circuit
(OTA) improved (see Fig. 16). The intrinsic fT of upcoming transistor is continu-
ously growing up if the transistor channel length is decreased. An OTA with a higher
GBW has more e±cient power to achieve, gaining the speed advantage o®ered by
process scaling. In addition, Nanometer design bene¯ts from high transconductance
device. Figure 17 shows the scale of input transconductance. Owing to the channel
length modulation e®ect, the output impedance proportional to the channel length is
decreased. Therefore, the intrinsic voltage gain of a transistor is reduced in Nano-
meter technologies. Figures 18 and 19 show the decrease of telescopic OTA gain and
CMRR varying between 71 and 110 dB. A gain-speed trade-o® must be made in
Nanometer CMOS process when faster speed and less gain are obtained from a single
transistor. The minimum transistor size leads to not only a lower gain but also poorer
matching properties of the device.34 The Slew rate is decreased in Fig. 20, due to the
0 100 200 300 4000
5
10
15
20
25
Process nodes (nm)
Inpu
t Tra
nsco
nduc
tanc
e (m
S)
22
32
4565
90130
180250 350
Fig. 17. The scale of gm1.
0 100 200 300 4000
20
40
60
80
100
Process nodes (nm)
DC
Gai
n (d
B)
350
45
65 90 130180
250
22
32
Fig. 18. The scale of DC gain.
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strong raise of transconductance and the limited output swing of telescopic OTA
during the scaling process. The device characteristics become more sensitive to
variations in the reduced channel length, making the OTA design tasks greatly
di±cult. Rapid shrinking of device dimensions and reduction of the supply voltage
reduce signi¯cantly the power dissipation of the device. Figure 21 shows the possible
decrease of OTA power from 6.46mW to 2.2mW. Nevertheless, better control of
leakage current should be made. Nanometer designers will have to focus on limiting
power consumption while sustaining throughput and reliability. During Nanoscale
process, in spite of the reduction of gain varying between 71.4 dB and 102 dB, tele-
scopic OTA circuit presents acceptable gain useful for high speed applications.
0 100 200 300 4000
20
40
60
80
100
120
Process nodes (nm)
CM
RR
(dB
)
22
3245
65 90130 180 250
350
Fig. 19. The scale of CMRR.
0 100 200 300 4000
100
200
300
400
500
600
Process nodes (nm)
Sle
w r
ate
(V/ µ
s)
2232
4565 90
130180 250
350
Fig. 20. The scale of Slew rate.
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5. Conclusion
The BW method is used to predict the primary parameters of CMOS device for
future process. By using the appropriate BSIM model for each primary parameter,
accurate values can be fruitfully obtained. Comparing PTM data to BW method, a
satisfying extrapolation with an e±ciency and scalability of the performed adjust-
ment is achieved. The BW method is e®ective for process projection and it presents a
prediction with evaluated quality. The Heuristic program plays a key role in opti-
mizing the predicted performance of telescopic OTA. The CMOS scaling down leads
to not only make OTA faster, but also to overcome many design di±culties. The
gain-bandwidth product the value of which can reach 7GHz is useful for new wireless
systems. Nanoscale CMOS can drop the power consumption of telescopic OTA below
3mW value favoring the low power wireless communication systems. The achieved
results show that faster speed and low power can be reached but less gain, low Slew
rate and limited voltage swings are obtained. The lower supply voltage leads to
di±culties in the design of high dynamic range Delta-Sigma modulator. It makes the
distortion a big challenge for high linearity modulator. Nanometer CMOS process
reduces the driving voltage for the switch, resulting in higher switch on resistance.
Future works will involve the use of the BW method to predict the performance of
Delta-Sigma modulator for data converters used in radio-communication receivers.
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. For
per
sona
l use
onl
y.