Asynchronous reset D- FF

1 //-----------------------------------------------------2 // Design Name : dff_async_reset3 // File Name : dff_async_reset.v4 // Function : D flip-flop async reset5 // Coder : Deepak Kumar Tala6 //-----------------------------------------------------7 module dff_async_reset (8 data , // Data Input9 clk , // Clock Input10 reset , // Reset input11 q // Q output12 );13 //-----------Input Ports---------------14 input data, clk, reset ;1516 //-----------Output Ports---------------17 output q;1819 //------------Internal Variables--------20 reg q;2122 //-------------Code Starts Here---------23 always @ ( posedge clk or negedge reset)24 if (~reset) begin25 q <= 1'b0;26 end else begin27 q <= data;28 end2930 endmodule //End Of Module dff_async_reset

You could download file dff_async_reset.v here

Synchronous reset D- FF

1 //-----------------------------------------------------2 // Design Name : dff_sync_reset3 // File Name : dff_sync_reset.v4 // Function : D flip-flop sync reset5 // Coder : Deepak Kumar Tala6 //-----------------------------------------------------7 module dff_sync_reset (8 data , // Data Input9 clk , // Clock Input10 reset , // Reset input11 q // Q output12 );13 //-----------Input Ports---------------14 input data, clk, reset ;1516 //-----------Output Ports---------------

17 output q;1819 //------------Internal Variables--------20 reg q;2122 //-------------Code Starts Here---------23 always @ ( posedge clk)24 if (~reset) begin25 q <= 1'b0;26 end else begin27 q <= data;28 end2930 endmodule //End Of Module dff_sync_reset

Asynchronous reset T - FF

1 //-----------------------------------------------------2 // Design Name : tff_async_reset3 // File Name : tff_async_reset.v4 // Function : T flip-flop async reset5 // Coder : Deepak Kumar Tala6 //-----------------------------------------------------7 module tff_async_reset (8 data , // Data Input9 clk , // Clock Input10 reset , // Reset input11 q // Q output12 );13 //-----------Input Ports---------------14 input data, clk, reset ;15 //-----------Output Ports---------------16 output q;17 //------------Internal Variables--------18 reg q;19 //-------------Code Starts Here---------20 always @ ( posedge clk or negedge reset)21 if (~reset) begin22 q <= 1'b0;23 end else if (data) begin24 q <= ! q;25 end2627 endmodule //End Of Module tff_async_reset

You could download file tff_async_reset.v here

Synchronous reset T - FF

1 //-----------------------------------------------------2 // Design Name : tff_sync_reset3 // File Name : tff_sync_reset.v

4 // Function : T flip-flop sync reset5 // Coder : Deepak Kumar Tala6 //-----------------------------------------------------7 module tff_sync_reset (8 data , // Data Input9 clk , // Clock Input10 reset , // Reset input11 q // Q output12 );13 //-----------Input Ports---------------14 input data, clk, reset ;15 //-----------Output Ports---------------16 output q;17 //------------Internal Variables--------18 reg q;19 //-------------Code Starts Here---------20 always @ ( posedge clk)21 if (~reset) begin22 q <= 1'b0;23 end else if (data) begin24 q <= ! q;25 end2627 endmodule //End Of Module tff_async_reset

Regular D Latch

1 //-----------------------------------------------------2 // Design Name : dlatch_reset3 // File Name : dlatch_reset.v4 // Function : DLATCH async reset5 // Coder : Deepak Kumar Tala6 //-----------------------------------------------------7 module dlatch_reset (8 data , // Data Input9 en , // LatchInput10 reset , // Reset input11 q // Q output12 );13 //-----------Input Ports---------------14 input data, en, reset ;1516 //-----------Output Ports---------------17 output q;1819 //------------Internal Variables--------20 reg q;2122 //-------------Code Starts Here---------23 always @ ( en or reset or data)24 if (~reset) begin25 q <= 1'b0;26 end else if (en) begin

27 q <= data;28 end

8-Bit Simple Up Counter

1 //-----------------------------------------------------2 // Design Name : up_counter3 // File Name : up_counter.v4 // Function : Up counter5 // Coder� : Deepak6 //-----------------------------------------------------7 module up_counter (8 out , // Output of the counter9 enable , // enable for counter10 clk , // clock Input11 reset // reset Input12 );13 //----------Output Ports--------------14 output [7:0] out;15 //------------Input Ports--------------16 input enable, clk, reset;17 //------------Internal Variables--------18 reg [7:0] out;19 //-------------Code Starts Here-------20 always @(posedge clk)21 if (reset) begin22 out <= 8'b0 ;23 end else if (enable) begin24 out <= out + 1;25 end262728 endmodule

8-Bit Up Counter With Load

1 //-----------------------------------------------------2 // Design Name : up_counter_load3 // File Name : up_counter_load.v4 // Function : Up counter with load5 // Coder : Deepak Kumar Tala6 //-----------------------------------------------------7 module up_counter_load (8 out , // Output of the counter9 data , // Parallel load for the counter10 load , // Parallel load enable11 enable , // Enable counting

12 clk , // clock input13 reset // reset input14 );15 //----------Output Ports--------------16 output [7:0] out;17 //------------Input Ports--------------18 input [7:0] data;19 input load, enable, clk, reset;20 //------------Internal Variables--------21 reg [7:0] out;22 //-------------Code Starts Here-------23 always @(posedge clk)24 if (reset) begin25 out <= 8'b0 ;26 end else if (load) begin27 out <= data;28 end else if (enable) begin29 out <= out + 1;30 end3132 endmodule8-Bit Up-Down Counter

1 //-----------------------------------------------------2 // Design Name : up_down_counter3 // File Name : up_down_counter.v4 // Function : Up down counter5 // Coder : Deepak Kumar Tala6 //-----------------------------------------------------7 module up_down_counter (8 out , // Output of the counter9 up_down , // up_down control for counter10 clk , // clock input11 data , // Data to load12 reset // reset input13 );14 //----------Output Ports--------------15 output [7:0] out;16 //------------Input Ports--------------17 input [7:0] data;18 input up_down, clk, reset;19 //------------Internal Variables--------20 reg [7:0] out;21 //-------------Code Starts Here-------22 always @(posedge clk)23 if (reset) begin // active high reset24 out <= 8'b0 ;25 end else if (up_down) begin26 out <= out + 1;27 end else begin28 out <= out - 1;29 end30

31 endmodule

Random Counter (LFSR)

1 //-----------------------------------------------------2 // Design Name : lfsr3 // File Name : lfsr.v4 // Function : Linear feedback shift register5 // Coder : Deepak Kumar Tala6 //-----------------------------------------------------7 module lfsr (8 out , // Output of the counter9 enable , // Enable for counter10 clk , // clock input11 reset // reset input12 );1314 //----------Output Ports--------------15 output [7:0] out;16 //------------Input Ports--------------17 input [7:0] data;18 input enable, clk, reset;19 //------------Internal Variables--------20 reg [7:0] out;21 wire linear_feedback;2223 //-------------Code Starts Here-------24 assign linear_feedback = ! (out[7] ^ out[3]);2526 always @(posedge clk)27 if (reset) begin // active high reset28 out <= 8'b0 ;29 end else if (enable) begin30 out <= {out[6],out[5],31 out[4],out[3],32 out[2],out[1],33 out[0], linear_feedback};34 end3536 endmodule // End Of Module counter

You could download file lfsr.v here

LFSR Up/Down

1 `define WIDTH 82 module lfsr_updown (

3 clk , // Clock input4 reset , // Reset input5 enable , // Enable input6 up_down , // Up Down input7 count , // Count output8 overflow // Overflow output9 );1011 input clk;12 input reset;13 input enable;14 input up_down;1516 output [`WIDTH-1 : 0] count;17 output overflow;1819 reg [`WIDTH-1 : 0] count;2021 assign overflow = (up_down) ? (count == {{`WIDTH-1{1'b0}}, 1'b1}) :22 (count == {1'b1, {`WIDTH-1{1'b0}}}) ;2324 always @(posedge clk)25 if (reset)26 count <= {`WIDTH{1'b0}};27 else if (enable) begin28 if (up_down) begin29 count <= {~(^(count & `WIDTH'b01100011)),count[`WIDTH-1:1]};30 end else begin31 count <= {count[`WIDTH-2:0],~(^(count & `WIDTH'b10110001))};32 end33 end3435 endmodule

Random Counter (LFSR)

1 //-----------------------------------------------------2 // Design Name : lfsr3 // File Name : lfsr.v4 // Function : Linear feedback shift register5 // Coder : Deepak Kumar Tala6 //-----------------------------------------------------7 module lfsr (8 out , // Output of the counter9 enable , // Enable for counter10 clk , // clock input11 reset // reset input12 );13

14 //----------Output Ports--------------15 output [7:0] out;16 //------------Input Ports--------------17 input [7:0] data;18 input enable, clk, reset;19 //------------Internal Variables--------20 reg [7:0] out;21 wire linear_feedback;2223 //-------------Code Starts Here-------24 assign linear_feedback = ! (out[7] ^ out[3]);2526 always @(posedge clk)27 if (reset) begin // active high reset28 out <= 8'b0 ;29 end else if (enable) begin30 out <= {out[6],out[5],31 out[4],out[3],32 out[2],out[1],33 out[0], linear_feedback};34 end3536 endmodule // End Of Module counter

You could download file lfsr.v here

LFSR Up/Down

1 `define WIDTH 82 module lfsr_updown (3 clk , // Clock input4 reset , // Reset input5 enable , // Enable input6 up_down , // Up Down input7 count , // Count output8 overflow // Overflow output9 );1011 input clk;12 input reset;13 input enable;14 input up_down;1516 output [`WIDTH-1 : 0] count;17 output overflow;1819 reg [`WIDTH-1 : 0] count;2021 assign overflow = (up_down) ? (count == {{`WIDTH-1{1'b0}}, 1'b1}) :22 (count == {1'b1, {`WIDTH-1{1'b0}}}) ;2324 always @(posedge clk)25 if (reset)26 count <= {`WIDTH{1'b0}};

27 else if (enable) begin28 if (up_down) begin29 count <= {~(^(count & `WIDTH'b01100011)),count[`WIDTH-1:1]};30 end else begin31 count <= {count[`WIDTH-2:0],~(^(count & `WIDTH'b10110001))};32 end33 end3435 endmodule

You could download file lfsr_updown.v here

1 module tb();2 reg clk;3 reg reset;4 reg enable;5 reg up_down;67 wire [`WIDTH-1 : 0] count;8 wire overflow;910 initial begin11 $monitor("rst %b en %b updown %b cnt %b overflow %b",12 reset,enable,up_down,count, overflow);13 clk = 0;14 reset = 1;15 enable = 0;16 up_down = 0;17 #10 reset = 0;18 #1 enable = 1;19 #20 up_down = 1;20 #30 $finish;21 end2223 always #1 clk = ~clk;2425 lfsr_updown U(26 .clk ( clk ),27 .reset ( reset ),28 .enable ( enable ),29 .up_down ( up_down ),30 .count ( count ),31 .overflow ( overflow )32 );3334 endmodule

Gray Counter

1 //-----------------------------------------------------

2 // Design Name : gray_counter3 // File Name : gray_counter.v4 // Function : 8 bit gray counterS5 // Coder : Deepak Kumar Tala6 //-----------------------------------------------------7 module gray_counter (8 out , // counter out9 enable , // enable for counter10 clk , // clock11 rst // active hight reset12 );1314 //------------Input Ports--------------15 input clk, rst, enable;16 //----------Output Ports----------------17 output [ 7:0] out;18 //------------Internal Variables--------19 wire [7:0] out;20 reg [7:0] count;21 //-------------Code Starts Here---------22 always @ (posedge clk)23 if (rst)24 count <= 0;25 else if (enable)26 count <= count + 1;2728 assign out = { count[7], (count[7] ^ count[6]),(count[6] ^29 count[5]),(count[5] ^ count[4]), (count[4] ^30 count[3]),(count[3] ^ count[2]), (count[2] ^31 count[1]),(count[1] ^ count[0]) };3233 endmodule

One Hot Counter

1 //-----------------------------------------------------2 // Design Name : one_hot_cnt3 // File Name : one_hot_cnt.v4 // Function : 8 bit one hot counter5 // Coder : Deepak Kumar Tala6 //-----------------------------------------------------7 module one_hot_cnt (8 out , // Output of the counter9 enable , // enable for counter10 clk , // clock input11 reset // reset input12 );

13 //----------Output Ports--------------14 output [7:0] out;1516 //------------Input Ports--------------17 input enable, clk, reset;1819 //------------Internal Variables--------20 reg [7:0] out;2122 //-------------Code Starts Here-------23 always @ (posedge clk)24 if (reset) begin25 out <= 8'b0000_0001 ;26 end else if (enable) begin27 out <= {out[6],out[5],out[4],out[3],28 out[2],out[1],out[0],out[7]};29 end3031 endmodule

Divide by 2 Counter

1 //-----------------------------------------------------2 // Design Name : clk_div3 // File Name : clk_div.v4 // Function : Divide by two counter5 // Coder : Deepak Kumar Tala6 //-----------------------------------------------------78 module clk_div (clk_in, enable,reset, clk_out);9 // --------------Port Declaration-----------------------10 input clk_in ;11 input reset ;12 input enable ;13 output clk_out ;14 //--------------Port data type declaration-------------15 wire clk_in ;16 wire enable ;17 //--------------Internal Registers----------------------18 reg clk_out ;19 //--------------Code Starts Here-----------------------20 always @ (posedge clk_in)21 if (reset) begin22 clk_out <= 1'b0;23 end else if (enable) begin24 clk_out <= ! clk_out ;25 end2627 endmodule

Divide By 3 Counter

This module divides the input clock frequency by 3

1 //-----------------------------------------------------2 // Design Name : divide_by_33 // File Name : divide_by_3.v4 // Function : Divide By 35 // Coder : Deepak Kumar Tala6 //-----------------------------------------------------7 module divide_by_3 (8 clk_in , //Input Clock9 reset , // Reset Input10 clk_out // Output Clock11 );12 //-----------Input Ports---------------13 input clk_in;14 input reset;15 //-----------Output Ports---------------16 output clk_out;17 //------------Internal Variables--------18 reg [1:0] pos_cnt;19 reg [1:0] neg_cnt;20 //-------------Code Start-----------------21 // Posedge counter22 always @ (posedge clk_in)23 if (reset) begin24 pos_cnt <= 0;25 end else begin26 pos_cnt <= (pos_cnt == 2) ? 0 : pos_cnt + 1;27 end28 // Neg edge counter29 always @ (negedge clk_in)30 if (reset) begin31 neg_cnt <= 0;32 end else begin33 neg_cnt <= (neg_cnt == 2) ? 0 : neg_cnt + 1;34 end3536 assign clk_out = ((pos_cnt ! = 2) && (neg_cnt ! = 2));3738 endmodule3940 // Testbench to check the divide_by_3 logic41 module test();42 reg reset, clk_in;43 wire clk_out;44 divide_by_3 U (45 .clk_in (clk_in),46 .reset (reset),47 .clk_out (clk_out)48 );

4950 initial begin51 clk_in = 0;52 reset = 0;53 #2 reset = 1;54 #2 reset = 0;55 #100 $finish;56 end5758 always #1 clk_in = ~clk_in;5960 endmodule

Divide By 4.5 Counter

1 //-----------------------------------------------------2 // Design Name : clk_div_453 // File Name : clk_div_45.v4 // Function : Divide by 4.55 // Coder : Deepak Kumar Tala6 //-----------------------------------------------------7 module clk_div_45 (8 clk_in, // Input Clock9 enable, // Enable is sync with falling edge of clk_in10 clk_out // Output Clock11 );1213 // --------------Port Declaration-----------------------14 input clk_in ;15 input enable ;16 output clk_out ;1718 //--------------Port data type declaration-------------19 wire clk_in ;20 wire enable ;21 wire clk_out ;2223 //--------------Internal Registers----------------------24 reg [3:0] counter1 ;25 reg [3:0] counter2 ;26 reg toggle1 ;27 reg toggle2 ;2829 //--------------Code Starts Here-----------------------30 always @ (posedge clk_in)31 if (enable == 1'b0) begin32 counter1 <= 4'b0;33 toggle1 <= 0;34 end else if ((counter1 == 3 && toggle2) || (~toggle1

&& counter1 == 4)) begin35 counter1 <= 4'b0;36 toggle1 <= ~toggle1;37 end else begin38 counter1 <= counter1 + 1;39 end4041 always @ (negedge clk_in)42 if (enable == 1'b0) begin43 counter2 <= 4'b0;44 toggle2 <= 0;45 end else if ((counter2 == 3 && ~toggle2) || (toggle2 && counter2 == 4)) begin46 counter2 <= 4'b0;47 toggle2 <= ~toggle2;48 end else begin49 counter2 <= counter2 + 1;50 end5152 assign clk_out = (counter1 <3 && counter2 < 3) & enable;5354 endmoduleSingle Port RAM Synchronous Read/Write

1 //-----------------------------------------------------2 // Design Name : ram_sp_sr_sw3 // File Name : ram_sp_sr_sw.v4 // Function : Synchronous read write RAM5 // Coder : Deepak Kumar Tala6 //-----------------------------------------------------7 module ram_sp_sr_sw (8 clk , // Clock Input9 address , // Address Input10 data , // Data bi-directional11 cs , // Chip Select12 we , // Write Enable/Read Enable13 oe // Output Enable14 );1516 parameter DATA_WIDTH = 8 ;17 parameter ADDR_WIDTH = 8 ;18 parameter RAM_DEPTH = 1 << ADDR_WIDTH;1920 //--------------Input Ports-----------------------21 input clk ;22 input [ADDR_WIDTH-1:0] address ;23 input cs ;24 input we ;25 input oe ;2627 //--------------Inout Ports-----------------------28 inout [DATA_WIDTH-1:0] data ;

2930 //--------------Internal variables----------------31 reg [DATA_WIDTH-1:0] data_out ;32 reg [DATA_WIDTH-1:0] mem [0:RAM_DEPTH-1];33 reg oe_r;3435 //--------------Code Starts Here------------------3637 // Tri-State Buffer control38 // output : When we = 0, oe = 1, cs = 139 assign data = (cs && oe && ! we) ? data_out : 8'bz;4041 // Memory Write Block42 // Write Operation : When we = 1, cs = 143 always @ (posedge clk)44 begin : MEM_WRITE45 if ( cs && we ) begin46 mem[address] = data;47 end48 end4950 // Memory Read Block51 // Read Operation : When we = 0, oe = 1, cs = 152 always @ (posedge clk)53 begin : MEM_READ54 if (cs && ! we && oe) begin55 data_out = mem[address];56 oe_r = 1;57 end else begin58 oe_r = 0;59 end60 end6162 endmodule // End of Module ram_sp_sr_sw

Single Port RAM Asynch Read, Synch Write

1 //-----------------------------------------------------2 // Design Name : ram_sp_ar_sw3 // File Name : ram_sp_ar_sw.v4 // Function : Asynchronous read write RAM5 // Coder : Deepak Kumar Tala6 //-----------------------------------------------------7 module ram_sp_ar_sw (8 clk , // Clock Input9 address , // Address Input10 data , // Data bi-directional11 cs , // Chip Select12 we , // Write Enable/Read Enable13 oe // Output Enable14 );15

16 parameter DATA_WIDTH = 8 ;17 parameter ADDR_WIDTH = 8 ;18 parameter RAM_DEPTH = 1 << ADDR_WIDTH;1920 //--------------Input Ports-----------------------21 input clk ;22 input [ADDR_WIDTH-1:0] address ;23 input cs ;24 input we ;25 input oe ;2627 //--------------Inout Ports-----------------------28 inout [DATA_WIDTH-1:0] data ;2930 //--------------Internal variables----------------31 reg [DATA_WIDTH-1:0] data_out ;32 reg [DATA_WIDTH-1:0] mem [0:RAM_DEPTH-1];3334 //--------------Code Starts Here------------------3536 // Tri-State Buffer control37 // output : When we = 0, oe = 1, cs = 138 assign data = (cs && oe && ! we) ? data_out : 8'bz;3940 // Memory Write Block41 // Write Operation : When we = 1, cs = 142 always @ (posedge clk)43 begin : MEM_WRITE44 if ( cs && we ) begin45 mem[address] = data;46 end47 end4849 // Memory Read Block50 // Read Operation : When we = 0, oe = 1, cs = 151 always @ (address or cs or we or oe)52 begin : MEM_READ53 if (cs && ! we && oe) begin54 data_out = mem[address];55 end56 end5758 endmodule // End of Module ram_sp_ar_sw

Single Port RAM Asynchronous Read/Write

1 //-----------------------------------------------------2 // Design Name : ram_sp_ar_aw3 // File Name : ram_sp_ar_aw.v

4 // Function : Asynchronous read write RAM5 // Coder : Deepak Kumar Tala6 //-----------------------------------------------------7 module ram_sp_ar_aw (8 address , // Address Input9 data , // Data bi-directional10 cs , // Chip Select11 we , // Write Enable/Read Enable12 oe // Output Enable13 );14 parameter DATA_WIDTH = 8 ;15 parameter ADDR_WIDTH = 8 ;16 parameter RAM_DEPTH = 1 << ADDR_WIDTH;1718 //--------------Input Ports-----------------------19 input [ADDR_WIDTH-1:0] address ;20 input cs ;21 input we ;22 input oe ;2324 //--------------Inout Ports-----------------------25 inout [DATA_WIDTH-1:0] data ;2627 //--------------Internal variables----------------28 reg [DATA_WIDTH-1:0] data_out ;29 reg [DATA_WIDTH-1:0] mem [0:RAM_DEPTH-1];3031 //--------------Code Starts Here------------------3233 // Tri-State Buffer control34 // output : When we = 0, oe = 1, cs = 135 assign data = (cs && oe && ! we) ? data_out : 8'bz;3637 // Memory Write Block38 // Write Operation : When we = 1, cs = 139 always @ (address or data or cs or we)40 begin : MEM_WRITE41 if ( cs && we ) begin42 mem[address] = data;43 end44 end4546 // Memory Read Block47 // Read Operation : When we = 0, oe = 1, cs = 148 always @ (address or cs or we or oe)49 begin : MEM_READ50 if (cs && ! we && oe) begin51 data_out = mem[address];52 end53 end5455 endmodule // End of Module ram_sp_ar_aw

Dual Port RAM Synchronous Read/Write

1 //-----------------------------------------------------2 // Design Name : ram_dp_sr_sw3 // File Name : ram_dp_sr_sw.v4 // Function : Synchronous read write RAM5 // Coder : Deepak Kumar Tala6 //-----------------------------------------------------7 module ram_dp_sr_sw (8 clk , // Clock Input9 address_0 , // address_0 Input10 data_0 , // data_0 bi-directional11 cs_0 , // Chip Select12 we_0 , // Write Enable/Read Enable13 oe_0 , // Output Enable14 address_1 , // address_1 Input15 data_1 , // data_1 bi-directional16 cs_1 , // Chip Select17 we_1 , // Write Enable/Read Enable18 oe_1 // Output Enable19 );2021 parameter data_0_WIDTH = 8 ;22 parameter ADDR_WIDTH = 8 ;23 parameter RAM_DEPTH = 1 << ADDR_WIDTH;2425 //--------------Input Ports-----------------------26 input [ADDR_WIDTH-1:0] address_0 ;27 input cs_0 ;28 input we_0 ;29 input oe_0 ;30 input [ADDR_WIDTH-1:0] address_1 ;31 input cs_1 ;32 input we_1 ;33 input oe_1 ;3435 //--------------Inout Ports-----------------------36 inout [data_0_WIDTH-1:0] data_0 ;37 inout [data_0_WIDTH-1:0] data_1 ;3839 //--------------Internal variables----------------40 reg [data_0_WIDTH-1:0] data_0_out ;41 reg [data_0_WIDTH-1:0] data_1_out ;42 reg [data_0_WIDTH-1:0] mem [0:RAM_DEPTH-1];4344 //--------------Code Starts Here------------------45 // Memory Write Block46 // Write Operation : When we_0 = 1, cs_0 = 147 always @ (posedge clk)48 begin : MEM_WRITE49 if ( cs_0 && we_0 ) begin

50 mem[address_0] <= data_0;51 end else if (cs_1 && we_1) begin52 mem[address_1] <= data_1;53 end54 end55565758 // Tri-State Buffer control59 // output : When we_0 = 0, oe_0 = 1, cs_0 = 160 assign data_0 = (cs_0 && oe_0 && ! we_0) ? data_0_out : 8'bz;6162 // Memory Read Block63 // Read Operation : When we_0 = 0, oe_0 = 1, cs_0 = 164 always @ (posedge clk)65 begin : MEM_READ_066 if (cs_0 && ! we_0 && oe_0) begin67 data_0_out <= mem[address_0];68 end else begin69 data_0_out <= 0;70 end71 end7273 //Second Port of RAM74 // Tri-State Buffer control75 // output : When we_0 = 0, oe_0 = 1, cs_0 = 176 assign data_1 = (cs_1 && oe_1 && ! we_1) ? data_1_out : 8'bz;77 // Memory Read Block 178 // Read Operation : When we_1 = 0, oe_1 = 1, cs_1 = 179 always @ (posedge clk)80 begin : MEM_READ_181 if (cs_1 && ! we_1 && oe_1) begin82 data_1_out <= mem[address_1];83 end else begin84 data_1_out <= 0;85 end86 end8788 endmodule // End of Module ram_dp_sr_sw

Dual Port RAM Asynchronous Read/Write

1 //-----------------------------------------------------2 // Design Name : ram_dp_ar_aw3 // File Name : ram_dp_ar_aw.v4 // Function : Asynchronous read write RAM5 // Coder : Deepak Kumar Tala6 //-----------------------------------------------------

7 module ram_dp_ar_aw (8 address_0 , // address_0 Input9 data_0 , // data_0 bi-directional10 cs_0 , // Chip Select11 we_0 , // Write Enable/Read Enable12 oe_0 , // Output Enable13 address_1 , // address_1 Input14 data_1 , // data_1 bi-directional15 cs_1 , // Chip Select16 we_1 , // Write Enable/Read Enable17 oe_1 // Output Enable18 );1920 parameter DATA_WIDTH = 8 ;21 parameter ADDR_WIDTH = 8 ;22 parameter RAM_DEPTH = 1 << ADDR_WIDTH;2324 //--------------Input Ports-----------------------25 input [ADDR_WIDTH-1:0] address_0 ;26 input cs_0 ;27 input we_0 ;28 input oe_0 ;29 input [ADDR_WIDTH-1:0] address_1 ;30 input cs_1 ;31 input we_1 ;32 input oe_1 ;3334 //--------------Inout Ports-----------------------35 inout [DATA_WIDTH-1:0] data_0 ;36 inout [DATA_WIDTH-1:0] data_1 ;3738 //--------------Internal variables----------------39 reg [DATA_WIDTH-1:0] data_0_out ;40 reg [DATA_WIDTH-1:0] data_1_out ;41 reg [DATA_WIDTH-1:0] mem [0:RAM_DEPTH-1];4243 //--------------Code Starts Here------------------44 // Memory Write Block45 // Write Operation : When we_0 = 1, cs_0 = 146 always @ (address_0 or cs_0 or we_0 or data_047 or address_1 or cs_1 or we_1 or data_1)48 begin : MEM_WRITE49 if ( cs_0 && we_0 ) begin50 mem[address_0] <= data_0;51 end else if (cs_1 && we_1) begin52 mem[address_1] <= data_1;53 end54 end5556 // Tri-State Buffer control57 // output : When we_0 = 0, oe_0 = 1, cs_0 = 158 assign data_0 = (cs_0 && oe_0 && ! we_0) ? data_0_out : 8'bz;5960 // Memory Read Block61 // Read Operation : When we_0 = 0, oe_0 = 1, cs_0 = 1

62 always @ (address_0 or cs_0 or we_1 or oe_0)63 begin : MEM_READ_064 if (cs_0 && ! we_0 && oe_0) begin65 data_0_out <= mem[address_0];66 end else begin67 data_0_out <= 0;68 end69 end7071 //Second Port of RAM72 // Tri-State Buffer control73 // output : When we_0 = 0, oe_0 = 1, cs_0 = 174 assign data_1 = (cs_1 && oe_1 && ! we_1) ? data_1_out : 8'bz;75 // Memory Read Block 176 // Read Operation : When we_1 = 0, oe_1 = 1, cs_1 = 177 always @ (address_1 or cs_1 or we_1 or oe_1)78 begin : MEM_READ_179 if (cs_1 && ! we_1 && oe_1) begin80 data_1_out <= mem[address_1];81 end else begin82 data_1_out <= 0;83 end84 end8586 endmodule // End of Module ram_dp_ar_aw

ROM/EPROM - Loading from File

1 //-----------------------------------------------------2 // Design Name : rom_using_file3 // File Name : rom_using_file.v4 // Function : ROM using readmemh5 // Coder : Deepak Kumar Tala6 //-----------------------------------------------------7 module rom_using_file (8 address , // Address input9 data , // Data output10 read_en , // Read Enable11 ce // Chip Enable12 );13 input [7:0] address;14 output [7:0] data;15 input read_en;16 input ce;1718 reg [7:0] mem [0:255] ;1920 assign data = (ce && read_en) ? mem[address] : 8'b0;21

22 initial begin23 $readmemb("memory.list", mem); // memory_list is memory file24 end2526 endmodule

You could download file rom_using_file.v here

You can find the rom model and testbench here and memory_list file here.

rom_using_case

1 //-----------------------------------------------------2 // Design Name : rom_using_case3 // File Name : rom_using_case.v4 // Function : ROM using case5 // Coder : Deepak Kumar Tala6 //-----------------------------------------------------7 module rom_using_case (8 address , // Address input9 data , // Data output10 read_en , // Read Enable11 ce // Chip Enable12 );13 input [3:0] address;14 output [7:0] data;15 input read_en;16 input ce;1718 reg [7:0] data ;1920 always @ (ce or read_en or address)21 begin22 case (address)23 0 : data = 10;24 1 : data = 55;25 2 : data = 244;26 3 : data = 0;27 4 : data = 1;28 5 : data = 8'hff;29 6 : data = 8'h11;30 7 : data = 8'h1;31 8 : data = 8'h10;32 9 : data = 8'h0;33 10 : data = 8'h10;34 11 : data = 8'h15;35 12 : data = 8'h60;36 13 : data = 8'h90;37 14 : data = 8'h70;38 15 : data = 8'h90;39 endcase

40 end4142 endmodule

Synchronous FIFO

1 //-----------------------------------------------------2 // Design Name : syn_fifo3 // File Name : syn_fifo.v4 // Function : Synchronous (single clock) FIFO5 // Coder : Deepak Kumar Tala6 //-----------------------------------------------------7 module syn_fifo (8 clk , // Clock input9 rst , // Active high reset10 wr_cs , // Write chip select11 rd_cs , // Read chipe select12 data_in , // Data input13 rd_en , // Read enable14 wr_en , // Write Enable15 data_out , // Data Output16 empty , // FIFO empty17 full // FIFO full18 );1920 // FIFO constants21 parameter DATA_WIDTH = 8;22 parameter ADDR_WIDTH = 8;23 parameter RAM_DEPTH = (1 << ADDR_WIDTH);24 // Port Declarations25 input clk ;26 input rst ;27 input wr_cs ;28 input rd_cs ;29 input rd_en ;30 input wr_en ;31 input [DATA_WIDTH-1:0] data_in ;32 output full ;33 output empty ;34 output [DATA_WIDTH-1:0] data_out ;3536 //-----------Internal variables-------------------37 reg [ADDR_WIDTH-1:0] wr_pointer;38 reg [ADDR_WIDTH-1:0] rd_pointer;39 reg [ADDR_WIDTH :0] status_cnt;40 reg [DATA_WIDTH-1:0] data_out ;41 wire [DATA_WIDTH-1:0] data_ram ;4243 //-----------Variable assignments---------------44 assign full = (status_cnt == (RAM_DEPTH-1));45 assign empty = (status_cnt == 0);

4647 //-----------Code Start---------------------------48 always @ (posedge clk or posedge rst)49 begin : WRITE_POINTER50 if (rst) begin51 wr_pointer <= 0;52 end else if (wr_cs && wr_en ) begin53 wr_pointer <= wr_pointer + 1;54 end55 end5657 always @ (posedge clk or posedge rst)58 begin : READ_POINTER59 if (rst) begin60 rd_pointer <= 0;61 end else if (rd_cs && rd_en ) begin62 rd_pointer <= rd_pointer + 1;63 end64 end6566 always @ (posedge clk or posedge rst)67 begin : READ_DATA68 if (rst) begin69 data_out <= 0;70 end else if (rd_cs && rd_en ) begin71 data_out <= data_ram;72 end73 end7475 always @ (posedge clk or posedge rst)76 begin : STATUS_COUNTER77 if (rst) begin78 status_cnt <= 0;79 // Read but no write.80 end else if ((rd_cs && rd_en) && ! (wr_cs && wr_en)81 && (status_cnt ! = 0)) begin82 status_cnt <= status_cnt - 1;83 // Write but no read.84 end else if ((wr_cs && wr_en) && ! (rd_cs && rd_en)85 && (status_cnt ! = RAM_DEPTH)) begin86 status_cnt <= status_cnt + 1;87 end88 end8990 ram_dp_ar_aw #(DATA_WIDTH,ADDR_WIDTH)DP_RAM (91 .address_0 (wr_pointer) , // address_0 input92 .data_0 (data_in) , // data_0 bi-directional93 .cs_0 (wr_cs) , // chip select94 .we_0 (wr_en) , // write enable95 .oe_0 (1'b0) , // output enable96 .address_1 (rd_pointer) , // address_q input97 .data_1 (data_ram) , // data_1 bi-directional98 .cs_1 (rd_cs) , // chip select99 .we_1 (1'b0) , // Read enable100 .oe_1 (rd_en) // output enable

101 );102103 endmodule

Asynchronous FIFO

Note: This code is written in Verilog 2001.

1 //==========================================2 // Function : Asynchronous FIFO (w/ 2 asynchronous clocks).3 // Coder : Alex Claros F.4 // Date : 15/May/2005.5 // Notes : This implementation is based on the article6 // 'Asynchronous FIFO in Virtex-II FPGAs'7 // writen by Peter Alfke. This TechXclusive8 // article can be downloaded from the9 // Xilinx website. It has some minor modifications.10 //=========================================1112 `timescale 1ns/1ps1314 module aFifo15 #(parameter DATA_WIDTH = 8,16 ADDRESS_WIDTH = 4,17 FIFO_DEPTH = (1 << ADDRESS_WIDTH))18 //Reading port19 (output reg [DATA_WIDTH-1:0] Data_out,20 output reg Empty_out,21 input wire ReadEn_in,22 input wire RClk,23 //Writing port.24 input wire [DATA_WIDTH-1:0] Data_in,25 output reg Full_out,26 input wire WriteEn_in,27 input wire WClk,2829 input wire Clear_in);

3031 // 32 reg [DATA_WIDTH-1:0] Mem [FIFO_DEPTH-1:0];33 wire [ADDRESS_WIDTH-1:0] pNextWordToWrite, pNextWordToRead;34 wire EqualAddresses;35 wire NextWriteAddressEn, NextReadAddressEn;36 wire Set_Status, Rst_Status;37 reg Status;38 wire PresetFull, PresetEmpty;3940 // 41 //Data ports logic:42 //(Uses a dual-port RAM).43 //'Data_out' logic:44 always @ (posedge RClk)45 if (ReadEn_in & ! Empty_out)46 Data_out <= Mem[pNextWordToRead];4748 //'Data_in' logic:49 always @ (posedge WClk)50 if (WriteEn_in & ! Full_out)51 Mem[pNextWordToWrite] <= Data_in;5253 //Fifo addresses support logic:54 //'Next Addresses' enable logic:55 assign NextWriteAddressEn = WriteEn_in & ~Full_out;56 assign NextReadAddressEn = ReadEn_in & ~Empty_out;5758 //Addreses (Gray counters) logic:59 GrayCounter GrayCounter_pWr60 (.GrayCount_out(pNextWordToWrite),6162 .Enable_in(NextWriteAddressEn),63 .Clear_in(Clear_in),6465 .Clk(WClk)66 );6768 GrayCounter GrayCounter_pRd69 (.GrayCount_out(pNextWordToRead),70 .Enable_in(NextReadAddressEn),71 .Clear_in(Clear_in),72 .Clk(RClk)73 );747576 //'EqualAddresses' logic:77 assign EqualAddresses =

(pNextWordToWrite == pNextWordToRead);7879 //'Quadrant selectors' logic:80 assign Set_Status = (pNextWordToWrite[ADDRESS_WIDTH-2] ~^ pNextWordToRead[ADDRESS_WIDTH-1]) & 81 (pNextWordToWrite[ADDRESS_WIDTH-1] ^ pNextWordToRead[ADDRESS_WIDTH-2]);8283 assign Rst_Status = (pNextWordToWrite[ADDRESS_WIDTH-2] ^ pNextWordToRead[ADDRESS_WIDTH-1]) & 84 (pNextWordToWrite[ADDRESS_WIDTH-1] ~^ pNextWordToRead[ADDRESS_WIDTH-2]);8586 //'Status' latch logic:87 always @ (Set_Status, Rst_Status, Clear_in) //D Latch w/ Asynchronous Clear & Preset.88 if (Rst_Status | Clear_in)89 Status = 0; //Going 'Empty'.90 else if (Set_Status)91 Status = 1; //Going 'Full'.9293 //'Full_out' logic for the writing port:94 assign PresetFull = Status & EqualAddresses; //'Full' Fifo.9596 always @ (posedge WClk, posedge PresetFull) //D Flip-Flop w/ Asynchronous Preset.97 if (PresetFull)98 Full_out <= 1;99 else100 Full_out <= 0;101102 //'Empty_out' logic for the reading port:103 assign PresetEmpty = ~Status & EqualAddresses; //'Empty' Fifo.104105 always @ (posedge RClk, posedge PresetEmpty) //D Flip-Flop w/ Asynchronous Preset.106 if (PresetEmpty)107 Empty_out <= 1;108 else109 Empty_out <= 0;110111 endmodule

Content Addressable Memory (CAM)

1 //-----------------------------------------------------2 // Design Name : cam3 // File Name : cam.v4 // Function : CAM5 // Coder : Deepak Kumar Tala6 //-----------------------------------------------------7 module cam (8 clk , // Cam clock9 cam_enable , // Cam enable10 cam_data_in , // Cam data to match11 cam_hit_out , // Cam match has happened12 cam_addr_out // Cam output address13 );1415 parameter ADDR_WIDTH = 8;16 parameter DEPTH = 1 << ADDR_WIDTH;17 //------------Input Ports--------------18 input clk;19 input cam_enable;20 input [DEPTH-1:0] cam_data_in;21 //----------Output Ports--------------22 output cam_hit_out;23 output [ADDR_WIDTH-1:0] cam_addr_out;24 //------------Internal Variables--------25 reg [ADDR_WIDTH-1:0] cam_addr_out;26 reg cam_hit_out;27 reg [ADDR_WIDTH-1:0] cam_addr_combo;28 reg cam_hit_combo;29 reg found_match;30 integer i;31 //-------------Code Starts Here-------32 always @(cam_data_in) begin33 cam_addr_combo = {ADDR_WIDTH{1'b0}};34 found_match = 1'b0;35 cam_hit_combo = 1'b0;36 for (i=0; i<DEPTH; i=i+1) begin37 if (cam_data_in[i] && ! found_match) begin38 found_match = 1'b1;39 cam_hit_combo = 1'b1;40 cam_addr_combo = i;41 end else begin42 found_match = found_match;43 cam_hit_combo = cam_hit_combo;44 cam_addr_combo = cam_addr_combo;45 end46 end47 end4849 // Register the outputs50 always @(posedge clk) begin51 if (cam_enable) begin52 cam_hit_out <= cam_hit_combo;53 cam_addr_out <= cam_addr_combo;54 end else begin

55 cam_hit_out <= 1'b0;56 cam_addr_out <= {ADDR_WIDTH{1'b0}};57 end58 end5960 endmodule

PARITY

Using Assign

1 //-----------------------------------------------------2 // Design Name : parity_using_assign3 // File Name : parity_using_assign.v4 // Function : Parity using assign5 // Coder : Deepak Kumar Tala6 //-----------------------------------------------------7 module parity_using_assign (8 data_in , // 8 bit data in9 parity_out // 1 bit parity out10 );11 output parity_out ;12 input [7:0] data_in ;1314 wire parity_out ;1516 assign parity_out = (data_in[0] ^ data_in[1]) ^17 (data_in[2] ^ data_in[3]) ^18 (data_in[4] ^ data_in[5]) ^19 (data_in[6] ^ data_in[7]);2021 endmodule

You could download file parity_using_assign.v here

Using function- I

1 //-----------------------------------------------------2 // Design Name : parity_using_function3 // File Name : parity_using_function.v4 // Function : Parity using function5 // Coder : Deepak Kumar Tala6 //-----------------------------------------------------7 module parity_using_function (8 data_in , // 8 bit data in9 parity_out // 1 bit parity out10 );11 output parity_out ;

12 input [7:0] data_in ;1314 wire parity_out ;1516 function parity;17 input [31:0] data;18 begin19 parity = (data_in[0] ^ data_in[1]) ^20 (data_in[2] ^ data_in[3]) ^21 (data_in[4] ^ data_in[5]) ^22 (data_in[6] ^ data_in[7]);23 end24 endfunction252627 assign parity_out = parity(data_in);2829 endmodule

You could download file parity_using_function.v here

Using function- II

1 //-----------------------------------------------------2 // Design Name : parity_using_function23 // File Name : parity_using_function2.v4 // Function : Parity using function5 // Coder : Deepak Kumar Tala6 //-----------------------------------------------------7 module parity_using_function2 (8 data_in , // 8 bit data in9 parity_out // 1 bit parity out10 );11 output parity_out ;12 input [7:0] data_in ;1314 wire parity_out ;15 function parity;16 input [31:0] data;17 integer i;18 begin19 parity = 0;20 for (i = 0; i < 32; i = i + 1) begin21 parity = parity ^ data[i];22 end23 end24 endfunction2526 always @ (data_in)27 begin28 parity_out = parity(data_in);29 end30

31 endmodule

You could download file parity_using_function2.v here

And the Practical One

1 //-----------------------------------------------------2 // Design Name : parity_using_bitwise3 // File Name : parity_using_bitwise.v4 // Function : Parity using bitwise xor5 // Coder : Deepak Kumar Tala6 //-----------------------------------------------------7 module parity_using_bitwise (8 data_in , // 8 bit data in9 parity_out // 1 bit parity out10 );11 output parity_out ;12 input [7:0] data_in ;1314 assign parity_out = ^data_in;1516 endmodule

SERIAL CRC

Below code is 16-bit CRC-CCITT implementation, with following features

Width = 16 bits Truncated polynomial =

0x1021 Initial value = 0xFFFF Input data is NOT

reflected Output CRC is NOT

reflected No XOR is performed

on the output CRC

1 //-----------------------------------------------------2 // Design Name : serial_crc_ccitt3 // File Name : serial_crc.v4 // Function : CCITT Serial CRC5 // Coder : Deepak Kumar Tala6 //-----------------------------------------------------7 module serial_crc_ccitt (8 clk ,9 reset ,10 enable ,

11 init ,12 data_in ,13 crc_out14 );15 //-----------Input Ports---------------16 input clk ;17 input reset ;18 input enable ;19 input init ;20 input data_in ;21 //-----------Output Ports---------------22 output [15:0] crc_out;23 //------------Internal Variables--------24 reg [15:0] lfsr;25 //-------------Code Start-----------------26 assign crc_out = lfsr;27 // Logic to CRC Calculation28 always @ (posedge clk)29 if (reset) begin30 lfsr <= 16'hFFFF;31 end else if (enable) begin32 if (init) begin33 lfsr <= 16'hFFFF;34 end else begin35 lfsr[0] <= data_in ^ lfsr[15];36 lfsr[1] <= lfsr[0];37 lfsr[2] <= lfsr[1];38 lfsr[3] <= lfsr[2];39 lfsr[4] <= lfsr[3];40 lfsr[5] <= lfsr[4] ^ data_in ^ lfsr[15];41 lfsr[6] <= lfsr[5];42 lfsr[7] <= lfsr[6];43 lfsr[8] <= lfsr[7];44 lfsr[9] <= lfsr[8];45 lfsr[10] <= lfsr[9];46 lfsr[11] <= lfsr[10];47 lfsr[12] <= lfsr[11] ^ data_in ^ lfsr[15];48 lfsr[13] <= lfsr[12];49 lfsr[14] <= lfsr[13];50 lfsr[15] <= lfsr[14];51 end52 end5354 endmodule

Parallel CRC

Below code is 16-bit CRC-CCITT implementation, with following features

Width = 16 bits Truncated polynomial =

0x1021

Initial value = 0xFFFF Input data is NOT

reflected Output CRC is NOT

reflected No XOR is performed

on the output CRC

//-----------------------------------------------------2 // Design Name : parallel_crc_ccitt3 // File Name : parallel_crc.v4 // Function : CCITT Parallel CRC5 // Coder : Deepak Kumar Tala6 //-----------------------------------------------------7 module parallel_crc_ccitt (8 clk ,9 reset ,10 enable ,11 init ,12 data_in ,13 crc_out14 );15 //-----------Input Ports---------------16 input clk ;17 input reset ;18 input enable ;19 input init ;20 input [7:0] data_in ;21 //-----------Output Ports---------------22 output [15:0] crc_out;23 //------------Internal Variables--------24 reg [15:0] crc_reg;25 wire [15:0] next_crc;26 //-------------Code Start-----------------27 assign crc_out = crc_reg;28 // CRC Control logic29 always @ (posedge clk)30 if (reset) begin31 crc_reg <= 16'hFFFF;32 end else if (enable) begin33 if (init) begin34 crc_reg <= 16'hFFFF;35 end else begin36 crc_reg <= next_crc;37 end38 end39 // Parallel CRC calculation40 assign next_crc[0] = data_in[7] ^ data_in[0] ^ crc_reg[4] ^ crc_reg[11];41 assign next_crc[1] = data_in[1] ^ crc_reg[5];42 assign next_crc[2] = data_in[2] ^ crc_reg[6];43 assign next_crc[3] = data_in[3] ^ crc_reg[7];44 assign next_crc[4] = data_in[4] ^ crc_reg[8];45 assign next_crc[5] = data_in[7] ^ data_in[5] ^ data_in[0] ^ crc_reg[4] ^ crc_reg[9] ^ crc_reg[11];46 assign next_crc[6] = data_in[6] ^ data_in[1] ^ crc_reg[5] ^ crc_reg[10];

47 assign next_crc[7] = data_in[7] ^ data_in[2] ^ crc_reg[6] ^ crc_reg[11];48 assign next_crc[8] = data_in[3] ^ crc_reg[0] ^ crc_reg[7];49 assign next_crc[9] = data_in[4] ^ crc_reg[1] ^ crc_reg[8];50 assign next_crc[10] = data_in[5] ^ crc_reg[2] ^ crc_reg[9];51 assign next_crc[11] = data_in[6] ^ crc_reg[3] ^ crc_reg[10];5253 endmoduleNot Gate

1 //-----------------------------------------------------2 // Design Name : not_switch3 // File Name : not_switch.v4 // Function : NOT Gate Using Switch Primitives5 // Coder : Deepak Kumar Tala6 //-----------------------------------------------------7 module not_switch (out, in);8 output out;9 input in;1011 supply1 power;12 supply0 ground;1314 pmos (out, power, in);15 nmos (out, ground, in);1617 endmoduleYou could download file not_switch.v here

Two Input XOR

1 module nor2_switch (a,b,y);2 input a, b;3 output y;45 supply1 power;6 supply0 ground;78 wire connect;910 nmos (y,ground,a);11 nmos (y,ground,b);12 pmos (y,connect,b);13 pmos (power,connect,a);14

15 endmoduleYou could download file xor_switch.v here

Two Input NAND

1 module nand_switch(a,b,out);2 input a,b;3 output out;45 supply0 vss;6 supply1 vdd;7 wire net1;89 pmos p1 (vdd,out,a);10 pmos p2 (vdd,out,b);11 nmos n1 (vss,net1,a);12 nmos n2 (net1,out,b);1314 endmodule

2:1 Mux

1 //-----------------------------------------------------2 // Design Name : mux21_switch3 // File Name : mux21_switch.v4 // Function : 2:1 Mux using Switch Primitives5 // Coder : Deepak Kumar Tala6 //-----------------------------------------------------7 module mux21_switch (out, ctrl, in1, in2);89 output out;10 input ctrl, in1, in2;11 wire w;1213 supply1 power;14 supply0 ground;1516 pmos N1 (w, power, ctrl);17 nmos N2 (w, ground, ctrl);1819 cmos C1 (out, in1, w, ctrl);20 cmos C2 (out, in2, ctrl, w);2122 endmodule

D Latch

1 module not_switch (out, in);2 output out;3 input in;45 supply1 power;6 supply0 ground;78 pmos (out, power, in);9 nmos (out, ground, in);1011 endmodule1213 module d_latch_switch(clk,d,q);14 input clk,d;15 output q;1617 wire clkn, net1, qn;1819 not_switch i1 (clkn,clk);2021 pmos p1 (d,q,clkn);22 nmos n1 (d,q,clk);2324 pmos p2 (q,net1,clk);25 nmos n2 (q,net1,clkn);2627 not_switch i2 (qn,q);28 not_switch i3 (net1,qn);2930 endmodule

Transimission Gate

1 module t_gate_switch (L,R,nC,C);2 inout L;3 inout R;4 input nC;5 input C;67 //Syntax: keyword

unique_name (drain. source, gate);8 pmos p1 (L,R,nC);9 nmos p2 (L,R,C);1011 endmoduleYou could download file t_gate_switch.v here

!((a+b+c).d)

1 module misc1 (a,b,c,d,y);2 input a, b,c,d;3 output y;45 wire net1,net2,net3;67 supply1 vdd;8 supply0 vss;910 // y = !((a+b+c).d)1112 pmos p1 (vdd,net1,a);13 pmos p2 (net1,net2,b);14 pmos p3 (net2,y,c);15 pmos p4 (vdd,y,d);1617 nmos n1 (vss,net3,a);18 nmos n2 (vss,net3,b);19 nmos n3 (vss,net3,c);20 nmos n4 (net3,y,d);2122 endmodule

Half Adder

1 //-----------------------------------------------------2 // Design Name : half_adder_gates3 // File Name : half_adder_gates.v4 // Function : CCITT Serial CRC5 // Coder : Deepak Kumar Tala6 //-----------------------------------------------------

7 module half_adder_gates(x,y,sum,carry);8 input x,y;9 output sum,carry;1011 and U_carry (carry,x,y);12 xor U_sum (sum,x,y);1314 endmoduleYou could download file half_adder_gates.v here

Full Adder

1 //-----------------------------------------------------2 // Design Name : full_adder_gates3 // File Name : full_adder_gates.v4 // Function : Full Adder Using Gates5 // Coder : Deepak Kumar Tala6 //-----------------------------------------------------7 module full_adder_gates(x,y,z,sum,carry);8 input x,y,z;9 output sum,carry;10 wire and1,and2,and3,sum1;1112 and U_and1 (and1,x,y),13 U_and2 (and2,x,z),14 U_and3 (and3,y,z);15 or U_or (carry,and1,and2,and3);16 xor U_sum (sum,x,y,z);1718 endmodule

Full Subtracter

1 //-----------------------------------------------------2 // Design Name : full_subtracter_gates3 // File Name : full_subtracter_gates.v4 // Function : Full Subtracter Using Gates5 // Coder : Deepak Kumar Tala6 //-----------------------------------------------------7 module full_subtracter_gates(x,y,z,difference,borrow);8 input x,y,z;9 output difference,borrow;1011 wire inv_x,borrow1,borrow2,borrow3;

1213 not (inv_x,x);14 and U_borrow1 (borrow1,inv_x,y),15 U_borrow2 (borrow2,inv_x,z),16 U_borrow3 (borrow3,y,z);1718 xor U_diff (difference,borrow1,borrow2,borrows);1920 endmodule

2:1 Mux

1 //-----------------------------------------------------2 // Design Name : mux_2to1_gates3 // File Name : mux_2to1_gates.v4 // Function : 2:1 Mux using Gate Primitives5 // Coder : Deepak Kumar Tala6 //-----------------------------------------------------7 module mux_2to1_gates(a,b,sel,y);8 input a,b,sel;9 output y;1011 wire sel,a_sel,b_sel;1213 not U_inv (inv_sel,sel);14 and U_anda (asel,a,inv_sel),15 U_andb (bsel,b,sel);16 or U_or (y,asel,bsel);1718 endmoduleYou could download file mux_2to1_gates.v here

4:1 Mux

1 //-----------------------------------------------------2 // Design Name : mux_4to1_gates3 // File Name : mux_4to1_gates.v4 // Function : 4:1 Mux Using Gates5 // Coder : Deepak Kumar Tala6 //-----------------------------------------------------7 module mux_4to1_gates(a,b,c,d,sel,y);8 input a,b,c,d;9 input [1:0] sel;

10 output y;1112 wire mux_1,mux_2;1314 mux_2to1_gates U_mux1 (a,b,sel[0],mux_1),15 U_mux2 (c,d,sel[0],mux_2),16 U_mux3 (mux_1,mux_2,sel[1],y);1718 endmodule

2 To 4 Decoder

1 module decoder_2to4_gates (x,y,f0,f1,f2,f3);2 input x,y;3 output f0,f1,f2,f3;45 wire n1,n2;67 not i1 (n1,x);8 not i2 (n2,y);9 and a1 (f0,n1,n2);10 and a2 (f1,n1,y);11 and a3 (f2,x,n2);12 and a4 (f3,x,y);1314 endmodule

Two Input OR

1 //-----------------------------------------------------2 // Design Name : or2_input3 // File Name : or2_input.v4 // Function : 2 Input OR Gate Using UDP5 // Coder : Deepak Kumar Tala6 //-----------------------------------------------------7 primitive or2_input (c,a,b);8 output c;9 input a,b;10 table11 //a b : c12 1 ? : 1;13 ? 1 : 1;14 0 0 : 0;15 0 x : x;16 x 0 : x;17 endtable18 endprimitive

You could download file or2_input.v here

Two Input XOR

1 primitive xor2_input (c,a,b);2 output c;3 input a,b;4 table5 0 0 : 0;6 0 1 : 1;7 1 0 : 1;8 1 1 : 0;9 x 1 : x;10 1 x : x;11 x 0 : x;12 0 x : x;13 x x : x;14 endtable15 endprimitive

2:1 Mux

1 primitive mux_21_udp(out, sel, i0, i1);2 output out;3 input sel, i0, i1;4 table5 // sel i0 i1 out6 0 0 ? : 0 ; // 17 0 1 ? : 1 ; // 28 1 ? 0 : 0 ; // 39 1 ? 1 : 1 ; // 410 ? 0 0 : 0 ; // 511 ? 1 1 : 1 ; // 612 endtable13 endprimitive

equential Logic Using UDP

D Latch

1 primitive latch_udp(q, clock, data) ;2 output q; reg q ;3 input clock, data;4 table5 // clock data q q+6 0 1 : ? : 1 ;7 0 0 : ? : 0 ;8 1 ? : ? : - ; // - = no change9 endtable10 endprimitiveYou could download file latch_udp.v here

D Flip Flop

1 //-----------------------------------------------------2 // Design Name : dff_udp3 // File Name : dff_udp.v4 // Function : D Flip Flop5 // Coder : Deepak Kumar Tala6 //-----------------------------------------------------7 primitive dff_udp (q,clk,d);8 input clk,d;9 output q;10 reg q;11 table12 // clk d : q : q+13 r 0 : ? : 0 ;14 r 1 : ? : 1 ;15 f ? : ? : - ;16 ? * : ? : - ;17 endtable18 endprimitiveYou could download file dff_udp.v here

SR Flip Flop

1 primitive srff_udp (q,s,r);2 output q;3 input s,r;45 reg q;67 initial q = 1'b1;89 table10 // s r q q+11 1 0 : ? : 1 ;12 f 0 : 1 : - ;13 0 r : ? : 0 ;14 0 f : 0 : - ;15 1 1 : ? : 0 ;16 endtable1718 endprimitiveYou could download file srff_udp.v here

JK Flip Flop

1 //-----------------------------------------------------2 // Design Name : jkff_udp3 // File Name : jkff_udp.v4 // Function : JK Flip Flop Using UDP5 // Coder : Deepak Kumar Tala6 //-----------------------------------------------------7 primitive jkff_udp (q,clk,j,k);8 input clk,j,k;9 output q;10 reg q;11 table12 // clk j k : q : q+13 r 0 0 : ? : - ;14 r 0 1 : ? : 0 ;15 r 1 0 : ? : 1 ;16 r 1 1 : 0 : 1 ;17 r 1 1 : 1 : 0 ;18 f ? ? : ? : - ;19 ? * ? : ? : - ;20 ? ? * : ? : - ;

21 endtable22 endprimitive

Verilog Code

1 module hello_pli ();23 initial begin4 $hello;5 #10 $finish;6 end78 endmodule

Verilog UART Model

1 //-----------------------------------------------------2 // Design Name : uart3 // File Name : uart.v4 // Function : Simple UART5 // Coder : Deepak Kumar Tala6 //-----------------------------------------------------7 module uart (8 reset ,9 txclk ,10 ld_tx_data ,11 tx_data ,12 tx_enable ,13 tx_out ,14 tx_empty ,15 rxclk ,16 uld_rx_data ,17 rx_data ,18 rx_enable ,19 rx_in ,20 rx_empty21 );22 // Port declarations23 input reset ;24 input txclk ;25 input ld_tx_data ;26 input [7:0] tx_data ;27 input tx_enable ;28 output tx_out ;29 output tx_empty ;30 input rxclk ;31 input uld_rx_data ;32 output [7:0] rx_data ;

33 input rx_enable ;34 input rx_in ;35 output rx_empty ;3637 // Internal Variables38 reg [7:0] tx_reg ;39 reg tx_empty ;40 reg tx_over_run ;41 reg [3:0] tx_cnt ;42 reg tx_out ;43 reg [7:0] rx_reg ;44 reg [7:0] rx_data ;45 reg [3:0] rx_sample_cnt ;46 reg [3:0] rx_cnt ;47 reg rx_frame_err ;48 reg rx_over_run ;49 reg rx_empty ;50 reg rx_d1 ;51 reg rx_d2 ;52 reg rx_busy ;5354 // UART RX Logic55 always @ (posedge rxclk or posedge reset)56 if (reset) begin57 rx_reg <= 0;58 rx_data <= 0;59 rx_sample_cnt <= 0;60 rx_cnt <= 0;61 rx_frame_err <= 0;62 rx_over_run <= 0;63 rx_empty <= 1;64 rx_d1 <= 1;65 rx_d2 <= 1;66 rx_busy <= 0;67 end else begin68 // Synchronize the asynch signal69 rx_d1 <= rx_in;70 rx_d2 <= rx_d1;71 // Uload the rx data72 if (uld_rx_data) begin73 rx_data <= rx_reg;74 rx_empty <= 1;75 end76 // Receive data only when rx is enabled77 if (rx_enable) begin78 // Check if just received start of frame79 if ( ! rx_busy && ! rx_d2) begin80 rx_busy <= 1;81 rx_sample_cnt <= 1;82 rx_cnt <= 0;83 end84 // Start of frame detected, Proceed with rest of data85 if (rx_busy) begin86 rx_sample_cnt <= rx_sample_cnt + 1;87 // Logic to sample at middle of data88 if (rx_sample_cnt == 7) begin

89 if ((rx_d2 == 1) && (rx_cnt == 0)) begin90 rx_busy <= 0;91 end else begin92 rx_cnt <= rx_cnt + 1;93 // Start storing the rx data94 if (rx_cnt > 0 && rx_cnt < 9) begin95 rx_reg[rx_cnt - 1] <= rx_d2;96 end97 if (rx_cnt == 9) begin98 rx_busy <= 0;99 // Check if End of frame received correctly100 if (rx_d2 == 0) begin101 rx_frame_err <= 1;102 end else begin103 rx_empty <= 0;104 rx_frame_err <= 0;105 // Check if last rx data was not unloaded,106 rx_over_run <= (rx_empty) ? 0 : 1;107 end108 end109 end110 end111 end112 end113 if ( ! rx_enable) begin114 rx_busy <= 0;115 end116 end117118 // UART TX Logic119 always @ (posedge txclk or posedge reset)120 if (reset) begin121 tx_reg <= 0;122 tx_empty <= 1;123 tx_over_run <= 0;124 tx_out <= 1;125 tx_cnt <= 0;126 end else begin127 if (ld_tx_data) begin128 if ( ! tx_empty) begin129 tx_over_run <= 0;130 end else begin131 tx_reg <= tx_data;132 tx_empty <= 0;133 end134 end135 if (tx_enable && ! tx_empty) begin136 tx_cnt <= tx_cnt + 1;137 if (tx_cnt == 0) begin138 tx_out <= 0;139 end140 if (tx_cnt > 0 && tx_cnt < 9) begin141 tx_out <= tx_reg[tx_cnt -1];142 end

143 if (tx_cnt == 9) begin144 tx_out <= 1;145 tx_cnt <= 0;146 tx_empty <= 1;147 end148 end149 if ( ! tx_enable) begin150 tx_cnt <= 0;151 end152 end153154 endmodule

Verilog Round Robin Arbiter Model

1 //----------------------------------------------------2 // A four level, round-robin arbiter. This was3 // orginally coded by WD Peterson in VHDL.4 //----------------------------------------------------5 module arbiter (6 clk,7 rst,8 req3,9 req2,10 req1,11 req0,12 gnt3,13 gnt2,14 gnt1,15 gnt016 );17 // --------------Port Declaration-----------------------18 input clk;19 input rst;20 input req3;21 input req2;22 input req1;23 input req0;24 output gnt3;25 output gnt2;26 output gnt1;27 output gnt0;2829 //--------------Internal Registers----------------------30 wire [1:0] gnt ;31 wire comreq ;32 wire beg ;33 wire [1:0] lgnt ;34 wire lcomreq ;

35 reg lgnt0 ;36 reg lgnt1 ;37 reg lgnt2 ;38 reg lgnt3 ;39 reg lasmask ;40 reg lmask0 ;41 reg lmask1 ;42 reg ledge ;4344 //--------------Code Starts Here-----------------------45 always @ (posedge clk)46 if (rst) begin47 lgnt0 <= 0;48 lgnt1 <= 0;49 lgnt2 <= 0;50 lgnt3 <= 0;51 end else begin52 lgnt0 <=(~lcomreq & ~lmask1 & ~lmask0 & ~req3 & ~req2 & ~req1 & req0)53 | (~lcomreq & ~lmask1 & lmask0 & ~req3 & ~req2 & req0)54 | (~lcomreq & lmask1 & ~lmask0 & ~req3 & req0)55 | (~lcomreq & lmask1 & lmask0 & req0 )56 | ( lcomreq & lgnt0 );57 lgnt1 <=(~lcomreq & ~lmask1 & ~lmask0 & req1)58 | (~lcomreq & ~lmask1 & lmask0 & ~req3 & ~req2 & req1 & ~req0)59 | (~lcomreq & lmask1 & ~lmask0 & ~req3 & req1 & ~req0)60 | (~lcomreq & lmask1 & lmask0 & req1 & ~req0)61 | ( lcomreq & lgnt1);62 lgnt2 <=(~lcomreq & ~lmask1 & ~lmask0 & req2 & ~req1)63 | (~lcomreq & ~lmask1 & lmask0 & req2)64 | (~lcomreq & lmask1 & ~lmask0 & ~req3 & req2 & ~req1 & ~req0)65 | (~lcomreq & lmask1 & lmask0 & req2 & ~req1 & ~req0)66 | ( lcomreq & lgnt2);67 lgnt3 <=(~lcomreq & ~lmask1 & ~lmask0 & req3 & ~req2 & ~req1)68 | (~lcomreq & ~lmask1 & lmask0 & req3 & ~req2)69 | (~lcomreq & lmask1 & ~lmask0 & req3)70 | (~lcomreq & lmask1 & lmask0 & req3 & ~req2 & ~req1 & ~req0)71 | ( lcomreq & lgnt3);72 end7374 //----------------------------------------------------75 // lasmask state machine.76 //----------------------------------------------------

77 assign beg = (req3 | req2 | req1 | req0) & ~lcomreq;78 always @ (posedge clk)79 begin80 lasmask <= (beg & ~ledge & ~lasmask);81 ledge <= (beg & ~ledge & lasmask)82 | (beg & ledge & ~lasmask);83 end8485 //----------------------------------------------------86 // comreq logic.87 //----------------------------------------------------88 assign lcomreq = ( req3 & lgnt3 )89 | ( req2 & lgnt2 )90 | ( req1 & lgnt1 )91 | ( req0 & lgnt0 );9293 //----------------------------------------------------94 // Encoder logic.95 //----------------------------------------------------96 assign lgnt = {(lgnt3 | lgnt2),(lgnt3 | lgnt1)};9798 //----------------------------------------------------99 // lmask register.100 //----------------------------------------------------101 always @ (posedge clk )102 if( rst ) begin103 lmask1 <= 0;104 lmask0 <= 0;105 end else if(lasmask) begin106 lmask1 <= lgnt[1];107 lmask0 <= lgnt[0];108 end else begin109 lmask1 <= lmask1;110 lmask0 <= lmask0;111 end112113 assign comreq = lcomreq;114 assign gnt = lgnt;115 //----------------------------------------------------116 // Drive the outputs117 //----------------------------------------------------118 assign gnt3 = lgnt3;119 assign gnt2 = lgnt2;120 assign gnt1 = lgnt1;121 assign gnt0 = lgnt0;122123 endmodule

You could download file arbiter.v here

Testbench Code

1 `include "arbiter.v"2 module top ();34 reg clk;5 reg rst;6 reg req3;7 reg req2;8 reg req1;9 reg req0;10 wire gnt3;11 wire gnt2;12 wire gnt1;13 wire gnt0;1415 // Clock generator16 always #1 clk = ~clk;1718 initial begin19 $dumpfile ("arbiter.vcd");20 $dumpvars();21 clk = 0;22 rst = 1;23 req0 = 0;24 req1 = 0;25 req2 = 0;26 req3 = 0;27 #10 rst = 0;28 repeat (1) @ (posedge clk);29 req0 <= 1;30 repeat (1) @ (posedge clk);31 req0 <= 0;32 repeat (1) @ (posedge clk);33 req0 <= 1;34 req1 <= 1;35 repeat (1) @ (posedge clk);36 req2 <= 1;37 req1 <= 0;38 repeat (1) @ (posedge clk);39 req3 <= 1;40 req2 <= 0;41 repeat (1) @ (posedge clk);42 req3 <= 0;43 repeat (1) @ (posedge clk);44 req0 <= 0;45 repeat (1) @ (posedge clk);46 #10 $finish;

47 end4849 // Connect the DUT50 arbiter U (51 clk,52 rst,53 req3,54 req2,55 req1,56 req0,57 gnt3,58 gnt2,59 gnt1,60 gnt061 );6263 endmodule

Pri-Encoder - Using if-else Statement

1 //-----------------------------------------------------2 // Design Name : pri_encoder_using_if3 // File Name : pri_encoder_using_if.v4 // Function : Pri Encoder using If5 // Coder : Deepak Kumar Tala6 //-----------------------------------------------------7 module pri_encoder_using_if (8 binary_out , // 4 bit binary output9 encoder_in , // 16-bit input10 enable // Enable for the encoder11 );12 output [3:0] binary_out ;13 input enable ;14 input [15:0] encoder_in ;1516 reg [3:0] binary_out ;1718 always @ (enable or encoder_in)19 begin20 binary_out = 0;21 if (enable) begin22 if (encoder_in[0] == 1) begin23 binary_out = 1;24 end else if (encoder_in[1] == 1) begin25 binary_out = 2;26 end else if (encoder_in[2] == 1) begin27 binary_out = 3;28 end else if (encoder_in[3] == 1) begin29 binary_out = 4;30 end else if (encoder_in[4] == 1) begin31 binary_out = 5;

32 end else if (encoder_in[5] == 1) begin33 binary_out = 6;34 end else if (encoder_in[6] == 1) begin35 binary_out = 7;36 end else if (encoder_in[7] == 1) begin37 binary_out = 8;38 end else if (encoder_in[8] == 1) begin39 binary_out = 9;40 end else if (encoder_in[9] == 1) begin41 binary_out = 10;42 end else if (encoder_in[10] == 1) begin43 binary_out = 11;44 end else if (encoder_in[11] == 1) begin45 binary_out = 12;46 end else if (encoder_in[12] == 1) begin47 binary_out = 13;48 end else if (encoder_in[13] == 1) begin49 binary_out = 14;50 end else if (encoder_in[14] == 1) begin51 binary_out = 15;52 end53 end54 end5556 endmoduleYou could download file pri_encoder_using_if.v here

Encoder - Using assign Statement

1 //-----------------------------------------------------2 // Design Name : pri_encoder_using_assign3 // File Name : pri_encoder_using_assign.v4 // Function : Pri Encoder using assign5 // Coder : Deepak Kumar Tala6 //-----------------------------------------------------7 module pri_encoder_using_assign (8 binary_out , // 4 bit binary output9 encoder_in , // 16-bit input10 enable // Enable for the encoder11 );1213 output [3:0] binary_out ;14 input enable ;15 input [15:0] encoder_in ;1617 wire [3:0] binary_out ;1819 assign binary_out = ( ! enable) ? 0 : (

20 (encoder_in[0]) ? 0 :21 (encoder_in[1]) ? 1 :22 (encoder_in[2]) ? 2 :23 (encoder_in[3]) ? 3 :24 (encoder_in[4]) ? 4 :25 (encoder_in[5]) ? 5 :26 (encoder_in[6]) ? 6 :27 (encoder_in[7]) ? 7 :28 (encoder_in[8]) ? 8 :29 (encoder_in[9]) ? 9 :30 (encoder_in[10]) ? 10 :31 (encoder_in[11]) ? 11 :32 (encoder_in[12]) ? 12 :33 (encoder_in[13]) ? 13 :34 (encoder_in[14]) ? 14 : 15);3536 endmodule

Decoder - Using case Statement

1 //-----------------------------------------------------2 // Design Name : decoder_using_case3 // File Name : decoder_using_case.v4 // Function : decoder using case5 // Coder : Deepak Kumar Tala6 //-----------------------------------------------------7 module decoder_using_case (8 binary_in , // 4 bit binary input9 decoder_out , // 16-bit out10 enable // Enable for the decoder11 );12 input [3:0] binary_in ;13 input enable ;14 output [15:0] decoder_out ;1516 reg [15:0] decoder_out ;1718 always @ (enable or binary_in)19 begin20 decoder_out = 0;21 if (enable) begin22 case (binary_in)23 4'h0 : decoder_out = 16'h0001;24 4'h1 : decoder_out = 16'h0002;25 4'h2 : decoder_out = 16'h0004;26 4'h3 : decoder_out = 16'h0008;27 4'h4 : decoder_out = 16'h0010;28 4'h5 : decoder_out = 16'h0020;

29 4'h6 : decoder_out = 16'h0040;30 4'h7 : decoder_out = 16'h0080;31 4'h8 : decoder_out = 16'h0100;32 4'h9 : decoder_out = 16'h0200;33 4'hA : decoder_out = 16'h0400;34 4'hB : decoder_out = 16'h0800;35 4'hC : decoder_out = 16'h1000;36 4'hD : decoder_out = 16'h2000;37 4'hE : decoder_out = 16'h4000;38 4'hF : decoder_out = 16'h8000;39 endcase40 end41 end4243 endmoduleYou could download file decoder_using_case.v here

Decoder - Using assign Statement

1 //-----------------------------------------------------2 // Design Name : decoder_using_assign3 // File Name : decoder_using_assign.v4 // Function : decoder using assign5 // Coder : Deepak Kumar Tala6 //-----------------------------------------------------7 module decoder_using_assign (8 binary_in , // 4 bit binary input9 decoder_out , // 16-bit out10 enable // Enable for the decoder11 );12 input [3:0] binary_in ;13 input enable ;14 output [15:0] decoder_out ;1516 wire [15:0] decoder_out ;1718 assign decoder_out = (enable) ? (1 << binary_in) : 16'b0 ;1920 endmodule

Mux : Using assign Statement

1 //---------------------------------------------------

--2 // Design Name : mux_using_assign3 // File Name : mux_using_assign.v4 // Function : 2:1 Mux using Assign5 // Coder : Deepak Kumar Tala6 //-----------------------------------------------------7 module mux_using_assign(8 din_0 , // Mux first input9 din_1 , // Mux Second input10 sel , // Select input11 mux_out // Mux output12 );13 //-----------Input Ports---------------14 input din_0, din_1, sel ;15 //-----------Output Ports---------------16 output mux_out;17 //------------Internal Variables--------18 wire mux_out;19 //-------------Code Start-----------------20 assign mux_out = (sel) ? din_1 : din_0;2122 endmodule //End Of Module muxYou could download file mux_using_assign.v here

Mux : Using if Statement

1 //-----------------------------------------------------2 // Design Name : mux_using_if3 // File Name : mux_using_if.v4 // Function : 2:1 Mux using If5 // Coder : Deepak Kumar Tala6 //-----------------------------------------------------7 module mux_using_if(8 din_0 , // Mux first input9 din_1 , // Mux Second input10 sel , // Select input11 mux_out // Mux output12 );13 //-----------Input Ports---------------14 input din_0, din_1, sel ;15 //-----------Output Ports---------------16 output mux_out;17 //------------Internal Variables--------18 reg mux_out;19 //-------------Code Starts Here---------

20 always @ (sel or din_0 or din_1)21 begin : MUX22 if (sel == 1'b0) begin23 mux_out = din_0;24 end else begin25 mux_out = din_1 ;26 end27 end2829 endmodule //End Of Module muxYou could download file mux_using_if.v here

Mux : Using case Statement

1 //-----------------------------------------------------2 // Design Name : mux_using_case3 // File Name : mux_using_case.v4 // Function : 2:1 Mux using Case5 // Coder : Deepak Kumar Tala6 //-----------------------------------------------------7 module mux_using_case(8 din_0 , // Mux first input9 din_1 , // Mux Second input10 sel , // Select input11 mux_out // Mux output12 );13 //-----------Input Ports---------------14 input din_0, din_1, sel ;15 //-----------Output Ports---------------16 output mux_out;17 //------------Internal Variables--------18 reg mux_out;19 //-------------Code Starts Here---------20 always @ (sel or din_0 or din_1)21 begin : MUX22 case(sel )23 1'b0 : mux_out = din_0;24 1'b1 : mux_out = din_1;25 endcase26 end2728 endmodule //End Of Module mux

Encoder - Using if-else Statement

1 //-----------------------------------------------------2 // Design Name : encoder_using_if3 // File Name : encoder_using_if.v4 // Function : Encoder using If5 // Coder : Deepak Kumar Tala6 //-----------------------------------------------------7 module encoder_using_if(8 binary_out , // 4 bit binary output9 encoder_in , // 16-bit input10 enable // Enable for the encoder11 );12 //-----------Output Ports---------------13 output [3:0] binary_out ;14 //-----------Input Ports---------------15 input enable ;16 input [15:0] encoder_in ;17 //------------Internal Variables--------18 reg [3:0] binary_out ;19 //-------------Code Start-----------------20 always @ (enable or encoder_in)21 begin22 binary_out = 0;23 if (enable) begin24 if (encoder_in == 16'h0002) begin25 binary_out = 1;26 end if (encoder_in == 16'h0004) begin27 binary_out = 2;28 end if (encoder_in == 16'h0008) begin29 binary_out = 3;30 end if (encoder_in == 16'h0010) begin31 binary_out = 4;32 end if (encoder_in == 16'h0020) begin33 binary_out = 5;34 end if (encoder_in == 16'h0040) begin35 binary_out = 6;36 end if (encoder_in == 16'h0080) begin37 binary_out = 7;38 end if (encoder_in == 16'h0100) begin39 binary_out = 8;40 end if (encoder_in == 16'h0200) begin41 binary_out = 9;42 end if (encoder_in == 16'h0400) begin43 binary_out = 10;44 end if (encoder_in == 16'h0800) begin45 binary_out = 11;46 end if (encoder_in == 16'h1000) begin47 binary_out = 12;48 end if (encoder_in == 16'h2000) begin49 binary_out = 13;50 end if (encoder_in == 16'h4000) begin51 binary_out = 14;

52 end if (encoder_in == 16'h8000) begin53 binary_out = 15;54 end55 end56 end5758 endmoduleYou could download file encoder_using_if.v here

Encoder - Using case Statement

1 //-----------------------------------------------------2 // Design Name : encoder_using_case3 // File Name : encoder_using_case.v4 // Function : Encoder using Case5 // Coder : Deepak Kumar Tala6 //-----------------------------------------------------7 module encoder_using_case(8 binary_out , // 4 bit binary Output9 encoder_in , // 16-bit Input10 enable // Enable for the encoder11 );12 output [3:0] binary_out ;13 input enable ;14 input [15:0] encoder_in ;1516 reg [3:0] binary_out ;1718 always @ (enable or encoder_in)19 begin20 binary_out = 0;21 if (enable) begin22 case (encoder_in)23 16'h0002 : binary_out = 1;24 16'h0004 : binary_out = 2;25 16'h0008 : binary_out = 3;26 16'h0010 : binary_out = 4;27 16'h0020 : binary_out = 5;28 16'h0040 : binary_out = 6;29 16'h0080 : binary_out = 7;30 16'h0100 : binary_out = 8;31 16'h0200 : binary_out = 9;32 16'h0400 : binary_out = 10;33 16'h0800 : binary_out = 11;34 16'h1000 : binary_out = 12;35 16'h2000 : binary_out = 13;36 16'h4000 : binary_out = 14;37 16'h8000 : binary_out = 15;

38 endcase39 end40 end4142 endmodule