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    Digital System Design

    Verilog:Examples of Basic Components

    Dr. Bassam Jamil

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    2222

    Topics

    Combinational Designs

    Mux/Dec/Encoder

    Sequential Designs

    FFs/Latches/Counters/Shifters

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    Parameterized Mux Designs

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    Parameterized Comparator Design

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    Mux With Tri-State Output

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    Encoder Design (1)

    endmodule

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    Encoder Design (2)

    ad

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    Priority Encoder Design (1)

    Adaf

    endmodule

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    Priority Encoder Design (2)

    ad

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    Decoder Design (1)

    Design (1) Design (2)

    ad

    endmodule

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    Seven Segment Display

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    Flip-Flops(1)

    D

    clk

    q

    D

    clk

    q

    en

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    Flip-Flops (2)

    QD

    resetN

    enable

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    Flip-Flip (3)

    Synchronous Set/Reset FF Asynchronous Set/Reset FF

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    Latch Design

    Transparent latch does not change the output ifthe enable (or clk) is off

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    Register Design

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    Register with Generate Statement

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    Register Design: Parallel Load

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    Register Design: Shift Register

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    Barrel Shift Register

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    Universal Shift Register

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    Register File

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    Up-Down Counter with Parallel Load

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    Ring Counter


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