vlsi testing - supercomputer education research centreviren/e0286/testing27.pdf · apr 02, 2008...
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Apr 02, 2008 E0286@SERC 1
VLSI Testing Memory Test
Virendra SinghIndian Institute of Science
E0286: Testing and Verification of SoC Designs
Lecture 27
Apr 02, 2008 E0286@SERC 2
RAM Organization
OUTPUT BUFFER
b63
.
A
A5
0
.
.
BUFFERS
a0
a5
x0
x63
b0 b0
4 K Bits64 X 64 CellsCELL ARRAY
SENSEAMPLIFIER
TRI−STATE
COLUMN (Y) DECODER
s0 s0 s11 s11
11
R/W2
R/W1
CONTROL
R/W
INPUT
TRI−STATE
DATA IN DATABUS
DATABUS
BU
FF
ER
S
RO
W (
X)
DE
CO
DE
R
COLUMN ADDRESSBUFFERS
b63
CS
BIT−LINE PAIRS
RO
W A
DD
RE
SS
6A A. . .
y630y
DATA OUT
Apr 02, 2008 E0286@SERC 3
n bits
1 Mb4 Mb16 Mb64 Mb
256 Mb1 Gb2 Gb
n
0.060.251.014.03
16.1164.43128.9
n × log2n
1.265.54
24.16104.7451.0
1932.83994.4
n3/2
64.5515.41.2 hr9.2 hr
73.3 hr586.4 hr
1658.6 hr
n2
18.3 hr293.2 hr
4691.3 hr75060.0 hr
1200959.9 hr19215358.4 hr76861433.7 hr
Size Number of Test Algorithm Operations
Test Time
Apr 02, 2008 E0286@SERC 4
Faults found only in SRAMOpen-circuited pull-up deviceExcessive bit line coupling capacitance
ModelDRFCF
SRAM Fault Models
Apr 02, 2008 E0286@SERC 5
DRAM Only Fault Models
Faults only in DRAMData retention fault (sleeping sickness)Refresh line stuck-at faultBit-line voltage imbalance faultCoupling between word and bit lineSingle-ended bit-line voltage shiftPrecharge
and decoder clock overlap
ModelDRFSAFPSFCF
PSFAF
Apr 02, 2008 E0286@SERC 6
Behavioral (black-box) Model -- State machine modeling all memory content combinations --IntractableFunctional (gray-box) Model -- UsedLogic Gate Model -- Not used Inadequately models transistors & capacitorsElectrical Model -- Very expensiveGeometrical Model -- Layout Model
Used with Inductive Fault Analysis
Fault Modeling
Apr 02, 2008 E0286@SERC 9
SAFTFCFNPSF
FaultStuck-at faultTransition faultCoupling faultNeighborhood Pattern Sensitive fault*
Reduced Functional Faults
Apr 02, 2008 E0286@SERC 10
Test Condition: For each cell, read a 0 and a 1.
< /0> (< /1>)
A A
S0 S1
S0 S1
w0
State diagram of a good cell
w1w0 w1
w1
w0w1
w0
SA0 fault SA1 fault
Stuck-at Faults
Apr 02, 2008 E0286@SERC 11
Cell fails to make a 0 → 1 or 1 → 0 transition.
Test Condition: Each cell must have an ↑ transition
and a ↓ transition, and be read each time before
making any further transitions.
<↑/0>, <↓/1>
<↑/0>
transition fault
w0 S1S0 w0 w1
w1
Transition Faults
Apr 02, 2008 E0286@SERC 12
Coupling Fault (CF): Transition in bit j (aggressor) causes unwanted change in bit i (victim)2-Coupling Fault: Involves 2 cells, special case of k-Coupling Fault
Must restrict k cells for practicalityInversion (CFin) and Idempotent (CFid) Coupling Faults -- special cases of 2-Coupling FaultsBridging and State Coupling Faults involve any # of cellsDynamic Coupling Fault (CFdyn) -- Read or write on j forces i to 0 or 1
Coupling Faults
Apr 02, 2008 E0286@SERC 13
w0/i
S00 S01
S11S10
w1/ j
w1/ i w1/ i
w1/ i, w0/ j
w0/ i, w0/ j
w1/i, w1/ j
w0/i, w1/ j
w0/ i
w1/ j
w0/ j
w0/ j
State Transition Diagram of Two Good Cells, i and j
Apr 02, 2008 E0286@SERC 14
w0/ j
S00 S01
S11S10
w1/ i
w0/ jw0/ i, w0/ jw0/ i, w1/ j
w1/ i, w1/ j w1/ i, w0/ j
w0/ i w1/ i
w1/ j
w0/ i
w1/ j
State Transition Diagram for CFin
< ↑
; ↕
>
Apr 02, 2008 E0286@SERC 15
Aggressor cell or line j is in a given state y and that forces victim cell or line i into state x< 0;0 >, < 0;1 >, < 1;0 >, < 1;1 >
w1/ i, w1/ j
00S 01S
11S10S
w1/ iw1/ i
w0/ i
w1/ i, w0/ j
w0/ i, w0/ j w0/ j
w1/ jw0/ i
w1/ j
w0/ j
State coupling fault (SCF) <1 ; 1>
w0/ i, w1/ j
State Coupling Faults (SCF)
Apr 02, 2008 E0286@SERC 16
M0: { March element (w0)
}for cell := 0 to n -
1 (or any other order) do
write 0 to A [cell];M1: { March element (r0, w1)
}
for cell := 0 to n -
1 doread A [cell]; { Expected value = 0}write 1 to A [cell];
M2: { March element (r1, w0)
}for cell := n –
1 down to 0 do
read A [cell]; { Expected value = 1 }write 0 to A [cell];
March Test Elements
Apr 02, 2008 E0286@SERC 17
AlgorithmMATSMATS+
MATS++MARCH X
MARCH C-
MARCH AMARCH Y
MARCH B
Description{ (w0); (r0, w1); (r1) }
{ (w0); (r0, w1); (r1, w0) }{ (w0); (r0, w1); (r1, w0, r0) }
{ (w0); (r0, w1); (r1, w0); (r0) }{ (w0); (r0, w1); (r1, w0);
(r0, w1); (r1, w0); (r0) }{ (w0); (r0, w1, w0, w1); (r1, w0, w1);
(r1, w0, w1, w0); (r0, w1, w0) }{ (w0); (r0, w1, r1); (r1, w0, r0); (r0) }
{ (w0); (r0, w1, r1, w0, r0, w1);(r1, w0, w1); (r1, w0, w1, w0);
(r0, w1, w0) }
March Tests
Apr 02, 2008 E0286@SERC 18
•
Address decoding error assumptions:–
Decoder does not become sequential
–
Same behavior during both read and write•
Multiple ADFs
must be tested for
•
Decoders can have CMOS stuck-open faults
Cx
Cx
y
Multiple CellsFault 2
No Address to
xAccess Cell C Accessed with A
Fault 3
y
Accessed for Ax
Ay
Ax
No Cell
Ax
Fault 1
C
Fault 4
for Cell Cx
Ay C
Multiple Addresses
x
Address Decoder Faults
Apr 02, 2008 E0286@SERC 19
•
A March test satisfying conditions 1 & 2 detects all address decoder faults.
•
...
Means any # of read or write operations•
Before condition 1, must have wx element–
x can be 0 or 1, but must be consistent in test
Condition
1
2
March element
(rx, …, w x )
(r x , …, wx)
Theorem
Apr 02, 2008 E0286@SERC 20
Algorithm
MATSMATS+MATS++MARCH XMARCH C-MARCH AMARCH YMARCH B
SAF
AllAllAllAllAllAllAllAll
ADF
SomeAllAllAllAllAllAllAll
TF
AllAllAllAllAllAll
CFin
AllAllAllAllAll
CFid
All
CFdyn
All
SCF
All
March Test Fault Coverage
Apr 02, 2008 E0286@SERC 21
March Test Complexity
AlgorithmMATS
MATS+MATS++
MARCH XMARCH C-MARCH AMARCH YMARCH B
Complexity4n5n6n6n10n15n8n17n
Apr 02, 2008 E0286@SERC 22
MATS+: { M0: (w0); M1: (r0, w1); M2: (r1, w0) }
(f) Bad machine
(a) Good machine
(d) Bad machine
after M2.
after M0.(e) Bad machine
after M1.
(b) Good machine
0 0
0 000
000
1 1 11 1 11 1 1
0 0
0 000
000
0 0
0 000
000
1 1 11 1
1 1 10
0 0
0 000
000
after M0. after M1.(c) Good machine
after M2.
MATS+ Example Cell (2,1) SA0 Fault
Apr 02, 2008 E0286@SERC 23
MATS+: { M0: (w0); M1: (r0, w1); M2: (r1, w0) }
(a) Good machineafter M0.
(b) Good machineafter M1. after M2.
(d) Bad machineafter M0.
(e) Bad machineafter M1.
(f) Bad machine
0 0
0 00
000
1
0 0
0 000
000
1 1 11 1 11 1 1
0 0
0 000
000
0 0
0 00
000
11 1 1
1 11 1 11
(c) Good machine
after M2.
MATS+ Example Cell (2, 1) SA1 Fault
Apr 02, 2008 E0286@SERC 24
Cell (2,1) is not addressableAddress (2,1) maps onto (3,1), and vice versaCannot write (2,1), read (2,1) gives random data
MATS+: { M0: (w0); M1: (r0, w1); M2: (r1), w0 }
(a) Good machineafter M0.
0 0
0 000
000
(b) Good machineafter M1.
1 1 11 1 11 1 1
(c) Good machineafter M2.
0 0
0 000
000
(d) Bad machineafter M0.
0 0
0 00
000
X
(e) Bad machineafter M1 for cell (2, 1).
1 1 1
1X 0 0
0 0(f) Bad machine
after M1.
1 1 11 1
1 1 1X
0 0
0 00
000
X
(g) Bad machine after M2.
MATS+ Example Multiple AF: Addressed Cell Not Accessed;
Data Written to Wrong Cell
Apr 02, 2008 E0286@SERC 26
LFSR and Inverse Pattern LFSR
NOR gate forces LFSR into all-0 stateGet all 2n patterns
Normal LFSR:G (x) = x3
+ x + 1
Inverse LFSR:G (x) = x3
+ x2
+ 1
Apr 02, 2008 E0286@SERC 27
Up / Down LFSR•
Preferred memory BIST pattern generator
Satisfies March test conditions
X0
D Q MUX
0
1
MUX
0
1
MUX
0
1 D Q D Q
MUX
0
1
X1 X2
Up/Down
Apr 02, 2008 E0286@SERC 28
Up / Down LFSR Pattern Sequences
Up Counting000100110111011101010001
Down Counting000001010101011111110100
Apr 02, 2008 E0286@SERC 29
Mutual ComparatorTest 4 or more memory arrays at same time:
Apply same test commands & addresses to all 4 arrays at same timeAssess errors when one of the di (responses) disagrees with the others
Apr 02, 2008 E0286@SERC 30
Mutual Comparator System
Memory BIST with mutual comparator
Benefit: Need not have good machine response stored or generated
Apr 02, 2008 E0286@SERC 31
SRAM BIST with MISR•
Use MISR to compress memory outputs
•
Control aliasing by repeating test:With different MISR feedback polynomialWith RAM test patterns in reverse order
•
March test:
{ (w Address); (r Address); (w Address);(r Address); (r Address); (w Address);(r Address); (r Address) }
•
Not proven to detect coupling or address decoder faults
Apr 02, 2008 E0286@SERC 33
LFSR and Inverse Pattern LFSR
NOR gate forces LFSR into all-0 stateGet all 2n patterns
Normal LFSR:G (x) = x3
+ x + 1
Inverse LFSR:G (x) = x3
+ x2
+ 1
Apr 02, 2008 E0286@SERC 34
Up / Down LFSR•
Preferred memory BIST pattern generator
Satisfies March test conditions
X0
D Q MUX
0
1
MUX
0
1
MUX
0
1 D Q D Q
MUX
0
1
X1 X2
Up/Down
Apr 02, 2008 E0286@SERC 35
Up / Down LFSR Pattern Sequences
Up Counting000100110111011101010001
Down Counting000001010101011111110100
Apr 02, 2008 E0286@SERC 36
Mutual ComparatorTest 4 or more memory arrays at same time:
Apply same test commands & addresses to all 4 arrays at same timeAssess errors when one of the di (responses) disagrees with the others
Apr 02, 2008 E0286@SERC 37
Mutual Comparator System
Memory BIST with mutual comparator
Benefit: Need not have good machine response stored or generated
Apr 02, 2008 E0286@SERC 38
SRAM BIST with MISR•
Use MISR to compress memory outputs
•
Control aliasing by repeating test:With different MISR feedback polynomialWith RAM test patterns in reverse order
•
March test:
{ (w Address); (r Address); (w Address);(r Address); (r Address); (w Address);(r Address); (r Address) }
•
Not proven to detect coupling or address decoder faults