wide-band fine-resolution dco with an active inductor and...

ETRI Journal, Volume 33, Number 2, April 2011 © 2011 YoungGun Pu et al. 201

This paper presents a wide-band fine-resolution digitally controlled oscillator (DCO) with an active inductor using an automatic three-step coarse and gain tuning loop. To control the frequency of the DCO, the transconductance of the active inductor is tuned digitally. To cover the wide tuning range, a three-step coarse tuning scheme is used. In addition, the DCO gain needs to be calibrated digitally to compensate for gain variations. The DCO tuning range is 58% at 2.4 GHz, and the power consumption is 6.6 mW from a 1.2 V supply voltage. An effective frequency resolution is 0.14 kHz. The phase noise of the DCO output at 2.4 GHz is –120.67 dBc/Hz at 1 MHz offset.

Keywords: Wide tuning range, active inductor, automatic three-step coarse and gain tuning loop, fine-resolution, digitally controlled oscillator (DCO).

Manuscript received Apr. 8, 2010; revised Sept. 1, 2010; accepted Sept. 20, 2010. This work was sponsored by ETRI System Semiconductor Industry Promotion Center,

Human Resource Development Project for SoC Convergence. YoungGun Pu (phone: +82 2 452 6229, email: [email protected]), AnSoo Park

(email: [email protected]), Joon-Sung Park (email: [email protected]), and Kang-Yoon Lee (email: [email protected]) are with the Department of Electronic Engineering, Konkuk University, Seoul, Rep. of Korea.

Yeon-Kug Moon (corresponding author, email: [email protected]) is with the Department of Biomicrosystem Technology, Korea University, Seoul, Rep. of Korea.

SuKi Kim (email: [email protected]) is with the Department of Electronics Engineering, Korea University, Seoul, Rep. of Korea.

doi:10.4218/etrij.11.0110.0209

I. Introduction

In submicron technology, digital radio frequency (RF) architecture will be adopted to reduce the cost, power consumption, and required area of the system. As the minimum feature size decreases, the supply voltage will also decrease. While an analog phase-locked loop (PLL) needs to be re-designed as the process is changed, a digital PLL can be easily translated into a new process. The digital PLL can be integrated into the digital RF transceiver. There are some issues in the digital PLL architecture. The digitally controlled oscillator (DCO) is one of the most critical blocks in the digital PLL. Conventionally, the frequency of the DCO is tuned with a varactor capacitance whose physical size is limited to several aFs. To overcome this limitation, a sigma-delta modulator is used to implement the fine capacitance [1]. Nevertheless there is still a limitation in the frequency resolution due to a physical limitation in the varactor size. In this case, the dithering bits of the sigma-delta modulator need to be increased in order to implement a finer resolution. Therefore, the area and power consumption also increases. In this paper, an active inductor is used for the frequency control, overcoming the minimum frequency resolution problem.

Typically, several LC-oscillators are used to cover the wide frequency band [2]. In this case, the area required and the power consumption can be a problem. So, several techniques are used to cover the wide frequency range with a single LC-oscillator. If the tuning range is wide, it comes at the cost of increased hardware and power consumption because the tuning range must be increased by using a capacitor array. The automatic coarse tuning scheme is typically used to widen the tuning range. The variation of the DCO gain, KDCO, is large in wide range applications. The automatic calibration of the DCO

Wide-Band Fine-Resolution DCO with an Active Inductor and Three-Step Coarse Tuning Loop

YoungGun Pu, AnSoo Park, Joon-Sung Park, Yeon-Kug Moon, SuKi Kim, and Kang-Yoon Lee

202 YoungGun Pu et al. ETRI Journal, Volume 33, Number 2, April 2011

gain is necessary to guarantee the same loop bandwidth for the phase noise and lock-time performances regardless of the channel frequency. This paper presents a wide-band fine-resolution DCO with an active inductor using an automatic three-step coarse and gain tuning loop.

II. Wide-Band Fine-Resolution DCO Architecture

Figure 1(a) shows the block diagram of the proposed DCO with an active inductor. It is composed of the DCO core, a sigma-delta modulator, and a coarse tuning digital controller. A 3rd order MASH type sigma-delta modulator is used with five dithering bits (FDTW<4:0>). Figure 1(b) shows the structure of the sigma-delta modulator [1]. Generally, as the operation frequency of the sigma-delta modulator is increased, the noise shaping characteristic would be better. However, because the sigma-delta modulator is hard to design at high clock frequency, SDM_CLK is determined to be 600 MHz, which can be simply generated though the divide-by-4 circuit. The delay of the critical path is minimized to guarantee the stable operation at 600 MHz.

Figure 2 shows the schematic of the DCO core. It consists of an active inductor, a passive inductor, a cap bank, and a negative-Gm. The active inductor is used for the wide-frequency range tuning and narrow-frequency range tuning control. The cap bank, which is composed of switches and MIM capacitors, provides the mid-frequency tuning range of the DCO. To meet the phase noise performance requirements,

Fig. 1. (a) Block diagram of proposed DCO with active inductorand (b) structure of sigma-delta modulator.

DCO_ OUT

DCO_ OUTB~

Coarse tuning digital-

controller

Sigma delta modulator

CDTW <63:0>

FDTW<4:0>

DCO core DCO tuning word (DTW)

<68:0>

SDM_OUT

/4

SDM

_CLK

GC

ON

T<9:

0>

RC

ON

T<9:

0>

DC

ON

T<19

:0>

CA

PS<9

:0>

FCO

NT

(a)

Combiner

FDTW<4:0>

SDM_CLK (600 MHz)

C1 carry-out C2 carry-out

C3 carry-out

SDM_OUT

(b)

Fig. 2. Schematic of proposed DCO core.

Passive inductor

Active inductor

Cap bank Negative-Gm

BIAS

Negative-Gm

MP1 MP2

SDM_OUT, CDTW <63:0>DCONT<19:0>

FCONT GCONT<9:0>RCONT<9:0>

DCO_OUTB

CAPS<9:0>

DCO_OUT

MN1 MN2

MN3

Fig. 3. (a) Transformation of series network to parallel networkand (b) transformation of parallel two inductors to four parallel components.

Passive inductor

Activeinductor

LS RS

LP

RP

LS1 RS1

LS2 RS2

LP1

LP2

RP1

RP2

LPEQ

RPEQ

(a)

(b)

a passive inductor is also used.

Figure 3(a) shows the transformation of the series network to a parallel network [3]. From the equivalence between two networks, RP and LP can be calculated as

2 2P S S/ ,R L ω R= (1)

2 2 2P S S S S(1 / ) ,L L R L ω L= + ≈ (2)

where LS and RS are the series inductance and resistance, respectively. The quality factor of two networks is typically greater than 3, whose definition is presented in (3).

Q = LSω/RS = RP/ωLP. (3) Figure 3(b) shows the transformation of two parallel

inductors to four parallel components. The equivalent resistance can be calculated from (1) by

PEQ P1 P2 P1 P2

2 2 2S1 S2 S1 S2 S2 S1

/ ( )

( ) / ( ).

R R R R R

L L L R L Rω

= +

= +

(4)

ETRI Journal, Volume 33, Number 2, April 2011 YoungGun Pu et al. 203

Fig. 4. Schematic of proposed active inductor.

FCONT

SDM_OUT

DCO_OUT

M1 M2

M3 M4

M5 M6

R9 R8

DCONT<19:0>

RCONT <9:0>

R0

GCONT<9:0>

Active inductorcontrol bank

DCO gain control bank

M9 M10

FCONT

DCONT <19:0>

FCDTW <64:0> FCDTW <64:0>

Active inductor control bank

V0 V9

CDTW<63> R9aR8a

RCONT <9:0>

R0a

V0a V9a

R9b R8b

RCONT <9:0>

R0b V0b V9b

CDTW<0>

FCDTW<0> FCDTW<1> FCDTW<64>

ID11

M11 <19:0>

M12 <19:0>

ID9

Cell_OUT Cell_OUTB

M7 <64:0>

M8 <64:0>

ID7

DCO_OUTB

Cell_OUT Cell_OUTB

The equivalent inductance can be calculated from (3) by

PEQ P1 P 2 P1 P2 S1 S2 S1 S2/ ( ) / ( ).L L L L L L L L L= + = + (5)

Thus, the total quality factor QP can be calculated as

P PEQ PEQ

2 2S1 S2 S1 S2 S1 S2 S2 S1

/

( ) / ( ).

Q R ωL

L L L L L R L Rω

=

= + +

(6)

Thus, the total quality factor QP is determined by two inductances and quality factors of two inductors when the passive inductor is placed in parallel with the active inductor.

The quality factor Q2 of the active inductor used in this design is from 3 to 4.5 in the frequency tuning range and LS2 and RS2 are 3 nH and 15 Ω, respectively. The self-resonant frequency is 2.98 GHz. For example, when the quality factor Q1 of the passive inductor is around 10 at 2.4 GHz and LS1 and RS1 are 1 nH and 1.5 Ω, respectively, QP is 6.31 from (6).

Thus, by using the passive inductor in parallel with the active inductor, the quality factor can be increased resulting in the improvement of the phase noise performance.

Figure 4 shows the schematic of the active inductor. It is a differentially configured gyrator-C active inductor [4]. The

inductance of the active inductor is given by

eq gs1 gs3 wire dsTot 1 3 dsTot2( ) (2 ),m mL C C C G g g G= + + + − (7)

dsTot ds5 ds7 ds9 ds11 dsGCB,G G G G G G= + + + + (8)

ds7 D7 ,G Iλ≅ (9)

where Cwire is the parasitic wire capacitance for the tuning bank and is minimized with the careful layout. Gds5, Gds7, Gds9, and Gds11 are the drain conductances of M5, M7, M9, and M11 in Fig. 4, respectively. GdsGCB is the PMOS (MG) drain conductance of the DCO gain control cell in the DCO gain control bank (see Fig. 5). λ is channel-length modulation coefficient of M7. From (7), the inductance (Leq) can be tuned by varying Gds5, Gds7, Gds9, Gds11, and GdsGCB. Gds7 is controlled by ID7 from (9). Although (9) is an equation for the saturation region, Gds7 is also controlled by ID7 in the non-saturation region. Although Leq depends on gm1 and gm3, it would be better to control the drain conductance, GdsTot, rather than gm1 and gm3, because the drain conductance has the linear relationship with ID. The variation of gm1 and gm3 can be also compensated by the automatic three-step coarse and gain tuning, which will be presented in section


Fig. 5. Schematic of DCO gain control bank.

GCONT<9>

GCONTB<9>

DCO gain control cell_0

DCO gaincontrol cell_9

Cell_OUT Cell_OUTB

GCONT<0>

GCONT <9>

DCO gain control cell_9

FCDTW <64:0>

DCO gain control bank

FCDTW <64:0>

GCONT<9> GCONTB<9>

IDGCB GCONTB<9>

MG1<0> Cell_OUT Cell_OUTB

MG2<0>

FCDTW<0> FCDTW<64>

IDGCB

MG1<64>

Cell_OUT Cell_OUTB

MG2<64>

GCONT<9>

III. As mentioned above, Gds9, Gds11, and GdsGCB are also controlled by ID9, ID11, and IDGCB, respectively. ID is dependent on the gate voltage and the size of the MOS (W/L). Thus, the method for the inductance tuning is to control the drain conductance Gds7, Gds9, Gds11, and GdsGCB except Gds5 by the gate voltage and the size of the MOS. The gate of M5 is connected to GND to prevent the gate node of M1 and M3 from floating and operate even when all the PMOS are turned off in the active inductor because the floating node is very sensitive to the digital noise. ID7, ID9, and ID11 are controlled by the FCDTW<64:0>, FCONT, and DCONT<19:0> in the active inductor control bank, respectively. IDGCB is controlled by the GCONT<19:0> in the DCO gain control bank.

Figure 5 shows the complete schematic of the gain control bank of the proposed DCO. It is composed of the ten DCO gain control cell arrays which are controlled by the signals from the GCONT<9:0>. When the GCONT<N> is high, the gate of the PMOS (M1, M2) is connected to the FCDTW<64:0>. However, if the GCONT<N> is low, the gate of PMOS (M1, M2) is connected to the VDD to disable the corresponding DCO gain control cell. The switches in the gain control cell are connected to the gate of the PMOS to reduce the degradation of the parasitic capacitance of the switches. The gain control bank is used to adjust KDCO at the wide frequency tuning range. In order to compensate for the variation of KDCO, the number of active DCO gain control cells is controlled by the automatic DCO gain tuning. Thus, the drain conductance (GdsGCB) is increased or decreased in the active inductor.

Fig. 6. Principle of adjusting frequency resolution.

RCONT<9>: Min. frequency resolution

Normalized gate voltage

Min.

Max.

V VDD

Freq

uenc

y (H

z)

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 (V9) (V8) (V7) (V6) (V5) (V4) (V3) (V2) (V1) (V0)

RCONT<0>: Max. frequency resolution

Figure 6 shows the principle of adjusting frequency resolution. The CDTW<63:0> and SDM_OUT are mapped to FCDTW<64:0> whose voltage levels are determined by RCONT<9:0> as shown in Fig. 4. The corresponding voltages are one of ten levels (V0 through V9) which are implemented with the resistor string (R0 through R9). The RCONT<9:0> are automatically controlled by the coarse tuning digital-controller in Fig. 1(a).

The adjustment of the voltage level corresponds to the fine frequency resolution of the DCO. For example, when the code value of RCONT<9:0> is “1000000000” and value of the SDM_OUT is high, the SDM_OUT is mapped to FCDTW<0> whose voltage level is V9. It can be calculated as

99 9

0

0.1,ii

RV VDD VDD

R=

= × = ×∑

(10)

where all resistors (R0 through R9) has the same value, and VDD is the supply voltage. In this case, the FCDTW<0> has the minimum frequency resolution.

III. Automatic Three-Step Coarse and DCO Gain Tuning Loop

The automatic three-step coarse and gain tuning procedure is as follows. Its principle is shown in Fig. 7.

Step 1. The 1st coarse tuning is the wide-frequency range tuning. The DCO frequency is measured through the coarse tuning digital-controller, as shown in Fig. 1(a). The optimum center frequency is selected by the FCONT adjusting the large inductance value of the active inductor. Thus, Gds9 is controlled by FONT in this step, as shown in Fig. 4. The frequency tuning range of the 1st coarse tuning is 0.5 GHz. The active inductor tuning method is used in step 1 in order to reduce the area of the metal-insulator-metal (MIM) capacitor used in step 2. The


Fig. 7. Concept of proposed three-step coarse and gain tuning.

FCONT is determined.

Step 4: DCO gain tuning

Freq. 2 Freq. 1

GCONT<9:0>, RCONT <9:0> are determined.

Freq. 2 –Freq. 1

DTW2 –DTW1 DTW<68:0>

FCONT

Center freq. 1

Center freq. 2

DCONT<19:0>

Step 1: 1st coarse tuning

Step 2: 2nd coarse tuning

Step 3: 3rd coarse tuning

Freq

uenc

y “0”

“1” Wide-tuning range

Freq

uenc

y CAPS<9:0>

Mid-tuning range

DTW<68:0> DTW<68:0>

(a) (b)

Freq

uenc

y

DTW<68:0>

(d) (c) DTW1 DTW2

KDCO=

Freq

uenc

y

Narrow-tuning range

DCONT<19:0> is determined.

CAPS <9:0> is determined.

0.5 GHz 1.4 GHz

0.14 kHz/LSB

0.9 GHz

2.7 GHz135 kHz/LSB

active inductor can cover the same frequency tuning range with smaller area than the MIM capacitor. If a very large MIM capacitor is used, it leads to reduction of the negative-Gm and voltage swing. Therefore, to alleviate the problem, an additional scheme is required to compensate for reduced negative-Gm, increasing the current consumption and necessitating a complicated frequency tuning method of DCO. In addition, it is better to perform the active inductor tuning in step 1 prior to the MIM capacitor tuning because the optimum active inductance value should be determined first for larger voltage swing and better phase-noise performance. The oscillation frequency of the DCO is determined by the product of overall inductance and capacitance, where the overall inductance is the parallel combination of active inductance and passive inductance. Since the quality factor of the DCO is dominated by the inductor and the quality factor of the overall inductor is determined by the active inductor, the optimum active inductor should be selected first, and MIM capacitance should be selected afterward.

Step 2. The 2nd coarse tuning is the mid-frequency range tuning. In this step, the MIM capacitances of the cap bank are controlled by CAPS<9:0>. The optimum MIM capacitances are selected through the 2nd coarse tuning process after the 1st coarse tuning is completed. The frequency tuning range of the 2nd coarse tuning is about 0.9 GHz.

Step 3. The 3rd coarse tuning is the narrow-frequency range tuning. Because the frequency step of the 2nd coarse tuning is several MHz and too coarse, additional fine-step tuning is required. At the 3rd coarse tuning step, DCONT<19:0> is determined to select the optimum frequency curve between the frequency curves at the 2nd coarse tuning step. In this step, Gds11 is controlled by DCONT<19:0> to adjust the inductance

DCO_DIVK

Fig. 8. Automatic three-step coarse and gain tuning loop of proposed DCO.

DCO

Reference divider

Digital comparator

~Three-step coarse and gain tuning controller

Coarse tuning

map table

3-step coarse and gain tuning loop

DCO gain tuning map

table

MUX

DCO_OUT

DCO_OUTB/2

15-bit counter

REF_CLKCOM_CLK

DEN_CLK

CH_Freq <14:0>

UP/DN

Gain_Max Gain_Min Channel frequency

DCO-CNT<14:0>

RST

_CN

T EN

_CN

T

GCONT<9:0> RCONT<9:0>

DCONT<19:0> CAPS<9:0>

FCONT

of the active inductor, as shown in Fig. 4. As a result, the frequency resolution of the 3rd coarse tuning is about 135 kHz/LSB.

Step 4. The DCO gain tuning begins when the three-step coarse tuning is completed. The KDCO, which is defined as the frequency deviation of the DCO with respect to a 1-LSB change, is equal to the frequency resolution. Thus, the KDCO is controlled by the value of the signal consisting of the RCONT<9:0> and the GCONT<9:0>, which adjust the frequency resolution. As shown in Fig. 6(d), the KDCO can be estimated by dividing the difference of Freq. 2 and Freq. 1 by the difference of DTW2 and DTW1. It is measured and calculated though the coarse tuning digital-controller. Then, the RCONT<9:0> and the GCONT<9:0> are adjusted so the KDCO

can reach its reference boundary. Figure 8 shows the automatic three-step coarse and gain

tuning loop. Most of the blocks can be shared between the automatic three-step coarse and gain tuning loop. When the frequency tuning range of the DCO is wide range, the variation of the DCO gain, KDCO, is very large depending on the frequency. Thus, the DCO gain control bank in Fig. 5 is required for the automatic DCO gain tuning loop. The KDCO can be calculated with a 15-bit counter and digital blocks that can be shared with the three-step coarse tuning block. Therefore, no additional hardware is required for the automatic DCO gain tuning loop.

When the digital-PLL receives the channel information, the coarse tuning reference table converts the channel information to the appropriate timing parameter for the three-step coarse tuning. The coarse tuning digital-controller works with the


Fig. 9. Timing diagram of 2nd coarse tuning loop.

Stage 9: CAPS<9> is determined.

Stage 8: CAPS<8> is determined.

Stage 0:CAPS<0> is determined.

1

1000000000 1100000000

00000000001111111111

0000011111

0000011111

Step 2: 2nd coarse

tuning CAPS<9:0>

Step 1: 1st coarse

tuning FCONT: 1

Step 3:3rd coarse

tuning DCONT<19:0>

Step 4: Gain

tuning RCONT<9:0> GCONT<9:0>

Step 5:Fine

tuningDTW<68:0>

REF_CLK

CNT_EN

DCO_DIVK

COM_CLK

DEN_CLK

RST_CNT

FCONT

CAPS<9:0>

DCONT<19:0>

RCONT<9:0>

GCONT<9:0>

reference clock signal (REF_CLK) to generate RST_CNT, CNT_EN, DEN_CLK, and COM_CLK signals. Since the coarse tuning process involves frequency tracking, the 15-bit counter is used to estimate the period of the DCO. This result, DCO_CNT<14:0>, is compared with the channel reference number, CH_Freq<14:0>, generated from the coarse tuning reference table based on the channel frequency. The frequency of DCO is detected through the 15-bit counter and is compared with the reference value. In each step, coarse and gain tuning control signals (FCONT, CAPS<9:0>, DCONT<19:0>, RCONT<9:0>, and GCONT<9:0>) are determined digitally based on the comparison result. After the three-step coarse and gain tuning, the DTW<68:0> is adjusted to finely tune the phase and frequency of the DCO at the fine tuning stage.

Figure 9 shows the timing diagram of the 2nd coarse tuning loop when FCONT is determined as “1” after the 1st coarse tuning. The 15-bit counter is periodically reset by the RST_CNT. This counting operation is masked by the CNT_EN signal. The 15-bit counter is enabled only when the CNT_EN is high. When the output of the counter is smaller than the channel reference number, CH_Freq<14:0>, the UP signal asserted at the rising edge of COM_CLK so as to make the frequency of the DCO higher. The UP/DOWN signals are used to decide the coarse and gain tuning control signals in the

Fig. 10. Chip microphotograph.

DCO

SDM+ Digital

controller

500 µm

340 µm

330 µm

330 µm

each tuning controller.

In Fig. 9, we assume that the counting value (DCO_ CNT<14:0>) is less than the desired channel frequency (CH_Freq<14:0>) when the code value of CAPS<9:0> is “1000000000”. The code value of CAPS<9> is determined as “1” in stage 9 of the 2nd coarse tuning and the code value of CAPS<8> is determined as “1” in stage 8 of the 2nd coarse tuning. The code value of CAPS<9:0> is changed from “1000000000” to “1100000000” at the falling edge of RST_CNT signal. The CAPS<9:0> is selected through the 2nd coarse tuning process by fixing the code values of other signals (FCONT, DCONT<19:0>, RCONT<9:0>, and GCONT <9:0>). After ten cycles of the 2nd coarse tuning, the 3rd coarse tuning is started. The coarse and gain tuning signals are determined through the four steps before the fine tuning.

IV. Experimental Results

This chip was fabricated using the CMOS process with 0.13 µm technology, a single poly layer, six layers of metal, the option of MIM capacitors, and high sheet resistance poly resistors. The chip microphotograph is shown in Fig. 10. The total area of the DCO core, sigma-delta modulator, and coarse tuning digital-controller is 0.28 mm2.

Figure 11 shows the measured tuning curve of the DCO after the three-step coarse and gain tuning. The frequency tuning range that can be achieved with the planar passive inductor and capacitance tuning is 0.9 GHz. As a three-step coarse tuning scheme is used, the tuning range can be widened by 0.5 GHz


Fig. 11. Measured tuning curve of DCO after three-step coarseand gain tuning.

FDTW<4:0>

2.0

2.2

2.4

2.6

2.8

3.0

3.2

3.4

3.6

0 4 8 12 16 20 24 28

Narrow-tuning range (2.7 MHz)

Mid-tuning range (0.9 GHz)

Wide-tuning range (1.4 GHz)

DCO gain tuning (0.14 kHz/LSB)

Slope: KDCO= 0.14 kHz/LSB

3rd coarse tuning (2.7 MHz)

2nd coarse tuning (0.9 MHz)

1st coarse tuning (1.4 MHz)

DC

O o

utpu

t fre

quen

cy (G

Hz)

Fig. 12. Output spectrum of DCO.

–11.8 dBm @ 2.4 GHz

Atten 10 dB RL 0 dBm

MKR –11.83 dBm 2.400048 GHz 10 dB/

Center 2.400048 GHz RBW 30 kHz *VBW 3.0 kHz

SPAN 5.000 MHz SWP 140 ms

under the same capacitance value. This has the effect of widening the tuning range without using extra capacitance.

The frequency resolution for the 1-LSB of the CDTW<63:0> is 4.6 kHz. Thus, the effective time-averaged frequency resolution done by the 5-bit SDM can be calculated as

fΣ = 4.6 kHz / 25 = 0.14 kHz. (11)

From (11), the KDCO is about 0.14 kHz/LSB because the frequency resolution for the 1-LSB of the DTW<68:0> is 0.14 kHz.

Figure 12 shows the output spectrum of the DCO when the three-step coarse and gain tuning is enabled. The output power level of the DCO is –11.8 dBm at 2.4 GHz. The phase noise of a free-running DCO output at 2.4 GHz is –120.67 dBc/Hz at 1 MHz offset as shown in Fig. 13.

When the output frequencies are 2.1 GHz and 3.5 GHz, the phase noise at 1 MHz offset are –121.2 dBc/Hz and –116.1 dBc/Hz, respectively. The figure of merit with the frequency

Fig. 13. Measured phase noise of DCO.

–120.67 dBc/Hz@ 1 MHz offset

10 dB/ RL –50 dBc/Hz

Spot frq=1.00 MHz –120.67 dBC/Hz

10 kHz Frequency offset from 2.400 GHz carrier

10 MHz

Table 1. Summary of measured performance.

[1] [5] [6] This work

Process 0.13 μmCMOS

0.18 μm CMOS

65 nmCMOS

0.13 μmCMOS

Supply voltage (V) 1.5 1.8 1.1 1.2 Power consumption

(mW) 3.45 5 3.3 6.6

Center frequency (GHz) 2.4 3.8 10 2.4

Tuning range (%) 20.8 26.3 10 58 Frequency resolutionwithout SDM (kHz)

23 20 1,030 4.6

Phase noise @ 1 MHz (dBc/Hz)

–117.0 –123

@1.2 MHz –102 –120.67

FOMT (dBc/Hz) –185.6 –194.4 –176.8 –195.3

Area (mm2) 0.54 N/A 0.02 0.28

tuning range (FOMT) for the DCO can be calculated using

oT offset

offset

DC

( ) 20log( )

10log( ) 20log( ),1 mW 10

fFOM PN f

fP FDR

= −

+ −

(12)

where foffset is the offset frequency, fo is the oscillation frequency, PN (foffset) is the phase noise found in the foffset, PDC is the DC power consumption, and the FDR is the frequency tuning range in a percentage. The performance of the proposed DCO is summarized in Table 1. The performance of the proposed DCO is summarized in Table1. The phase noise performance of this work is better than that of [5], and the frequency resolution of the DCO is the smallest of all. In addition, the tuning range of the proposed DCO is the widest and FOMT of this work is the best among the references.


V. Conclusion

This paper presents a wide-band fine-resolution digitally controlled oscillator (DCO) with an active inductor using an automatic three-step coarse and gain tuning loop. To control the frequency of the DCO, the transconductance of the active inductor is tuned digitally. To cover the wide tuning range, a three-step coarse tuning loop is used. At the same time, the DCO gain needs to be calibrated digitally to compensate for the gain variations. The tuning range of the DCO is 2.1 GHz to 3.5 GHz with the effective frequency resolution of 0.14 kHz. The power consumption is 6.6 mW from a 1.2 V supply. The phase noise of the DCO output at 2.4 GHz is to –120.67 dBc/Hz at 1 MHz offset.

References

[1] R.B. Staszewski et al., “Digitally Controlled Oscillator (DCO)-Based Architecture for RF Frequency Synthesis in a Deep-Submicrometer CMOS Process,” IEEE Trans. Circuits Syst. II, vol. 50, no. 11, Nov. 2003, pp. 815-828.

[2] D. Leenaerts et al., “A SiGe BiCMOS 1 ns Fast Hopping Frequency Synthesizer for UWB Radio,” Proc. IEEE Int. Solid-State Circuits Conf. Dig., vol. 1, Feb. 2005 pp. 202-593.

[3] B. Razavi, Design of Analog CMOS Integrated Circuits, New York: McGRAW-Hill, 2001.

[4] L. Lu, H. Hsieh, and Y. Liao, “A Wide Tuning-Range CMOS VCO with a Differential Tunable Active Inductor,” IEEE Trans. Microwave Theory Tech., vol. 54, no. 9, Sept. 2006, pp. 3462-3468.

[5] S. Wang et al., “A Noise Reduced Digitally Controlled Oscillator Using Complementary Varactor Pair,” Proc. IEEE Int. Symp. Circuits Syst., May 2007, pp. 937-940.

[6] N. Da Dalt et al., “A 10b 10 GHz Digitally Controlled LC Oscillator in 65 nm CMOS,” Proc. IEEE Int. Solid-State Circuits Conf. Dig., Feb. 2006, pp. 669-678.

[7] Y. Koo et al., “A Fully Integrated CMOS Frequency Synthesizer with Charge-Averaging Charge Pump and Dual-Path Loop Filter for PCS- and Cellular-CDMA Wireless Systems,” IEEE J. Solid-State Circuits, vol. 37, no. 5, May 2002, pp. 536-542.

YoungGun Pu received his BS and MS from the Department of Electronic Engineering at Konkuk University, Seoul, Korea, in 2006 and 2008, where he is currently working toward a PhD in electronic engineering. His research interests include CMOS fully integrated frequency synthesizers and oscillators and

transceivers for low-power mobile communication.

AnSoo Park received the BS from the Department of Electronic Engineering at Konkuk University, Seoul, Korea, in 2009, where he is currently working toward his MS in electronic engineering. His research interests are in CMOS RF design, high-speed analog integrated circuit design, frequency synthesizer,

and other techniques of analog signal processing.

Joon-Sung Park received his BS from the Department of Electronic Engineering at Konkuk University, Seoul, Rep. of Korea, in 2008, where he is currently working toward his MS in electronic engineering. His research interest is focused on CMOS RF/analog integrated circuit design for wireless application.

Yeon-Kug Moon received the BS and MS in electronics engineering from Inha University, Inchon, Rep. of Korea, in 1998 and 2000, respectively. In 2008, He joined Korea University and ULSI Lab in Seoul, Rep. of Korea, where he is working toward the PhD. In October 1999, he joined ARALION, where he

was involved in INFINIBAND chipset development. From 2001 to 2006, he joined the RFIC group in System LSI of Samsung Electronics, where he worked on RFIC development for multimode multiband RF chipsets. Since April 2006, he has been a member of Wireless Network Research Center of Korea Electronics Technology Institute (KETI). His research interests are in the area of RF and analog integrated circuit design for wireless transceivers.

SuKi Kim received the BS and MS in electrical engineering from Korea University, Seoul, Rep. of Korea, in 1973 and 1975, and the PhD in electrical engineering from the University of Minnesota, Minneapolis, in 1980. From 1980 to 1985, he was with AT&T Bell Laboratory. From 1988 to 1990, he was with Hughes,

Germantown, MD. During 1990, he was the Vice President of Samsung Electronics, Inc., Korea. From 1990 to 1995, he was an adjunct professor at the University of Minnesota. Since 1995, he has been with the Department of Electronics Engineering, Korea University. His current research interests include mixed mode IC design and the virtual prototyping of microsystems for system-on-chip applications.


Kang-Yoon Lee received his BS, MS, and PhD from the School of Electrical Engineering at Seoul National University, Seoul, Rep. of Korea, in 1996, 1998, and 2003, respectively. From 2003 to 2005, he was with GCT Semiconductor Inc., San Jose, CA, where he was a Manager of the Analog Division and

worked on the design of the CMOS frequency synthesizer for CDMA/PCS/PDC and single-chip CMOS RF chip sets for W-CDMA, WLAN, and PHS. Since 2005, he has been with the Department of Electronics Engineering, Konkuk University, Seoul, Rep. of Korea, where he is currently an assistant professor. His research interests include implementation of the CMOS RF transceiver, analog integrated circuits, and the analog/digital mixed-mode VLSI system design.

wide-band fine-resolution dco with an active inductor and...

Documents