workshop april 4th, 2007 lithography a uc discovery...

04/04/2007 FLCC - LithographyFLCC

Feature-level Compensation & Control

WorkshopApril 4th, 2007 Lithography

A UC Discovery Project

04/04/2007 FLCC - Lithography

2

FLCC

Current Milestones (Year 3)• Establish industry acceptable Process-EDA test structures (LITH Y3.1) Wojtek

Poppe (Collaborating from SRC Grant) Lynn Wang Refine test-patterns designs to measure key model parameters while mitigating chip test

area, minimize mask-writing time, and maximize simplicity in quantitative interpretation.

• Create design-rule qualifiable test structures for PPC calibration (LITH Y3.2) Juliet Holwill

Create 2-D test patterns that are compatible with design rules and superior to device features in identifying and quantifying process parameters for pre-compensation treatments.

• Test electrical PSM-PI and explore zero-foot-print electronic versions (LITH Y3.3)Evaluate wafer performance of electrical probe PSM-PI for focus mapping. Combine

parameter specific interferometric-probe targets with electronic detection and RF communication for in situ stepper measurements. Juliet Holwill and (Jing Xue)

• Evaluate Pattern-Matching for predicting device variation hot-spots (LITH Y3.4)

Develop maximum lateral impact functions for locating gates with high levels of device variation and correlate results with wafer experiments and the Quantitative Yield Simulator being developed on SRC/DARPA support. Juliet Holwill

• Prototype Pattern-Matching for predicting interconnect delay variation (LITH Y3.5)Develop maximum lateral impact functions and net-list tracking software for locating,

quantifying and summing variations in interconnect delay due to residual process non-idealities. Eric Chin

100%

100%

80%

80%

100%

Exp

Exp


3

FLCC

Future Milestones (Year 4)• Build a web-based, interactive platform for collaborative analysis of variation. (LITH Y4.1)

Wojtek PoppeAssemble current in-depth understanding, catalog SEM and electrical measurements versus wafer

position, and facilitate on-line statistical queries of simulation and experimental data to promote collaborative prediction and analysis of sources of non-uniformity in Semiconductor Manufacturing.

• Make electrical measurements and perform statistical analysis of wafer data. (LITH 4.2) Lynn Wang

Make electrical and SEM measurements of fabricated leakage test circuit patterns from Cypress and correlate mean and variance with layout and programmed treatments and simulation predictions.

• EM effects in masks, inspection and novel meta-material monitors. (LITH 4.3) Marshal Miller

Characterize PSM mask opening cross-talk, develop analysis methodologies for surface roughness generated noise in inspection, and explore novel guided-wave, and plasmon, and meta-material devices for CD and LER monitors.

• Demonstrate accuracy and speed of Pattern-Matching for hot-spots and diagnostic design-rule compatible patterns (LITH Y4.4) Juliet Holwill and Lynn Wang

Compare estimates of linewidth shape and device leakage from Pattern Matching with full lithography simulation and the Quantitative Yield Simulator being developed on SRC/DARPA support for both custom and standard design styles. Use simulation and Pattern Matching to assess the trade-off in sensitivity as maximal lateral impact functions are morphed into production acceptable designs.

• Demonstrate accuracy and speed of Pattern-Matching for predicting interconnect delay variation (LITH Y4.5) Eric Chin

Compare Pattern Matching estimates of interconnect delay variation including full chip CMP modeling with brute force modeling.

Blue = Underway


4

FLCC

Collaborative Multi-Student Enhanced NMOS Test Chip

178 30-pad cells

Ready for many more contributors on next chipNew Optical Digital Profilometery Structures

WojtekPoppeSRC


5

FLCC

Widths from

180nm to 2um

isolated Preferred pitches Forbidden pitchesBest ILSPoor ILS Worst ILS

Gate CDGate Oxide Thickness

Channel Doping

Ioff sensitivity enhancement 2500% 750% 1125%

Compare enhanced and standard transistor

0.0 0.8 1.61E-14

1E-13

1E-12

1E-11

1E-10

1E-9

1E-8

1E-7

1E-6

1E-5

1E-4

Dra

in C

urre

nt (A

) log

sca

le

Gate Voltage (V)

<10 mV/dec @ 4 K<10 mV/dec @ 4 K

300 K

VT at 300 KVT at 4 K

Cryogenic testing

Segregating LWR from RDFRDF = Random Dopant Fluctuation


6

FLCC

Relational Database for Data Aggregation

transistor

Simulated Dimensions

has

Simulated C urrents

has

Measured Dimensions

Electrical Dimensions

has

Transistor_typeis_like

from

from

E-beamMachine

Probe Card

using

Optical Model

Transistor Model

(1,n)

(1,n)

(1,n)

(1,n)

(1,n)

(1,n)(1,n)

(1,n)

(1,1)

(1,1)

(1,1)

(1,1)

(1,1)

(1,1)

(1,1)

(1,1)

IsCharacterized

by

CD_SEM_data

from

(1,n)

(1,1)

(0,n)

(1,1)

Cell

Cell_type

contains

Is of

Test Strategy

(1,n)

(1,n)

has(1,1)

(1,1)

(1,1)

(1,1)die contains

(1,1)(1,n)

Isprocessed

at

Process conditions

(1,n)

(1,1)

by

Tester

(1,n)

(1,n)date

Created bydesigner(1,1)(1,n)

reports generates

guest

reads

has Non_idealities(1,1)

(1,1)

(1,n)

(1,n) (1,n)

(1,1)

ModifiedDimensions

has(1,1)

(1,n)

Characterized Wafer map

(1,1)

generates

(1,n)

is_at (1,1)location

(1,1)

Electrical Data

from

(1,n)

(1,1)

(1,n)

(1,1)

IsCharacterized

by

using(1,n)

o,t

user

o,t

Electrical Measurements

from(1,1)

(1,n)

See next pageFor non-transistor

types

contains

Hasextra

Other_values

(0,n)

(1,1)

has

Pin Config

(1,1)

(1,n)

Measurement Conditions (ex. Temp) Transistor AttributesSimulation results for different process conditions

Upload process non-idealities

Store Process Conditions

Transistor Location

Data Analysis Reports

Testing Strategy


7

FLCC

Photomask Edge Effect: Characterization

MarshalMillerFLCC

KojiKikuchi

Sony VIFDan

CeperleySRC

Imy CEI

Real CER

• Both Real and Imy Edge Effects• Adjusting Phase Etch Depth adds Purple

to cancel Yellow• Do we tell the Designers?• How can the Imy effects be measured?


8

FLCC

Solution: Measure 2nd Order Diffraction Efficiency

50% RealImy

Sqrt(I2)

0.01

Duty Cycle50% RealImy

Sqrt(I2)

0.01

50% RealImy

Sqrt(I2)

0.01

Duty Cycle

• Shift gives Real term (bias)

• Lack of a full minimum gives Imaginary term

• Will this work for ATT-PSM? (on new NMOS mask)


9

FLCC

Photomask Edge Effect: Characterization

50% RealImy

Sqrt(I2)

0.01

Duty Cycle50% RealImy

Sqrt(I2)

0.01

50% RealImy

Sqrt(I2)

0.01

Duty Cycle

5λ +5 deg 10λ

3λ

5λ


10

FLCC

EM Topography Effects Defect

• ATT-PSM and CPL Mask Opening Cross-Talk– Use TEMPEST time-evolution to visualize cross-talk as it

occurs among masks openings– Introduced reduced parameter edge and line source models

• Noise in Inspection– Utilize fields in smooth structures to estimate noise sources– Utilize partial coherence to reduce summation effort

Roughness(dipoles)

Build on Kostas Adam’s work


11

FLCC

EM Topography Effects (Cont.)

High Q guided wave resonator structure

Changes in duty cycle affect couplingVariations in CD affect QLER produces out of plane scatter

• Guided-wave Monitors for CD’s and LER– Identify high Q optical guiding structures as test vehicles– Evaluate sensitivity of angle and bandwidth (Q) of optical

coupling into guides to duty cycle, duty cycle spread, and LER


12

FLCC

Visualization of Focus Effects at LayoutJuliet Holwill

Cutline

Intensity Vs Distance at a range of coma levels for 0.193 NA = 0.5, defocus = -0.01

0

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

0 0.5 1 1.5 2 2.5 3 3.5

Distance (um)

Inte

nsity

-0.04 coma-0.02 Coma0 Coma0.02 Coma0.04 Coma

Line End Shortening

50/50 FLCC/SRC


13

FLCC

Pattern Matching Accuracy: Line End Shortening (LES)

• LES can be modeled using the product of the match factor times the aberration level.

• For Coma, LES is linear• For Defocus, LES is

parabolic

Line End Shortening

0

0.01

0.02

0.03

0.04

0.05

0.06

-0.05 -0.04 -0.03 -0.02 -0.01 0 0.01 0.02 0.03 0.04 0.05

Coma Amount (waves RMS)

Line

End

Sho

rteni

ng (u

m)

Line End Shortening

0.04

0.045

0.05

0.055

0.06

0.065

0.07

0.075

0.08

0.085

-0.05 -0.04 -0.03 -0.02 -0.01 0 0.01 0.02 0.03 0.04 0.05

Defocus Amount (waves RMS)

Line

edg

e sh

orte

ning

(um

)

dIdLIL ∆

=∆LE

S

Coma

DefocusLE

S

Aberration Level

Aberration LevelLES = Line End Shortening


14

FLCC

Phase-Shifting Mask Spillover TrendsMask Type

Slope Coma MF

∆L Splat (0.02 Coma)

∆L PM(0.02 Coma)

Focus MF

∆L Splat(0.04 Focus)

∆L PM(0.04 Focus)

Binary 6.95 0.075 4nm TBC 0.309 38nm TBC

Att. PSM

7.933 0.094 2nm TBC 0.318 27nm TBC

Alt. PSM

9.083 0.150 18nm TBC 0.342 30nm TBC

TBC = to be calibratedThe Pattern Match Factors and spillback light increases with the additional light through a phase-shifting mask but the impact on edge placement is partially mitigated by the increase in image slope.

Cutline


15

FLCC

Automatic Generation of Design Rule Compatible Monitors

• Automate the generation process

• Include input patterns for focus, illumination, high-NA, polarization

• Evaluate the change in sensitivity and selectivity vs. design rules

• Extend to evaluating and generating 2D targets suitable for OPC calibration

Focus examples


16

FLCC

Aberration Monitoring with Electrical Testing

=+

Contact Pad Thin line of conductive material

Open circuit created when aberration present

Defocus = 0.02 Defocus = 0.2Defocus = 0.0 Defocus = 0.02 Defocus = 0.2Defocus = 0.0


17

FLCC

Standard Cell Interactions: Approach

Lynn Wang

Boundary

MF = 0.3Adjacent cells increase Match

Factors and hence variation through

focus

50/50 FLCC/SRC

Cell i Cell j


18

FLCC

Standard Cell Interactions: Focus Test


19

FLCC

Standard Cell Interactions: DL vs. Match


20

FLCC

Interconnect Variation Assessment: ConceptMajor Physical Contributors to Variation:- Lithography (Focus, Overlay, Aberrations, …)- CMP (Density, …)- Etch (Sidewall Angle, …)

Key idea: Predict interconnect delay variations by tracing Pattern Matches through circuits and adjusting extracted RCs.

Delay Variation = f(local layout, layout in layers above and below, die location, wafer position)

Eric Chin

SPIE 6521-16, 4:50 PM

50/50 FLCC/SRC


21

FLCC

Interconnect Variation Assessment: System

Pattern Matcher

Predict Geometrical Variations

Estimate Changes in R, CNetlist Backannotation

Timing Analysis

Parasitic Extraction

Fast-CAD Techniques:1) Focus solely on

critical paths to improve runtime

2) Include layer specific lithography, Etch, CMP process variations.

See Poster for initial results

Nominal

CMP Erosion

Linewidth (nm) Space (nm) Height (nm) Ct (fF/mm) R (Ohm/mm) Delay (ps) Error110 110 175 180.724 1558.44 97.17 0.00%

98 122 175 166.61 1749.27 100.55 3.48%122 98 175 197.65 1405.15 95.82 -1.39%110 110 158 171.39 1726.12 102.06 5.04%

98 122 158 158.185 1937.48 105.74 8.82%122 98 158 187.181 1556.34 100.50 3.43%

Delay of a 1mm M1 interconnect (array) Pitch=220nm

Litho LW Effect


22

FLCC

Future Milestones (Year 4)• Build a web-based, interactive platform for collaborative analysis of variation. (LITH Y4.1) Wojtek PoppeAssemble current in-depth understanding, catalog SEM and electrical measurements versus wafer

position, and facilitate on-line statistical queries of simulation and experimental data to promote collaborative prediction and analysis of sources of non-uniformity in Semiconductor Manufacturing.

• Make electrical measurements and perform statistical analysis of wafer data. (LITH 4.2) Juliet Holwill, Lynn Wang

Make electrical and SEM measurements of fabricated leakage test circuit patterns from Cypress and correlate mean and variance with layout and programmed treatments and simulation predictions.

• EM effects in masks, inspection and novel meta-material monitors. (LITH 4.3) Marshal MillerCharacterize PSM mask opening cross-talk, develop analysis methodologies for surface roughness

generated noise in inspection, and explore novel guided-wave, and plasmon, and meta-material devices for CD and LER monitors.

• Demonstrate accuracy and speed of Pattern-Matching for hot-spots and diagnostic design-rule compatible patterns (LITH Y4.4) Juliet Holwill and Lynn Wang

Compare estimates of linewidth shape and device leakage from Pattern Matching with full lithography simulation and the Quantitative Yield Simulator being developed on SRC/DARPA support for both custom and standard design styles. Use simulation and Pattern Matching to assess the trade-off in sensitivity as maximal lateral impact functions are morphed into production acceptable designs.

• Demonstrate accuracy and speed of Pattern-Matching for predicting interconnect delay variation (LITH Y4.5) Eric Chin

Compare Pattern Matching estimates of interconnect delay variation including full chip CMP modeling with brute force modeling.

Black = Finished; Green = Continuing; Red = To Start

workshop april 4th, 2007 lithography a uc discovery...

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