2004 ie theory paper

8/2/2019 2004 IE Theory Paper

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WSS 2004 (Industrial Electronics) FinalsTheory Paper

Question 1

Assume that the diodes are ideal and have a forward voltage drop of 0.7V,determine the current through diode D1 for the circuits below.

1k

D1

1k

ZD13.3V

5mA

10V

1.5K2.2K

1.0K

+15V

-15V0V

D1


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Question 1 Solution


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Question 2

Design a 2-bit 2s complement number converter using the 2-4 decoder and 4-2encoder whose function tables are given as follows.

Functional Table of 2-4 Decoder Functional Table of 4-2 Encoder

InputA B

OutputY0 Y1 Y2 Y3

10000

x x0 00 11 01 1

1 1 1 10 1 1 11 0 1 11 1 0 11 1 1 0

Question 2 Solution

InputA0 A1 A2 A3

OutputY0 Y1

0 1 1 11 0 1 11 1 0 11 1 1 0

0 00 11 01 1


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Question 3

Design a 2nd Order Butterworth voltage controlled voltage source (VCVS)low-pass active filter that has a pass-band voltage gain of one and a cut-offfrequency of 1 kHz. Sketch the gain amplitude versus frequency response of

this filter. Let C = 0.47 F. Hence, determine the roll-off rate of the filter.

C 1

CR 1 R 2

R 3

R 4

Butterworth VCVS low pass filter

Table 1

Circuit Element ValuesGain 1 2 4 6 8 10 R1 1.422 1.126 0.824 0.617 0.521 0.462R2 5.399 2.250 1.537 2.051 2.429 2.742

R3 Open 6.752 3.148 3.203 3.372 3.560R4 0 6.752 9.444 16.012 23.602 32.038C1 0.33C C 2C 2C 2C 2CNote: Resistances in k for scaling ratio (100 / f c C'), K=1.

Question 3 Solution


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Question 4

Put the following expression in sum-of-product (SOP) form. Verify witha truth table that the SOP expression you end with, is the same as the givenexpression.

daa)]c(a[bd +++

Question 4 Solution


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Question 5

The figure below shows a non-inverting clamper circuit.

a) By means of Superposition Theorem, prove that the output voltage is:

V o = V ref +

+

1

F1 R

RV in

b) Sketch the output waveform (for 1 cycle) if Vin is a 4 Vp-p sinewave of 1 kHzwith zero dc offset voltage, and Vref is set to 1 Vdc.

+

+V CC

V EE

op-amp

R 4 10 k

R F=10k R 1=10k

V o

C 1

R L

V in +V CC

V EE

R 2 V ref 1V

C i

R 3


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Question 5 Solution


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Question 6

6 a) Based on the memory chip and the 3-to-8 Decoder ICs given below, design amemory module with a capacity of 2 K x 8. Draw the complete circuit diagramand label all bus lines clearly.

6 b) Explain what will happen when the Chip-Select pin of one of the many memorychips is accidentally shorted to ground.

Question 6 Solution

Y0S2S1S0

EN0EN1 Y7

3-To-8 Decoder Memory Chip

A0 I/O 0 :::A8 I /O 7

R/W

CS

::

::


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Question 7

Assuming ideal op amps, determine the output voltage V o for each circuit in below.

a)

Figure 1A

b)

Figure 1B


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Question 7 Solution


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Question 8

Figure 2 shows the intersection of two roads. Vehicle-detection sensors areplaced along lanes A, B, C and D. The sensor outputs are LOW (0) when novehicle is present, and HIGH (1) when a vehicle is present. The intersection

traffic light is controlled as follow:i) The E-W traffic light will be green whenever both lanes C and D are

occupied.ii) The E-W light will be green whenever either C or D is occupied but

lanes A and B are not both occupied.iii) The N-S light will be green whenever both lanes A and B are occupied

but C and D are not both occupied.iv) The N-S light will also be green when either lane A or B is occupied

while C and D are both vacant.v) The E-W light will be green when no vehicles are present.

Using the sensor outputs A, B, C and D as inputs, design a logic circuit tocontrol the traffic light. There should be 2 outputs, N-S and E-W, whichbecome 1 when the corresponding light is to be green.

Figure 2


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Question 8 Solution


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Question 9

A 10 bits digital ramp ADC is operating at the clock rate of 1MHz, and the full scale

output is equal to 10.23 V.

a. Determine the step size and the resolution of this ADC converter.

b. Determine the digital equivalent value of an analogue input of 3.728 V.

c. Determine the conversion time required for converting the analogue 3.728 V to it

digital equivalent value.

d. Determine the average conversion time of this ADC.

Question 9 Solution


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Question 10

A 4 input CMOS domino AND logic gate with inputs A, B, C and D is designed asshown.

The Inputs are normally held low during the period of Pre-charge. During the evaluate

cycle, input A is at logic High and input B, C and D are at logic Low.

The Output node drives an inverter with a switching threshold (V Tn) of 2.8V. C P is the

capacitance at the source-drain node of the series pull-down network and C L is the

capacitance at the intermediate Output node of the logic gate.

Calculate the maximum ratio of C P / C L required to ensure that charge sharing will not

corrupt the final output value.

Vout

Vdd (+5V)

CL

Cp

Vx

A

B

C

D

Output

Time (t)

5V Pre-charg e

EvaluateEvaluate


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Question 10 Solution


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2004 ie theory paper

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