8A3xxxx 72QFN EVK User Manual

© 2019 Integrated Device Technology, Inc. 1 February 14, 2019

Description

The 8Axxxx 72QFN EVK is designed to help customers evaluate IDT ClockMatrix devices. This document discusses the following about the EVK:

Introduces the board and its power supply and jumper settings

Describes the input and output connectors for normaloperation

Explains how to bring up the board using the TimingCommander software GUI

Discusses how to configure and program the board togenerate standard-compliant frequencies

Kit Contents

8A34xxx 72QFN Evaluation Board

USB Type A cable

Requirements

IDT Timing Commander Software Installed (available atwww.idt.com/timingcommander)

ClockMatrix GUI (available at www.idt.com/clockmatrix)

USB 2.0 or USB 3.0 interface

Windows XP SP3 or later

Processor: Minimum 1GHz

Memory: Minimum 512MB; recommended 1GB

Available disk space: Minimum 600MB (1.5GB 64-bit);recommended 1GB (2GB 64-bit)

Network access during installation if the .NET framework isnot currently installed on the system

8A3xxxx 72QFN EVK Board

8A3xxxx 72QFN EVK User Manual

© 2019 Integrated Device Technology, Inc. 2 February 14, 2019

Important Notes

Disclaimer

Integrated Device Technology, Inc. and its affiliated companies (herein referred to as “IDT”) shall not be liable for any damages arising out of defects resulting from

(i) delivered hardware or software

(ii) non-observance of instructions contained in this manual and in any other documentation provided to user, or

(iii) misuse, abuse, use under abnormal conditions, or alteration by anyone other than IDT.

TO THE EXTENT PERMITTED BY LAW, IDT HEREBY EXPRESSLY DISCLAIMS AND USER EXPRESSLY WAIVES ANY AND ALL WARRANTIES, WHETHER EXPRESS, IMPLIED, OR STATUTORY, INCLUDING, WITHOUT LIMITATION, IMPLIED WARRANTIES OF MERCHANTABILITY AND OF FITNESS FOR A PARTICULAR PURPOSE, STATUTORY WARRANTY OF NON-INFRINGEMENT, AND ANY OTHER WARRANTY THAT MAY ARISE BY REASON OF USAGE OF TRADE, CUSTOM, OR COURSE OF DEALING.

Important Equipment Warning: Ensure the correct connection of all cables. Supplying the board using the wrong polarity could result in damage to the board and/or the equipment. Check that all jumpers have been removed from the board before applying power.

Contents

1. Usage Guide .................................................................................................................................................................................................4

1.1 Board Overview ...................................................................................................................................................................................4

1.2 Board Power Supply ............................................................................................................................................................................5

1.3 Voltage Selection Jumpers ..................................................................................................................................................................5

1.4 GPIO Switches, LEDs, and Test Points ..............................................................................................................................................6

1.5 USB Jack .............................................................................................................................................................................................7

1.6 I2C between FTDI, CM Device, and Onboard EEPROM .....................................................................................................................7

2. Working with Timing Commander™ for Programing/Configuration ..............................................................................................................8

2.1 Default Operation ................................................................................................................................................................................8

2.2 Using Timing Commander to Control the Board ..................................................................................................................................9

2.3 Output Terminations and Rework to Take 1PPS Input ......................................................................................................................15

3. How to Upload Firmware to the RAM .........................................................................................................................................................16

4. Schematics .................................................................................................................................................................................................18

5. Ordering Information ...................................................................................................................................................................................18

6. Revision History ..........................................................................................................................................................................................18

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© 2019 Integrated Device Technology, Inc. 3 February 14, 2019

List of Figures

Figure 1. Overview of 72QFN ClockMatrix Evaluation Board .............................................................................................................................4

Figure 2. Example of Voltage Jumpers ...............................................................................................................................................................5

Figure 3. GPIO Setting and Status Display Area ................................................................................................................................................7

Figure 4. Board Setting for Default Operation ....................................................................................................................................................8

Figure 5. Starting Up Timing Commander GUI ...................................................................................................................................................9

Figure 6. Selecting 8A34001 using Personality File v4.6 ..................................................................................................................................10

Figure 7. Timing Commander GUI with a Settings File Opened .......................................................................................................................11

Figure 8. Setting I2C for Connecting the Board with GUI ..................................................................................................................................12

Figure 9. A Green Band appears when a Valid Connection is Made ................................................................................................................12

Figure 10. Firmware Version Mismatch Warning Message ................................................................................................................................13

Figure 11. Reading Firmware Version ................................................................................................................................................................13

Figure 12. Read Firmware Version of ClockMatrix Chip .....................................................................................................................................14

Figure 13. AC Coupling and Terminations for Input Clock ..................................................................................................................................15

Figure 14. Configuring CLK0 as CMOS to Receive a 1PPS Input ......................................................................................................................15

List of Tables

Table 1. GPIO Settings ......................................................................................................................................................................................6

Table 2. EEPROM I2C Connections ..................................................................................................................................................................7

8A3xxxx 72QFN EVK User Manual

© 2019 Integrated Device Technology, Inc. 4 February 14, 2019

1. Usage Guide

1.1 Board Overview

The following diagram identifies various components of the board: input and output SMA connectors, power supply jacks, and some jumper settings necessary for the board operations.

Figure 1. Overview of 72QFN ClockMatrix Evaluation Board

Detailed descriptions of the board are as follows:

Input SMA Connectors – There are five differential inputs labeled CLK0/nCLK0–CLK4/nCLK4. Each input clock can be configured differentially (LVDS, PECL 2.5V, and PECL 3.3V) or in single-ended format (CMOS).

Output SMA Connectors – There are 12 outputs labeled as Q0/nQ0–Q11/nQ11. Each output clock can be configured differentially (LVDS, LVPECL, or user-defined amplitude) or in single-ended format (LVCMOS – in-phase or out-of-phase).

GPIO switch, LEDs, and test points – There are seven GPIOs available. Each GPIO can be set a “low” or “high” level (if input) or displayed with an LED (if output). Some GPIOs are used to set the chip in a certain working condition on power-up. For more information, see GPIO Switches, LEDs, and Test Points.

USB connector – A USB mini connector connects the evaluation board to a PC for GUI communications. No power is drawn from the USB connector other than to power the FTDI USB chip.

8A3xxxx 72QFN EVK User Manual

© 2019 Integrated Device Technology, Inc. 5 February 14, 2019

VDDQx voltage selection jumpers – Each output voltage can be individually supplied with 1.8V, 2.5V, or 3.3V. These jumpers are used toselect the voltage for the output voltages.

Reset button – A small button is used to reset the board.

OSCI Input connector – An SMA connector, J45, can optionally supply a clock signal to overdrive the crystal.

Optional OCXO/TCXO Reference – An OCXO/TCXO footprint, is output at J82. It can be connected to J46 (below) as the reference forthe System DPLL.

SysDPLL Input – An SMA connector, J46, is provided to supply a local OCXO/TCXO reference as an optional reference for the SystemDPLL.

Crystal – A crystal of various frequencies must be present for board operations. A 3225 footprint is provided for SMT crystals. For easyplug-in of a canned crystal, two through holes are also available.

EEPROM – An SO-8 socket is provided to hold an EEPROM device of compatible package. An EEROM is used to store firmware andcustomer configuration data, if needed.

1.2 Board Power Supply

The board uses a single +5V supply for its power supplies. When running the board, please set the bench power supply at 5V/2A. The red jack (J1) is positive; the black jack (J2) is the ground.

Multiple LDOs are used to generate 3.3V, 2.5V, and 1.8V from the +5V supply.

1.3 Voltage Selection Jumpers

There are eight headers/jumpers to select different voltages for different functional blocks of the chip. Each header has pin 1 and 3 labeled in silkscreen – jumping pin 1 and pin 2 will select 3.3V; jumping pin 2 and pin 3 will select 2.5V; no jumper will have 1.8V.

Please see the following example for JP4 and JP9 – JP4 will select 2.5V; JP9 will select 3.3V.

Figure 2. Example of Voltage Jumpers

8A3xxxx 72QFN EVK User Manual

© 2019 Integrated Device Technology, Inc. 6 February 14, 2019

The following list shows which head/jumper is used to select what voltage:

JP1 – VDDD

JP2 – VDDA

JP3 – VCC_GPIO_DC

JP4 – VDDO_Q8_3_5

JP5 – VDDO_Q2_4_11

JP6 – VDDO_1_10_7

JP7 – VDD_CLK0

JP9 – VDDO_Q0_9_6

Important Equipment Warning: VDD_FOD voltage is selected by resistors R908 and R909. In order to prevent damage to the device, both R908 and R909 should not be stuffed, in which case VDD_FOD = 1.8V.

1.4 GPIO Switches, LEDs, and Test Points

An 8-bit dip switch sets the logic levels for seven GPIOs (GPIO0-5 and GPIO9). The following table shows the GPIO levels for each setting and the corresponding LED state.

Table 1. GPIO Settings

Dip Switch Position GPIO Logic Level LED

Left Low On

Center High if GPIO is configured as Input

High or Low according to the GPIO output setting

High if GPIO is configured as Input

High or Low according to the GPIO output setting

Right High Off

Please see the picture and labels in Figure 3.

When the GPIOs are configured as outputs (such as User-Controlled or LOL indicator), the dip switch for the corresponding GPIO should be placed in the center position. The LED will indicate the state of the GPIO.

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© 2019 Integrated Device Technology, Inc. 7 February 14, 2019

Figure 3. GPIO Setting and Status Display Area

1.5 USB Jack

The board has a USB mini-connector. The other end of the USB cable is a USB Type A connector going to a PC.

1.6 I2C between FTDI, CM Device, and Onboard EEPROM

One of the major differences between the 72QFN and 144BGA144 chips is that there is only one serial bus on the 72QFN chip. The I2C bus between the FTDI chip and CM chip is the same bus between the CM chip and the onboard EEPROM. The onboard EEPROM is used to store device firmware and/or customer’s configuration data. JP12 and JP13 must be jumped between pin 1 and 2 to enable the I2C connections.

Table 2. EEPROM I2C Connections

JP12/JP13 JP12/JP13

Jumper Position Pin 1 and 2 Pin 2 and 3

EEPROM I2C Path FDTI and CM Chip;

CM Chip and EEPROM N/A

8A3xxxx 72QFN EVK User Manual

© 2019 Integrated Device Technology, Inc. 8 February 14, 2019

2. Working with Timing Commander™ for Programing/Configuration

The following sections are best cross-referenced with the ClockMatrix GUI Step-by-Step User Guide which is available on www.idt.com.

2.1 Default Operation

The board can operate off an EEPROM that has stored all information including firmware and a default configuration data. A default operation provides a sanity check on the board before running the board through the IDT Timing Commander. Please set the board in the following default conditions (see Figure 4 for jumper and switch positions).

Set all the GPIOs to the center position. This will ensure that GPIO9 is high and that the serial port is configured for I2C 1-byte addressing.

VDDA = 3.3V, VDD_ FOD = 1.8V, and VDDO_Qx = 3.3V

Crystal frequency = 50MHz

CLK0 = 25MHz

FTDI, CM device, and EEPROM share the same I2C bus by jumping Pin 1 and 2 of JP12 and JP13

With the above default conditions ready, connect the board to the PC using a USB type A to USB mini cable, and power up the board using a single +5V supply. On power-up, the ClockMatrix chip will read its firmware and configuration data from EEPROM and update all registers. When this process is completed, the following frequencies are available:

Q0 = 122.88MHz

Q1 = 122.88MHz

Figure 4. Board Setting for Default Operation

Important Equipment Warning: In order to set GPIO9 to “High”, the switch for GPIO9 must be set either to the “+” (high) position or the center position.

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8A3xxxx 72QFN EVK User Manual

© 2019 Integrated Device Technology, Inc. 9 February 14, 2019

2.2 Using Timing Commander to Control the Board

Once the default operation is successful, complete the following steps to configure and program the ClockMatrix device per your specific application requirements using Timing Commander GUI tools:

1. Power up the board and set the main serial port in I2C mode by GPIO9 = “high”. Connect the board to the PC.

2. Start the Timing Commander software. You will see options of “New Setting File” and “Open Setting file”. For a new configuration, select “New Setting File”.

Figure 5. Starting Up Timing Commander GUI

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© 2019 Integrated Device Technology, Inc. 10 February 14, 2019

3. After selecting “New Settings File”, a device selection window will pop up. In the window, choose the intended device in the list (in this example, 8A34001 is selected). Click the button at the lower right corner of the window (red circle) to browse and select the correct personality file (in this example, personality v4.6 is selected). Click OK.

Figure 6. Selecting 8A34001 using Personality File v4.6

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© 2019 Integrated Device Technology, Inc. 11 February 14, 2019

4. The GUI window with the 8A34001 block diagram will open for configurations; or if “Open Settings File” is selected in Step 3, you will be prompted to browse and select an existing .tcs file and the personality file. When the configuration file is open, all configured values will be displayed (see Figure 7).

Figure 7. Timing Commander GUI with a Settings File Opened

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© 2019 Integrated Device Technology, Inc. 12 February 14, 2019

5. In order to connect the board with Timing Commander (PC), click the button (red circle) at the up-right corner of the GUI to set up the communication protocols (see Figure 7).

After I2C and one-byte addressing are selected, click OK to close the window.

Figure 8. Setting I2C for Connecting the Board with GUI

6. Click on the chip symbol at the upper-right corner to initiate the connection. The connection is valid when a green band appears at the upper-right corner of the window, as shown below.

Figure 9. A Green Band appears when a Valid Connection is Made

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© 2019 Integrated Device Technology, Inc. 13 February 14, 2019

7. If ClockMatrix chip’s firmware, or firmware loaded from EEPROM, has a different version from that in the Personality file, a firmware version mismatch warning message will appear. Click “Close” button to close the message window and a connection is made.

Figure 10. Firmware Version Mismatch Warning Message

8. Once the connection is made, the firmware version can be read within the GUI. Click the “Firmware Utility” button to bring up the Firmware Utility window, as shown below.

Figure 11. Reading Firmware Version

8A3xxxx 72QFN EVK User Manual

© 2019 Integrated Device Technology, Inc. 14 February 14, 2019

9. Within the Firmware Utility window, click the “Get Firmware Version” button to read the firmware version.

Figure 12. Read Firmware Version of ClockMatrix Chip

10. In the case where the firmware version mismatches each other, a firmware upgrade is necessary to update the chip’s firmware. To do so, complete the steps in How to Upload Firmware (see Section 3) to update the chip’s firmware.

8A3xxxx 72QFN EVK User Manual

© 2019 Integrated Device Technology, Inc. 15 February 14, 2019

2.3 Output Terminations and Rework to Take 1PPS Input

All outputs are terminated with a 100Ω resistor across the output pair. This is the recommended termination regardless of the Voffset and Vswing settings. Since the outputs are DC-coupled, they will support a 1PPS output without any need for rework.

Important Equipment Warning: When connecting the outputs to measurement equipment, use a DC-block to ensure that the output operates at its intended Voffset. Otherwise, the equipment may load the output down and cause degraded performance.

The following rework must be implemented in order to support a 1PPS input clock. All input clocks for this board are ac-coupled and terminated as in the following figure.

Figure 13. AC Coupling and Terminations for Input Clock

For a 1PPS input, a single-ended input with DC-coupling is recommended. As such, the populated AC-coupling capacitor must be removed and the input must be configured as LVCMOS, not differential.

1. In Figure 13, to make CLK0 supportive of 1PPS input, first configure CLK0 as LVCMOS in Timing Commander (see Figure 14).

Figure 14. Configuring CLK0 as CMOS to Receive a 1PPS Input

2. Once in LVCMOS mode, CLK0_P and CLK0_N will be two separate LVCMOS inputs instead of a differential pair. To make CLK0_P receive a 1PPS input, replace C881 with a 0Ω resistor; and at the same time, remove R765 and R770.

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© 2019 Integrated Device Technology, Inc. 16 February 14, 2019

3. How to Upload Firmware to the RAM

1. Connect to the EVK board.

2. Power up the board with no EEPROM present. This ensures the firmware is 4.0.2.7017, as displayed in the figure.

3. The GUI will indicate that the firmware on the chip does not match the GUI firmware. Press “Close”.

4. Open the “Firmware Utility” window by clicking on the button as follows.

5. Update the Firmware first. Press “Update RAM to Current FW Only”.

6. In the next window, press “Yes” and wait around 3-4 minutes.

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© 2019 Integrated Device Technology, Inc. 17 February 14, 2019

7. Once the firmware is updated, the following window will indicate a successful update. Click “Close”.

8. Press “Get Firmware Version” to verify that the RAM was updated correctly, then click “Close”.

8A3xxxx 72QFN EVK User Manual

© 2019 Integrated Device Technology, Inc. 18 February 14, 2019

4. Schematics

Please see the schematics located at the end of this document.

5. Ordering Information

Orderable Part Number Description

8A34044-EVK 8A3xxxx 72QFN Evaluation Kit

6. Revision History

Revision Date Description of Change

February 14, 2019 Initial release.

Corporate Headquarters

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Sales

1-800-345-7015 or 408-284-8200 Fax: 408-284-2775 www.IDT.com/go/sales

Tech Support

www.IDT.com/go/support

DISCLAIMER Integrated Device Technology, Inc. (IDT) and its affiliated companies (herein referred to as “IDT”) reserve the ri ght to modify the products and/or specifications described herein at any time, without notice, at IDT's sole discretion. Performance specifications and operating parameters of the described products are determine d in an independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limite d to, the suitability of IDT's products for any particular purpose, an implied warranty of merchantability, or non -infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT's products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT pro duct can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. Integrated Device Technology, IDT and the IDT logo are trademarks or registered trademarks of IDT and its subsidiaries in the United States and other countries. Other trademarks used herein are the property of IDT or their respective third party owners. For datasheet type definitions and a glossary of common terms, visit www.idt.com/go/glossary. All contents of this document are copyright of Integrated Device Technology, Inc. All rights reserved.

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CLK_Q6_P 8CLK_Q6_N 8

CLK_Q7_P 8CLK_Q7_N 8

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CLK_Q10_P 8CLK_Q10_N 8

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VDDA_SEL

C845

0.1uF

03-09-15 RvR

ADM7171ACPZ-R7

U69

IC REG LDO ADJ 1A 8LFCSP

SS4

EN5

VIN7

VIN8 VOUT

1

VOUT2

SENSE3

GND6

GNDPAD9

R599

17.4

k

C842

10uF

C837

10uF

R909

NP

DN

S

19-02-14 RvR

J1

111-0702-001POST BINDING INSULATED RED

11

C864

10uF

C865

0.01uF

C957

0.0

1uF

C846

10uF

R486

3k D16

LNJ347W83RA

JP1

VDDA_SEL

C799

0.1uF

R908

NP

DN

S

19-02-14 RvR

J2

111-0703-001POST BINDING INSUL GROUNDED BLCK

11

R30

52.3

k

RvR02-09-15

U89

LP38798SD-ADJ/NOPBIC REG LDO ADJ 0.8A 12WSON

IN1

IN2

IN_CP3

CP4

EN5

GND6

GND7

FB8

SET9

OUT_FB10

OUT11

OUT12

DAP13

RT1 1206L350SLTHYR

R703

10k

C15

1.0

uF

C8

0.01uF

C14

0.01uF

C800

10uF

R903 26.1k

R597

1k

R76 44.2kR17 44.2k

C16

0.0

1uF

RvR02-09-15

U9

LP38798SD-ADJ/NOPBIC REG LDO ADJ 0.8A 12WSON

IN1

IN2

IN_CP3

CP4

EN5

GND6

GND7

FB8

SET9

OUT_FB10

OUT11

OUT12

DAP13

R70626.1k

C836

1000pF

R12

10k

RvR02-09-15

U17

LP38798SD-ADJ/NOPBIC REG LDO ADJ 0.8A 12WSON

IN1

IN2

IN_CP3

CP4

EN5

GND6

GND7

FB8

SET9

OUT_FB10

OUT11

OUT12

DAP13

C803

0.1uF

C10

0.0

1uF

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

SILKSCRN:VDDO_Q8,Q3,Q5

SILKSCRN:VDDO_Q0,Q9,Q6

SILKSCRN:VDDO_Q1,Q10,Q7

SILKSCRN:VDDO_Q2,Q4,Q11

SILKSCRN:VDD_CLK0

3V3

2V5

SILKSCRN:3.3V Top2.5V Bot1.8V Float

3V3

2V5

SILKSCRN:3.3V Top2.5V Bot1.8V Float

3V3

2V5

SILKSCRN:3.3V Top2.5V Bot1.8V Float

3V3

2V5

SILKSCRN:3.3V Top2.5V Bot1.8V Float

3V3

2V5

SILKSCRN:3.3V Top2.5V Bot1.8V Float

5V0

VDDO_Q1_10_7

5V0

VDDO_Q2_4_11

VDDO_Q8_3_5

5V0

VDDO_Q0_9_6

5V0

5V0

VDD_CLK0

OF

PROJECT NAME

DRAWN

CHECK

DESIGN TITLE

DRAWING NUMBER REVISION

RELEASE DATE SHEET

SUBTITLE

1.2SK-10280-01

IDT8A34001

93

Fidus Systems375 Terry Fox Drive, Ottawa, ON K2K 0J8

Indira3

DB

DB

DB

27 October 2016

Power Supplies 2

OF

PROJECT NAME

DRAWN

CHECK

DESIGN TITLE

DRAWING NUMBER REVISION

RELEASE DATE SHEET

SUBTITLE

1.2SK-10280-01

IDT8A34001

93

Fidus Systems375 Terry Fox Drive, Ottawa, ON K2K 0J8

Indira3

DB

DB

DB

27 October 2016

Power Supplies 2

OF

PROJECT NAME

DRAWN

CHECK

DESIGN TITLE

DRAWING NUMBER REVISION

RELEASE DATE SHEET

SUBTITLE

1.2SK-10280-01

IDT8A34001

93

Fidus Systems375 Terry Fox Drive, Ottawa, ON K2K 0J8

Indira3

DB

DB

DB

27 October 2016

Power Supplies 2

R64 26.1k

C812

0.1uF

R404 44.2k

C20

0.01uF

R55

10k

R400

10k

R89 21kR50 26.1k

C401

0.0

1uF

RvR02-09-15

U19

LP38798SD-ADJ/NOPBIC REG LDO ADJ 0.8A 12WSON

IN1

IN2

IN_CP3

CP4

EN5

GND6

GND7

FB8

SET9

OUT_FB10

OUT11

OUT12

DAP13

C810

0.1uF

R401 26.1k

C813

10uF

R501 44.2k

TP1

C26

0.01uF

C816

0.1uFR403 21k

R47

10k

R92 44.2k

C811

10uF JP4

VDDA_SEL

R61

10k

R58

52.3

k

C817

10uF

R503 21k

C403

0.1uF

C23

0.01uF

R40

10k

R35

52.3

k

C27

1.0

uF

JP9

VDDA_SEL

C21

1.0

uF

R93 21k

R402

52.3

k

R84 44.2k

C404

10uF

C29

0.01uF

C28

0.0

1uF

C30

1.0

uF

R65

52.3

k

C22

0.0

1uF

C24

1.0

uF

JP7

VDDA_SEL

R51

52.3

k

RvR02-09-15

U21

LP38798SD-ADJ/NOPBIC REG LDO ADJ 0.8A 12WSON

IN1

IN2

IN_CP3

CP4

EN5

GND6

GND7

FB8

SET9

OUT_FB10

OUT11

OUT12

DAP13

C814

0.1uFR85 21k

RvR02-09-15

U400

LP38798SD-ADJ/NOPBIC REG LDO ADJ 0.8A 12WSON

IN1

IN2

IN_CP3

CP4

EN5

GND6

GND7

FB8

SET9

OUT_FB10

OUT11

OUT12

DAP13

C400

1.0

uF

C31

0.0

1uF

R88 44.2k

C25

0.0

1uF

C402

0.01uF

JP5

VDDA_SEL

C815

10uF

R57 26.1k

RvR02-09-15

U22

LP38798SD-ADJ/NOPBIC REG LDO ADJ 0.8A 12WSON

IN1

IN2

IN_CP3

CP4

EN5

GND6

GND7

FB8

SET9

OUT_FB10

OUT11

OUT12

DAP13

R43 26.1k

RvR02-09-15

U20

LP38798SD-ADJ/NOPBIC REG LDO ADJ 0.8A 12WSON

IN1

IN2

IN_CP3

CP4

EN5

GND6

GND7

FB8

SET9

OUT_FB10

OUT11

OUT12

DAP13

JP6

VDDA_SEL

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

USB 3V3

SILKSCRN:USB PWR

Notes:

1. By connecting I2C to the header's pin 1 and 3, this isto give I2C access to external I2C master;

2. By installing R926 and R927, FTDI can also access AuxI2C port (also removing R87 and R88). This feature is notexpected to be used.

3. Normal use: FTDI controls I2C port; Header is connectedto Aux port in SPI configuration.

3V3_FTDI

1V8_FTDI

5V0_USB

VCC_GPIO_DC

VCC_GPIO_DC

3V3

3V3

3V3

3V3

3V3

CLK_FTDI_PLL_SCL_OD 6FTDI_PLL_SDA_OD 6

SPI_SCLK 6SPI_SDIO 6SPI_SDI 6SPI_CSN 6

OF

PROJECT NAME

DRAWN

CHECK

DESIGN TITLE

DRAWING NUMBER REVISION

RELEASE DATE SHEET

SUBTITLE

1.2SK-10280-01

IDT8A34001

94

Fidus Systems375 Terry Fox Drive, Ottawa, ON K2K 0J8

Indira3

DB

DB

DB

27 October 2016

FTDI USB Interface

OF

PROJECT NAME

DRAWN

CHECK

DESIGN TITLE

DRAWING NUMBER REVISION

RELEASE DATE SHEET

SUBTITLE

1.2SK-10280-01

IDT8A34001

94

Fidus Systems375 Terry Fox Drive, Ottawa, ON K2K 0J8

Indira3

DB

DB

DB

27 October 2016

FTDI USB Interface

OF

PROJECT NAME

DRAWN

CHECK

DESIGN TITLE

DRAWING NUMBER REVISION

RELEASE DATE SHEET

SUBTITLE

1.2SK-10280-01

IDT8A34001

94

Fidus Systems375 Terry Fox Drive, Ottawa, ON K2K 0J8

Indira3

DB

DB

DB

27 October 2016

FTDI USB Interface

L84

220

08-10-14 EM

TXB0104RGYR

U404

IC VOLT-LEVEL TRANSLATOR 14-QFN

DNS

VCCA1

A12

A23

A34

A45

NC16

GND7

OE8

NC29

B410B311B212B113

VCCB14

GND_PAD15

C48

0.1

uF

GNDGND

RK24-07-13

Y1

ABM8G-12.000MHZ-18-D2Y-TCRYSTAL 12.0000MHZ 20PPM 4SMD

1 3

24

C45

0.1

uF

C413

0.1

uF

EM 06-02-13

J17

548190589CONN RCPT USB MINI-B 5POS RA SMT

VBUS1

DATA_N2DATA_P3

ID4

GND5

GND_SHLD6

GND_SHLD7

GND_SHLD8

GND_SHLD9

C687

10uF

RK16-08-13

FT2232HQ-REEL

U1

IC USB HS DUAL UART/FIFO 64-QFN

GND1

OSCI2

OSCO3

VPHY4

GND5

REF6

DATA_N7 DATA_P8

VPLL9

AGND10

GND11

VCORE12

TEST13

RESET_N14

GND15

ADBUS016

ADBUS117

ADBUS218

ADBUS319

VCCIO20

ADBUS421

ADBUS522

ADBUS623

ADBUS724

GND25

ACBUS026

ACBUS127

ACBUS228

ACBUS329

ACBUS430

VCCIO31

ACBUS532

ACBUS633

ACBUS734

GND35

SUSPEND_N36

VCORE37

BDBUS038

BDBUS139

BDBUS240

BDBUS341

VCCIO42

BDBUS443

BDBUS544

BDBUS645

BDBUS746

GND47

BCBUS048

VREGOUT49

VREGIN50

GND51

BCBUS152

BCBUS253

BCBUS354

BCBUS455

VCCIO56

BCBUS557

BCBUS658

BCBUS7/PWRSAV_N59

PWREN_N60

EEDATA61 EECLK62 EECS63

VCORE64

GND_PAD65

C42

0.1

uF

DB 24-07-14

TPD4S012DRYR

U55

IC 4CH ESD SOLUTION W/CLAMP 6SON

USBD_P1

USBD_N2

VBUS6

ID3

GND4

NC5

R383

10k

R424 1k

18-03-13 RK

N2510-6V0C-RB-WD

J4

CONN HEADER 10POS SMT VERT 30AU

11

33

55

77

99

22

44

66

88

1010

R420

4.7

k

R384

17.4

k

C684

4.7

uF

03-09-15 RvR

ADM7171ACPZ-R7

U57

IC REG LDO ADJ 1A 8LFCSP

SS4

EN5

VIN7

VIN8 VOUT

1

VOUT2

SENSE3

GND6

GNDPAD9

R382 1k

C688

10uF

08-10-14 EM

TXB0104RGYR

U403

IC VOLT-LEVEL TRANSLATOR 14-QFN

VCCA1

A12

A23

A34

A45

NC16

GND7

OE8

NC29

B410B311B212B113

VCCB14

GND_PAD15

C41

0.1

uF

R3810

R421

4.7

k

C43

0.1

uF

D2LNJ347W83RA

C411

0.1

uF

C690

12pF

R422

0DN

S

C685

4.7

uF

R425 1k

C412

0.1

uF

C40

0.1

uF

C39

0.1

uF

C46

3.3

uF

C686

1000pF

C691

12pF

C38

0.1

uF

R385

12k

R474

1k

C44

0.1

uF

R410 33

L83

220

C47

0.1

uF

R423

0DN

S

C410

0.1

uF

R411 33

SPI_SDIO

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

GPIO[0]

GPIO[4]

GPIO[1]

GPIO[5]

GPIO[9]

GPIO[2] GPIO[3]

Note for Silkcreen:Place GPIO[x] lable close to eachcorresponding LED and Test point.

SILKSCRN:

H L

VCC_GPIO_DC

VCC_GPIO_DC

VCC_GPIO_DC

VCC_GPIO_DC

VCC_GPIO_DC

VCC_GPIO_DC

VCC_GPIO_DC VCC_GPIO_DC

GPIO06

GPIO16

GPIO26

GPIO36

GPIO46

GPIO56

GPIO96

OF

PROJECT NAME

DRAWN

CHECK

DESIGN TITLE

DRAWING NUMBER REVISION

RELEASE DATE SHEET

SUBTITLE

1.2SK-10280-01

IDT8A34001

95

Fidus Systems375 Terry Fox Drive, Ottawa, ON K2K 0J8

Indira3

RK

DB

RK

27 October 2016

GPIO LEDs

OF

PROJECT NAME

DRAWN

CHECK

DESIGN TITLE

DRAWING NUMBER REVISION

RELEASE DATE SHEET

SUBTITLE

1.2SK-10280-01

IDT8A34001

95

Fidus Systems375 Terry Fox Drive, Ottawa, ON K2K 0J8

Indira3

RK

DB

RK

27 October 2016

GPIO LEDs

OF

PROJECT NAME

DRAWN

CHECK

DESIGN TITLE

DRAWING NUMBER REVISION

RELEASE DATE SHEET

SUBTITLE

1.2SK-10280-01

IDT8A34001

95

Fidus Systems375 Terry Fox Drive, Ottawa, ON K2K 0J8

Indira3

RK

DB

RK

27 October 2016

GPIO LEDs

R431 1k

TP6

R428 1k

R4871k

R4961k

U405

DIP_SW8

VCC1

nc12

nc23

nc34

nc45

nc56

nc67

VEE8

s89s710s611s512s413s314s215s116

R4951k

TP2

R4921k

R4881k

R432 1k

TP11

TP7

R429 1k

TP3

D6

LNJ347W83RA

TP4

R426 1k

R4911k

TP5

R427 1k

D4

LNJ347W83RA

D11

LNJ347W83RA

R430 1k

D9

LNJ347W83RA

D8

LNJ347W83RA

D7

LNJ347W83RA

R5001k

D5

LNJ347W83RA

GPIO0

GPIO1

GPIO3

GPIO4

GPIO5

GPIO2

GPIO9

GPIO0

GPIO2

GPIO0GPIO1

GPIO3GPIO4GPIO5

GPIO4

GPIO1

GPIO5

GPIO9

GPIO2 GPIO3

GPIO9

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Place sockets to match spacing of through-hole crystal

Place close to crystal Y3

SILKSCRN:OSCI

SILKSCRN:JUMPER IN = WP OFF

SILKSCRN:RESET

JP12~JP15 Default Jump Up

SPI Bus

I2 Bus

SILKSCRN:JUMPER IN = JTAG

VCC_GPIO_DCVCC_GPIO_DC

3V3

5V0

VCC_GPIO_DC

CLK_FTDI_PLL_SCL_OD4

FTDI_PLL_SDA_OD4

SPI_SCLK4

SPI_SDIO4

SPI_SDI4

SPI_CSN4

OSCI

OSCO

PLL_I2C_SDA_SDI

PLL_I2C_SDA_CSN

PLL_I2C_SCL_SCLK

PLL_I2C_SDA_SDIO

TST_CHIP_RST_N_OD

JTAG_SEL

OF

PROJECT NAME

DRAWN

CHECK

DESIGN TITLE

DRAWING NUMBER REVISION

RELEASE DATE SHEET

SUBTITLE

1.2SK-10280-01

IDT8A34001

96

Fidus Systems375 Terry Fox Drive, Ottawa, ON K2K 0J8

Indira3

DB

DB

DB

27 October 2016

PLL Core

OF

PROJECT NAME

DRAWN

CHECK

DESIGN TITLE

DRAWING NUMBER REVISION

RELEASE DATE SHEET

SUBTITLE

1.2SK-10280-01

IDT8A34001

96

Fidus Systems375 Terry Fox Drive, Ottawa, ON K2K 0J8

Indira3

DB

DB

DB

27 October 2016

PLL Core

OF

PROJECT NAME

DRAWN

CHECK

DESIGN TITLE

DRAWING NUMBER REVISION

RELEASE DATE SHEET

SUBTITLE

1.2SK-10280-01

IDT8A34001

96

Fidus Systems375 Terry Fox Drive, Ottawa, ON K2K 0J8

Indira3

DB

DB

DB

27 October 2016

PLL Core

R118 33

R442

10k

R120 33

R471 0DNS

15-0

1-1

6R

vR

0552-2-15-01-11-27-10-0P2DNS

1

JP15

EEPROM_SEL

NC1NC2

DM25-11-15

Y3

CX3225GB50000P0HPQCCCRYSTAL 50.000MHZ 20PPM 18PF SMD

1 3

24

04-06-14RvR

SW1

KMR211GLFSSWITCH TACTILE SPST-NO 0.05A 32V

12

5

3 4

R122 33

R450

0

R470 0DNS

R121 33

R446

4.7

k

EM08-04-14

U407

TPS3808G01DRVRADJ SUPPLY MONITOR PRG DLY 6QFN

CT3

GND5

RESET_N6

VDD1

SENSE2

MR_N4

GND_PAD7

C426

0.0

1uF

RvR11-11-14

A08-LC-TT

P3

IC SOCKET STRAIGHT 8POS TIN

11

22

33

44

55667788

28-01-14 RvR

U408

24LC64-I/PIC EEPROM 64KBIT 400KHZ 8DIP

DNS

A01

A12

A23

VSS4

SDA5 SCL6

WP7

VCC8

18-03-13 RK

TSM-102-01-T-SV

J7

CONN HEADER 2POS 0.1IN PITCH SMD

11

22

18-03-13 RK

TSM-102-01-T-SV

J83

CONN HEADER 2POS 0.1IN PITCH SMD

11

22

R451

4.7

kD

NS

JP14

EEPROM_SEL

R469 0DNS

R445

1k

R452

4.7

kD

NS

R117 33

R455

4.7

k

C765 10pF

R468 39

15-0

1-1

6R

vR

0552-2-15-01-11-27-10-0P1DNS

1

R447

4.7

k

R454

4.7

k

R449 1k

C759 1.0uFDNS

R119 33

R444

10k

R453

4.7

k

JP13

EEPROM_SEL

RK19-03-13

J45

5-1814832-1

R472 0DNS

C417

0.1

uF

Y2

A-50.000-12-EXTCRYSTAL 50MHZ 12PF 30PPM HC49/U

DNS

C415

0.1

uF

R935

4.7

k

R443

10k

DN

SC

416

0.1

uF

DN

S

R473

10

DN

S

JP12

EEPROM_SEL

C766 10pF

R448

4.7

k

PLL_I2C_SCL_SCLKPLL_I2C_SDA_SDIO

TST_CHIP_RST_N_OD

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

SILKSCRN:CLK0_N

SILKSCRN:CLK0_P

PLACE NEAR OSCILLATOR

SILKSCRN:CLK1_N

SILKSCRN:CLK1_P

SILKSCRN:CLK2_N

SILKSCRN:CLK2_P

SILKSCRN:CLK3_N

SILKSCRN:CLK3_P

SILKSCRN:CLK4_N

SILKSCRN:CLK4_P

SILKSCRN:CLK OSC

3V3

VDD_CLK0VDD_CLK0

VDD_CLK0

VDD_CLK0

VDD_CLK0

CLK_CLK0_P

CLK_CLK0_N

CLK_CLK1_P

CLK_CLK1_N

CLK_CLK2_P

CLK_CLK2_N

CLK_CLK3_P

CLK_CLK3_N

CLK_CLK4_P

CLK_CLK4_N

OF

PROJECT NAME

DRAWN

CHECK

DESIGN TITLE

DRAWING NUMBER REVISION

RELEASE DATE SHEET

SUBTITLE

1.2SK-10280-01

IDT8A34001

97

Fidus Systems375 Terry Fox Drive, Ottawa, ON K2K 0J8

Indira3

RK

DB

RK

27 October 2016

PLL Input Clocks

OF

PROJECT NAME

DRAWN

CHECK

DESIGN TITLE

DRAWING NUMBER REVISION

RELEASE DATE SHEET

SUBTITLE

1.2SK-10280-01

IDT8A34001

97

Fidus Systems375 Terry Fox Drive, Ottawa, ON K2K 0J8

Indira3

RK

DB

RK

27 October 2016

PLL Input Clocks

OF

PROJECT NAME

DRAWN

CHECK

DESIGN TITLE

DRAWING NUMBER REVISION

RELEASE DATE SHEET

SUBTITLE

1.2SK-10280-01

IDT8A34001

97

Fidus Systems375 Terry Fox Drive, Ottawa, ON K2K 0J8

Indira3

RK

DB

RK

27 October 2016

PLL Input Clocks

C881 1.0uF

R913 0

R795

2.6

7k

R926 49.9

R768

2.6

7k

C895 1.0uF

R920 0

C884 1.0uF

R791

2.6

7k

C425 1.0uF

R781

2.6

7k

C885 1.0uF

R776

2.6

7k

13-11-13 RvR

MH6

MTG250C125PPLATED MH 250MIL PAD 125MIL DIAMETER

1

20-03-13 RK

Y4

M6141LF12.8MHZ MERC 9X7 HOT CMOS 3.3V OCXO

VCC4

NC1 OUT

3

GND2

RK19-03-13

J23

5-1814832-1

R912 0

R143 33DNS

R922 49.9

C893 1.0uF

13-11-13 RvR

MH1

MTG250C125PPLATED MH 250MIL PAD 125MIL DIAMETER

1

R801

2.6

7k

R924 0

R773

2.6

7k

C883 1.0uF

RK19-03-13

J26

5-1814832-1CONN SOCKET SMA STR DIE CAST PCB

R767 49.9

R786

2.6

7k

R460

2.6

7k

R771

2.6

7k

13-11-13 RvR

MH7

MTG250C125PPLATED MH 250MIL PAD 125MIL DIAMETER

1

L97 220

RK19-03-13

J21

5-1814832-1

RK19-03-13

J24

5-1814832-1CONN SOCKET SMA STR DIE CAST PCB

13-11-13 RvR

MH10

MTG250C125PPLATED MH 250MIL PAD 125MIL DIAMETER

1

13-11-13 RvR

MH2

MTG250C125PPLATED MH 250MIL PAD 125MIL DIAMETER

1

R796

2.6

7k

R511 49.9

R789 49.9

R769

2.6

7k

R916 0

R779 49.9

R792

2.6

7k

R782

2.6

7k

RK 19-03-13

J82

5-1814832-1

13-11-13 RvR

MH8

MTG250C125PPLATED MH 250MIL PAD 125MIL DIAMETER

1

C196

0.1

uF

RK19-03-13

J62

5-1814832-1

R799 49.9

RK19-03-13

J22

5-1814832-1CONN SOCKET SMA STR DIE CAST PCB

R772 49.9

13-11-13 RvR

MH3

MTG250C125PPLATED MH 250MIL PAD 125MIL DIAMETER

1

R802

2.6

7k

R774

2.6

7k

R914 49.9

RK19-03-13

J19

5-1814832-1

C195

10uF

13-11-13 RvR

MH9

MTG250C125PPLATED MH 250MIL PAD 125MIL DIAMETER

1

13-11-13 RvR

MH11

MTG250C125PPLATED MH 250MIL PAD 125MIL DIAMETER

1

RK19-03-13

J63

5-1814832-1CONN SOCKET SMA STR DIE CAST PCB

R765

2.6

7k

13-11-13 RvR

MH4

MTG250C125PPLATED MH 250MIL PAD 125MIL DIAMETER

1

C844

0.1

uF

C882 1.0uF

RK19-03-13

J20

5-1814832-1

R915 49.9

R785

2.6

7k

TP19

13-11-13 RvR

MH12

MTG250C125PPLATED MH 250MIL PAD 125MIL DIAMETER

1

R775

2.6

7k

C891 1.0uF

R770

2.6

7k

13-11-13 RvR

MH5

MTG250C125PPLATED MH 250MIL PAD 125MIL DIAMETER

1

C887 1.0uF

RK19-03-13

J25

5-1814832-1

CLK_EXT_OSC

CLK_CLOCK0_N

CLK_CLOCK0_P

CLK_CLOCK1_P

CLK_CLOCK1_N

CLK_CLOCK2_P

CLK_CLOCK2_N

CLK_CLOCK3_P

CLK_CLOCK3_N

CLK_CLOCK4_P

CLK_CLOCK4_N

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

SILKSCRN:Q0_P

SILKSCRN:Q1_P

SILKSCRN:Q2_P

SILKSCRN:Q3_P

SILKSCRN:Q7_P

SILKSCRN:Q6_P

SILKSCRN:Q5_P

SILKSCRN:Q4_P

SILKSCRN:Q0_N

SILKSCRN:Q1_N

SILKSCRN:Q2_N

SILKSCRN:Q3_N

SILKSCRN:Q7_N

SILKSCRN:Q6_N

SILKSCRN:Q5_N

SILKSCRN:Q4_N

SILKSCRN:Q11_P

SILKSCRN:Q10_P

SILKSCRN:Q9_P

SILKSCRN:Q8_P

SILKSCRN:Q11_N

SILKSCRN:Q10_N

SILKSCRN:Q9_N

SILKSCRN:Q8_N

PLACE PARALLELTERMINATIONSCLOSE TO U58

CLK_Q0_P7

CLK_Q0_N7

CLK_Q1_P7

CLK_Q1_N7

CLK_Q2_P7

CLK_Q2_N7

CLK_Q4_P7

CLK_Q4_N7

CLK_Q5_P7

CLK_Q5_N7

CLK_Q3_P7

CLK_Q3_N7

CLK_Q6_P7

CLK_Q6_N7

CLK_Q7_P7

CLK_Q7_N7

CLK_Q8_P7

CLK_Q8_N7

CLK_Q9_P7

CLK_Q9_N7

CLK_Q10_P7

CLK_Q10_N7

CLK_Q11_P7

CLK_Q11_N7

OF

PROJECT NAME

DRAWN

CHECK

DESIGN TITLE

DRAWING NUMBER REVISION

RELEASE DATE SHEET

SUBTITLE

1.2SK-10280-01

IDT8A34001

98

Fidus Systems375 Terry Fox Drive, Ottawa, ON K2K 0J8

Indira3

DB

DB

DB

27 October 2016

PLL Output Clocks

OF

PROJECT NAME

DRAWN

CHECK

DESIGN TITLE

DRAWING NUMBER REVISION

RELEASE DATE SHEET

SUBTITLE

1.2SK-10280-01

IDT8A34001

98

Fidus Systems375 Terry Fox Drive, Ottawa, ON K2K 0J8

Indira3

DB

DB

DB

27 October 2016

PLL Output Clocks

OF

PROJECT NAME

DRAWN

CHECK

DESIGN TITLE

DRAWING NUMBER REVISION

RELEASE DATE SHEET

SUBTITLE

1.2SK-10280-01

IDT8A34001

98

Fidus Systems375 Terry Fox Drive, Ottawa, ON K2K 0J8

Indira3

DB

DB

DB

27 October 2016

PLL Output Clocks

RK 19-03-13

J29

5-1814832-1

R761

100

R729 0

R737 0

R759

100

R735 0

R746 0

R752

100

RK 19-03-13

J40

5-1814832-1CONN SOCKET SMA STR DIE CAST PCB

R739 0

R750

100

R736 0

RK 19-03-13

J34

5-1814832-1CONN SOCKET SMA STR DIE CAST PCB

R748 0

RK 19-03-13

J41

5-1814832-1

R741

100

R744 0

RK 19-03-13

J76

5-1814832-1

R756 0

RK 19-03-13

J74

5-1814832-1

RK 19-03-13

J31

5-1814832-1

R734

100

R732

100

R753 0

R743

100

RK 19-03-13

J72

5-1814832-1

RK 19-03-13

J35

5-1814832-1

RK 19-03-13

J43

5-1814832-1

R757 0

RK 19-03-13

J42

5-1814832-1CONN SOCKET SMA STR DIE CAST PCB

R733

100

RK 19-03-13

J70

5-1814832-1

R763 0

R758 0

RK 19-03-13

J77

5-1814832-1CONN SOCKET SMA STR DIE CAST PCB

RK 19-03-13

J30

5-1814832-1CONN SOCKET SMA STR DIE CAST PCB

R747 0

RK 19-03-13

J75

5-1814832-1CONN SOCKET SMA STR DIE CAST PCB

RK 19-03-13

J32

5-1814832-1CONN SOCKET SMA STR DIE CAST PCB

R742

100

R764 0

R749 0

RK 19-03-13

J37

5-1814832-1

RK 19-03-13

J73

5-1814832-1CONN SOCKET SMA STR DIE CAST PCB

R762 0

RK 19-03-13

J44

5-1814832-1CONN SOCKET SMA STR DIE CAST PCB

RK 19-03-13

J36

5-1814832-1CONN SOCKET SMA STR DIE CAST PCB

R751

100

RK 19-03-13

J71

5-1814832-1CONN SOCKET SMA STR DIE CAST PCB

R754 0

R738 0

R755 0

R760

100

R730 0

RK 19-03-13

J39

5-1814832-1

R731 0

RK 19-03-13

J38

5-1814832-1CONN SOCKET SMA STR DIE CAST PCB

R740 0

R745 0

RK 19-03-13

J33

5-1814832-1

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

VDD_FOD

VDD_CLK0

VDDO_Q8_3_5

VDDO_Q0_9_6 VDDO_Q2_4_11

VDDO_Q1_10_7

VDDA

VDD_FOD_0

VDD_FOD_2

VDD_FOD_5

VDDA_0

VDDA_1

VDDO_Q8

VDDO_Q3

VDDO_Q5

VDDO_Q9

VDDO_Q6

VDDO_Q0

VDDO_Q1

VDDO_Q10

VDDO_Q7

VDDO_Q2

VDDO_Q4

VDDO_Q11

VDD_CLK0_0

OF

PROJECT NAME

DRAWN

CHECK

DESIGN TITLE

DRAWING NUMBER REVISION

RELEASE DATE SHEET

SUBTITLE

1.2SK-10280-01

IDT8A34001

99

Fidus Systems375 Terry Fox Drive, Ottawa, ON K2K 0J8

Indira3

RK

DB

RK

27 October 2016

PLL Power

OF

PROJECT NAME

DRAWN

CHECK

DESIGN TITLE

DRAWING NUMBER REVISION

RELEASE DATE SHEET

SUBTITLE

1.2SK-10280-01

IDT8A34001

99

Fidus Systems375 Terry Fox Drive, Ottawa, ON K2K 0J8

Indira3

RK

DB

RK

27 October 2016

PLL Power

OF

PROJECT NAME

DRAWN

CHECK

DESIGN TITLE

DRAWING NUMBER REVISION

RELEASE DATE SHEET

SUBTITLE

1.2SK-10280-01

IDT8A34001

99

Fidus Systems375 Terry Fox Drive, Ottawa, ON K2K 0J8

Indira3

RK

DB

RK

27 October 2016

PLL Power

C93710uF

C708

0.1

uF

L87 220

L107 220

C87510uF

L109 220

C719

10uF

R8970

L94 220C726

0.1

uF

R8920

C724

0.1

uF

C731

10uF

L104 220

C9380.1

uF

C727

10uF

L5 220

L106 220

C701

10uF

C722

0.1

uF

C94110uF

R8860

R8940

R8750

L93 220

C717

10uF

R8960

L110 220

R8880

C94910uF

L4 220

C94510uF

R887

0

C8760.1

uF

C699

10uF

L108 220

C702

0.1

uF

C732

0.1

uF

C9420.1

uF

C860

0.1

uF

C720

0.1

uF

R879

0

C715

10uF

C728

0.1

uF

C94310uF

C93910uF

R8760C696

10uF

C700

0.1

uF

C9460.1

uF

R882

0

C729

10uF

C9500.1

uF

R8990

C94710uF

C718

0.1

uF

L90 220

C95110uF

R8950

C697

0.1

uF

C9400.1

uF

C716

0.1

uF

C9440.1

uF

R8890L103 220

C730

0.1

uF

R8980

L96 220

R8910

C9520.1

uF

C698

0.1

uF

C733

10uF

C707

10uF

C9480.1

uF

R8850C725

10uF

L100 220

C723

10uF

C714

0.1

uF

L105 220

L95 220

C734

0.1

uF

C8720.1

uF

R8770

C721

10uF

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