a dry electrode low power cmos eeg...
TRANSCRIPT
A DRY ELECTRODE LOW POWER
CMOS EEG ACQUISITION SOC FOR
SEIZURE DETECTION
TEAM 6: MATTHIEU DURBEC, VALENTIN BERANGER,
KARIM ELOUELDRHIRI
ECE 6414 – SPRING 2017
• Project motivation
• Design overview
• Body-Electrode Interface
• Voltage references
• Chopper Stabilized LNA
• Low Pass filter
• ADC Driver
• SAR-ADC
• Conclusion
OUTLINE
Epilepsy neurological disorder Abnormal firing in a group of neurons Clinical onset:
Loss of coherence/cognition Loss of motor control Convulsions
Objective: sense these signals and establish correlation with clinical onset
Use of machine learning techniques and training to patient-specific data
PROJECT MOTIVATION
Multi Channel EEG Acquisition system Wireless low power chip Digitized EEG signals transmitted for
processing Machine learning algorithm for processing
channel signals IC design specifications
DESIGN OVERVIEW
Dry-electrode model: Gel free solution Increased impedance in the skin-electrode interface
Circuit model: Resistor : body Resistor & Capacitance: Stratum Corneum
Electrode offset voltage (EOV): 10-100mV EEG Signals: 10-50 μV EEG frequency range: 0.5 - 100 Hz
BODY-ELECTRODE INTERFACE
A chopper stabilized amplifier system consists of modulating and demodulating carriers with period T= 1/fchop, where fchop is the chopper frequency.
DC servo loop uses for high pass filter and cancel residual offset
Chopping reduces the DC input impedance of the sensing front-end. The low input impedance can result in attenuation of the weak input signals and degradation in noise performance
Chopper-stabilized LNA
Chopping -> reduces the flicker noise
Upmodulated flicker noise and offset show up as ripples at the output of the amplifier
Sol :a parallel-RC impedance is added immediately after the 1st stage.
A fully differential chopper amplifier
The EEG signal bandwidth is in the range 0.5-100 Hz
Pseudo-resistor larger than 100 GΩ in the feedback loop. Proccess variations (factor of 100).
Duty-cycled resistors to enable high linearity and reliability
DC servo loop
Chopping reduces the DC input impedance of the sensing front-end
-> Impedance boosting.
Auxialiary path
Impedance boosting
The auxiliary-path used charges the input caps Cin at the beginning of every chopping phase using aux-buffers reducing the charge provided by the input voltage, thus boosting Zin.
Impedance boosting
Vin provides zero charge ->
Problem : Amplification of aux-buffer offset and flicker noise
Impedance boosting
Sol: Voff is up-modulated to fc/4 by using mixers M1 and M2
Voff creates a benign ripple instead of a DC offset.
Storage capacitors Caux=8pF assist the aux-buffers at the beginning of the pre-charge phase.
Higher input impedance without increasing power consumption
Impedance boosting
Results
Results
Metrics Target SpecificationVoltage Supply 3.1V
Power consumption 67µWGain 43.5dBBW 0.5Hz-10kHz
CMRR 55dBInput impedance 8GΩ @1Hz
Input-referred noise 0.75µVRMS (1-200Hz)5.27µVRMS(200-10kHz)
Ripple rejection yesProcess 0.6 um
Power supply: 3.7V Rechargeable Polymer Li-Ion
battery Tenergy model PL 401225
Bandgap Reference Circuit: Constant Vref independent of
temperature swings CTAT, PTAT and Start-up circuit
Generated Vref: 3.14V at Vdd
VOLTAGE REFERENCES: BGR
VOLTAGE REFERENCES: BGR
Voltage Regulator: Ensures constant voltage across the
system Negative feedback control loop Supplies reference voltage to the
entire chip Output of the regulator 95% the
voltage reference generated by BGR
VOLTAGE REFERENCES: REGULATOR
VOLTAGE REFERENCES: REGULATOR
VOLTAGE REFERENCES: REGULATOR
Fully differential topology with common mode feedback and gain enhancement
Provide frequency cut off for EEG signals and gain
Low pass filter specifications
LOW PASS FILTER
LOW PASS FILTER
Drive capacitance sample & hold of the ADC
Fully differential amplifier with common mode feedback and gain enhancement
Additional gain to reach the ADC dynamic range
ADC Driver specifications
ADC DRIVER
ADC DRIVER
ADC DRIVER
12-bit successive approximation register converter
6-bit main-DAC and 6-bit sub-DAC architecture, both implemented as passive charge-redistribution capacitor arrays, providing an inherent sample and hold function
Energy per conversion down to very low speeds (i.e., around 600 S/s)
SAR ADC Design
Three steps: purging, auto-zeroing and sampling
Management of clocking is crucial in this design
Use of a consequent number of switches
SAR ADC Operation Principle
Charge scaling DAC
Unit capacitance - 500fF
Importance of transmission gate
Digital to Analog Converter (DAC)
Successive Approximation Register
Specifications
Comparison with State of the Art
CONCLUSION
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REFERENCES
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