noise canceling in 1-d data: presentation #4

Noise Canceling in 1-D Data: Presentation #4

Seri Rahayu Abd RaufFatima BoujarwahJuan ChenLiyana Mohd SharippArti Thumar

M2

Feb 14th, 2005Gate Level Design

Overall Project Objective: Implementing Noise Cancellation Algorithm in Hardware

Project Manager: Bobby Colyer

Status

• Design proposal (Done)

• Architecture proposal (Done)

• Size Estimates and Floorplan:– Structural Verilog (Done)– Revised Floorplan (Done)

• To be done:– Schematics (85%)– Layout (5%)– Spice simulation

Previous Block Diagram

Final Block Diagram

Structural Verilog Output

Behavioral Verilog OutputStructural Verilog Output

Similar Output Values.

Differences due to 16-bit Floating Point Units

Result Comparison

New Transistor Count…

PartLast Week’s Transistors

New Transistors

16-bit FPA 5x1700 = 8500 3x 4154 = 12462

16-bit FPM 3x2028 = 6084 3x 3858 = 11574

Registers 10x16x14 = 2240 7x16x14 = 1568

ROM 800 800

Converter 2x312 = 624 2x312 = 624

MUX/DEMUX 384 384

Adder 248 248

Counter 214 214

Alternator 64 64

Total≈ 19146 + Misc ≈ 22000

≈ 27938 + Misc ≈ 30000

Area EstimatesPart Last week’s Area (µ²) New Area (µ²)

16-bit FPA 5x140x110 = 77000 3x140x140 = 58800

16-bit FPM 3x140x106 = 44520 3x170x170 = 85800

16-bit Register 10x33x24 = 7920 7x33x24 = 5544

ROM 43x180 = 7740 43x180 = 7740

MUX/DEMUX 6x6.8x57 = 2325.6 6x6.8x57 = 2325.6

Converter 2x20x40 = 1600 2x20x40 = 1600

Counter 1004.5 1004.5

Adder 28x35 = 980 28x35 = 980

Alternator 1x48 = 48 1x48 = 48

Total≈ 143138 µ² + Misc ≈ 190000 µ²

≈ 163842µ² + Misc ≈ 200000 µ²

Revised Floorplan

Mux 16-bit 2:1 Layout

Schematics

ROM

Alignment Shifter

Leading Zero Counter

Rounding Unit

Normalizing Unit

Wallace Tree Multiplier

Input of ROM Table Testbench

Test Results for Sine

Time = 40ns Input: 2.52 (21st value) SinOutput: 00110001 = 0.5823

Test Results for Cosine

Time = 40ns Input: 010100 (21st value) CosOutput: 10110101 = -0.8130

Critical Path Estimation

• Cycle 2 will be longer than Cycle 1 because it uses 3 FPM + 2 FPA while Cycle 1 uses 2 FPM + 3 FPA

Last week’s challenges…

• Finalizing out designs for the floating point adders and multipliers– Wallace tree multiplier vs

Array multiplier• Choose Wallace implementation

because it saves 10% of power – Leading zero counter for

normalizing block • Found a smaller implementation

of the normalizing block

This week’s challenges…

• Completing and Testing Top level Schematic

• Creating Layouts for Floating Point Multipliers and Adders with different shapes

• Clock Skew and other Timing issues

• Transistor count .. again..

Questions?