bit cell ratio testing
DESCRIPTION
Bit Cell Ratio Testing. Thin Cell. Advantages: Smallest possible area of 6T Bit Cell, Can be mirrored (saves area = can reduce distance between n-wells and p-wells). 2by2 Array of Thin Cell Layout. - PowerPoint PPT PresentationTRANSCRIPT
![Page 1: Bit Cell Ratio Testing](https://reader036.vdocument.in/reader036/viewer/2022081502/5681623b550346895dd26d96/html5/thumbnails/1.jpg)
Bit Cell Ratio Testing
![Page 2: Bit Cell Ratio Testing](https://reader036.vdocument.in/reader036/viewer/2022081502/5681623b550346895dd26d96/html5/thumbnails/2.jpg)
Thin CellAdvantages: Smallest possible area of 6T Bit Cell, Can be mirrored (saves area = can reduce distance between n-wells and p-wells)
![Page 3: Bit Cell Ratio Testing](https://reader036.vdocument.in/reader036/viewer/2022081502/5681623b550346895dd26d96/html5/thumbnails/3.jpg)
2by2 Array of Thin Cell LayoutAdvantages: WLs are horizontal, VDD/VSS/BL/BLB are vertical, Mirrored Thin Cells save area and make it easy to add N/P Taps, Easy to Cascade to other 2by2 Arrays
![Page 4: Bit Cell Ratio Testing](https://reader036.vdocument.in/reader036/viewer/2022081502/5681623b550346895dd26d96/html5/thumbnails/4.jpg)
Buffers (First Inv = Min Size, Second Inv = 4x Min)Advantages: Needs to be thin to have 2 Buffers to be smaller than the width of a Thin cell, Easy to souce VDD and VSS, Easily connect inputs and outputs (top and bottom of diagram), Easily N-Tapped, P-Tapped
![Page 5: Bit Cell Ratio Testing](https://reader036.vdocument.in/reader036/viewer/2022081502/5681623b550346895dd26d96/html5/thumbnails/5.jpg)
Word Select (1to2 DEMUX) – Sends Data to ColumnAdvantages: Data comes from top, Address from side (design decision), N-wells together, P-wells together (easy to add N-taps and P-taps), easily mirrored
![Page 6: Bit Cell Ratio Testing](https://reader036.vdocument.in/reader036/viewer/2022081502/5681623b550346895dd26d96/html5/thumbnails/6.jpg)
TX Gates (4x Min Size) – Disconnects BL Drivers, Avoids Fight between Bitcells and BL DriversAdvantages: Outputs nicely spread apart, Select lines are all tied together and come in from side, Inputs from top, Outputs on bottom, Easily N-Tapped and P-Tapped from left or right side, Easily mirrored.
![Page 7: Bit Cell Ratio Testing](https://reader036.vdocument.in/reader036/viewer/2022081502/5681623b550346895dd26d96/html5/thumbnails/7.jpg)
Precharge/BL/BLB GeneratorAdvantages: Pitched Matched (Made it as thin as possible while fitting it in with rest of circuit), BL/BLB are on the outsides running vertically, Easily P-Tapped, N-Tapped, Thin, PRECH, WRITE, and Data Signals
![Page 8: Bit Cell Ratio Testing](https://reader036.vdocument.in/reader036/viewer/2022081502/5681623b550346895dd26d96/html5/thumbnails/8.jpg)
Sense AmpAdvantages: Wanted as short as possible, but width had to be smaller than width of Thin Cell, Similar to Thin Cell by using Cross Coupled Inverter layout, Easily mirrored, Easily P-Tapped, N-Taped
![Page 9: Bit Cell Ratio Testing](https://reader036.vdocument.in/reader036/viewer/2022081502/5681623b550346895dd26d96/html5/thumbnails/9.jpg)
1 SRAM BlockAdvantages: Symmetrical, Pitched Match (All separate components fit in nicely), 1 VDD/VSS source for Bit Cell Array, Can be mirrored, Most inputs, Inputs come in from Left and Top side
![Page 10: Bit Cell Ratio Testing](https://reader036.vdocument.in/reader036/viewer/2022081502/5681623b550346895dd26d96/html5/thumbnails/10.jpg)
Block Pair Merger Schematic
![Page 11: Bit Cell Ratio Testing](https://reader036.vdocument.in/reader036/viewer/2022081502/5681623b550346895dd26d96/html5/thumbnails/11.jpg)
Block Pair Merger
![Page 12: Bit Cell Ratio Testing](https://reader036.vdocument.in/reader036/viewer/2022081502/5681623b550346895dd26d96/html5/thumbnails/12.jpg)
Block Pair
![Page 13: Bit Cell Ratio Testing](https://reader036.vdocument.in/reader036/viewer/2022081502/5681623b550346895dd26d96/html5/thumbnails/13.jpg)
Decoder
![Page 14: Bit Cell Ratio Testing](https://reader036.vdocument.in/reader036/viewer/2022081502/5681623b550346895dd26d96/html5/thumbnails/14.jpg)
Layout Diagram(Connections Removed to Reduce Clutter)