ch08 sequential logic...wk (glwlrq &odvvlilfdwlrq ri orjlf flufxlwv %dvhg rq ehkdylru ... 7 $ hq...

CMOS Digital Integrated Circuits

Chapter 8Sequential MOS LogicCircuits

S.M. Kang, Y. Leblebici, and

C. Kim

1 Copyright © 2014 McGraw-Hill Education. Permission required for reproduction or display.

Sequential Circuit

Combinational block +memory block

Introduction (1)

© CMOS Digital Integrated Circuits – 4th Edition2

Classification of logic circuits

Based on behavior

Static behavior of the two inverter basic bistable elements

Bistable Elements : Cross Coupled Inverter


1 2

2 1

o i

o i

v v

v v

VTC of the two inverters & qualitative

view of the potential energy levels

Time domain behaviorCircuit diagram

Bistable Elements : Circuit


Stable operating point : Two energy minima

Unstable operating point: One energy maximum All four transistors are in saturation

.

Bistable Elements : Small Signal (1) Small signal input and output currents of the inverters


1 2 2 2 1 1

1 21 2

1 21 2

, (8.1)

,

,

g d m g g d m g

g gg g

g gg g g g

i i g v i i g v

q qv v

C C

dv dvi C i C

dt dt

1 22 1,g g

m g g m g g

dv dvg v C g v C

dt dt 1 2

2 1,m m

g g

g gdq dqq q

C dt C dt

22 2

1 11 12 2

gm m

g m g

Cg gd q d qq q

C g dt dt C

21

1 02 20

1 g

m

Cd qq with

dt g

(8.1)=>(8.3) (8.2)

τ0

Bistable Elements : Small Signal (2) The time domain solution

The time domain expressions (t is a large value)


0 01 0 1 1 0 11 1 1

(0) ' (0) (0) ' (0)( ) , (0) (0)

2 2

t t

g g

q q q qq t e e q C v

q

1 2 2 1,g o g ov v v v 0 0

0 0

2 2 0 2 2 0 2

1 1 0 1 1 0 1

1 1( ) ( (0) ' (0)) ( (0) ' (0))

2 2

1 1( ) ( (0) ' (0)) ( (0) ' (0))

2 2

t t

o o o o o

t t

o o o o o

v t v v e v v e

v t v v e v v e

0

0

1 1 0 1

2 2 0 2

1( ) ( (0) ' (0))

2

1( ) ( (0) ' (0))

2

t

o o o

t

o o o

v t v v e

v t v v e

Phase Plane Representation

The bistable circuit behavior


1

2

:

:o th OH OL

o th OL OH

v V V or V

v V V or V

1 2,o th o thv V v V

Stable

Unstable

Propagation of a Transient Signal


01

1

( )

(0)

t

o

o

v te

v

0

T

nA e

The time domain behavior :

The loop gain:

SR Latch CircuitSR latch circuit based on

NOR2 gates


Gate level schematic and block diagram

Truth Table and Operation ModeTruth table of the NOR based SR latch circuit

Operation mode of the NOR based SR latch circuit


Total lumped capacitance at each output node

Circuit Diagram of the SR Latch


,2 ,5 ,3 ,4 ,7 ,7 ,8

,3 ,7 ,1 ,4 ,5 ,5 ,6

Q gb gb db db db sb db

gb gb db db db sb dbQ

C C C C C C C C

C C C C C C C C

Rise time : , , ,( ) ( 2) ( 2)rise Q rise Q fall QSR latch NOR NOR

CMOS SR Latch : Another Type Pseudo nMOS SR latch

circuit based on NOR2 gates


SR latch based on NAND2 gates

NAND Based SR LatchGate level schematic

& Block diagram


Pseudo-nMOS NAND-based SR latch circuit

Clocked SR LatchGate level schematic


Input and output waveform

Level sensitive circuit

Clocked NOR Based SR Latch : AOIAOI-based implementation of the clocked NOR-based

SR-latch Circuit


very small transistor count

Clocked NAND-Based SR Latch CircuitSchematic w/ active low i/p (CK=S=0 for set or CK=R=0 for reset)


Schematic w/ active high i/p (CK=S=1 for set or CK=R=1 for reset)

Clocked JK LatchGate level schematic

SR-latch : indeterminate when both inputs S and R are activated

JK latch : adding two feedback lines from the outputs to the inputs


Clocked JK Latch : All NAND Implementation

All-NAND implementation of the clocked JK latch circuit


Clocked JK Latch : Another TypeClocked NOR-based JK latch


CMOS AOI JK latch

Clocked JK Latch : Truth Table

Clocked JK Latch : Toggle SwitchToggle Switch

If both inputs are equal to logic 1, output will oscillate.(The clock pulse width < input to output propagation delay)

JK latch is operated exclusively in this mode


Master-Slave Flip-FlopMaster-Slave Flip-Flop

Two cascaded stages are activated with opposite clock phases.


Master Slave

Master-Slave Flip-Flop : OperationClock pulse 0

Master latch inactive (slave becomes active)

Clock pulse 1 Slave latch inactive

(master becomes active)

No uncontrolled oscillation : J=K=1

Ones catching problem Unwanted o/p transition

due to glitch at i/p Sol. : edge-triggered


NOR Based Master-Slave Flip-Flop Circuit toggling when J=K=1

one stage must be active at any given time A NOR-Based master-slave flip-flop


Timing Diagram for (+)ve-edge Triggered FF


Data-Q & Clk-Q Delays


Timing Diagram for Latch


Gate-level schematic

CK : 1 Q assumes the value of the input DCK : 0 Q preserve its state

CMOS D-Latch


Block diagram

CMOS D-Latch : Version 1Constructed by

Two inverter loop + Two CMOS TG

CK:1 TG at input is activated

CK:0 TG at inverter loop is activated


CMOS D-Latch (version 1)

CMOS D-Latch : Simplified version 1 Simplified schematic

view and timing diagram


Setup time & Hold time Setup time and hold time

should be met

Any violation can cause metastability problems.

CMOS Master-Slave D-Latch : Version 2 (1)

Constructed by simply cascading two D-latch circuits

First stage (Master) : driven by CK signal

Second stage (Slave) : driven by inverted CK signal


CMOS D-Latch (Version 2)

Master Slave

Master-Slave D-latch : Version2 SimulationSimulated input and output waveforms of version2


Master-Slave D-latch : Setup Time Violation

Simulated waveforms master-slave D-latch circuit with setup time violation at 0.25ns


Master Slave D-Latch : LayoutLayout of the master-slave D-latch


C2MOS Master-Slave D-Latch (Version 3)

Constructed by four tri-state inverters


Advantages of HLFF : small D-Q delay, negative setup time, logic embedding with small penalty

Minimum delay between FF should be guaranteed (due to increased hold time)

Pulsed Latch Based Clocked Storage Elements

Hybrid latch flip-flop circuit (HLFF)


Short pulse generation inHLFF

Semi Dynamic Flip-Flop (SDFF)

SDFF to operate faster than HLFF The back-end latch has only two stacked NMOS

Disadvantage Short pulse generators : Always toggle =>large power consumption


CK

D

Q

VDD

VDD

Q

EP-SFF CircuitEP-SFF circuit and CK generator

Advantages : Large amount of time borrowing, short output delay, energy and area efficient

Disadvantage : Large hold time


Sense Amplifier Based Flip Flop (SAFF)Sensed amplifier based flip-flop circuit


Disadvantage : Large propagation delay through SR latch

Modified SAFF

To overcome large propagation delay of SAFF Cross-coupled Nand gates are replaced with a faster SR latch


Delay Comparison of CSE


0.13um CMOS technology with a supply voltage of 1.2V

Embedded Logic SDFF


D AB A+B AB+CDEmbedded 199ps 219ps 229ps 246psDiscrete 199ps 298ps 305ps 367psSpeedup 1.0 1.36 1.33 1.49

Power Consumption Portion of Chips


Power Consumption of ClockingPower consumption of a particular clocking scheme

(Dominated by dynamic power consumption)

Power dissipation by flip flops


ck scheme ck network FFP P P

2,CK network CLK line rep ck tr ck swing DD leak repP f C C C V V I

20 0 , ,

FF ff

ff i i local buf DD CLK DD leak local buf leak FF

P P

P C C C V f V I I

Ci : internal node Capacitance Co : output node Capacitanceαi : internal node transition ratio α0 : output node transition ratioClocal-buf : local clock buffer capacitance β: 1 or 2 (for double-edge) Ileak,local-buf:leakage current of local clock buffer Ileak,FF : flip flop leakage current

Low-Power CSEs


Clock-on-demand FF Conditional capture FF

Reduced swing clock FF Low-swing clock double-edge-triggered FF

Appendix: Schmitt TriggerSchmitt Trigger circuit


1) Vin=0V M1, M2 : on

M3, M4, M5 : off M6 : on (saturation), let VT,6=0.62V

2) Vin=VT0,n=0.48V M5 : starts to turn on M4 : off

Schmitt Trigger : Positive Input Sweep (1)


1.2x y DDV V V V

1.2xV V

,6 0.58z DD TV V V V

Schmitt Trigger : Positive Input Sweep (2)3) Vin = 0.6V

M4 : off (assumption) M5, M6 : on (Saturation)


2 2' '

0, ,6

5 60, ,62 2C n in T n C n DD z Tn n

in T n C n DD z T C n

E L V V E L V V Vk kW W

L LV V E L V V V E L

2

2 0.4 1.2 0.48 0.524( 1.011 1.011)0.4 (0.6 0.48) 1

(0.6 0.48) 0.4 10 1.2 0.48 0.524( 1.011 1.011) 0.4

z z

z z

V V

V V

0.18zV V

,4 0,0.6 0.18 0.42 0.48GS T nV V

M4 is indeed turned off

4) Vin=0.62V M5 : on (Linear) , M6 : on (Saturation) Vz is decreasing

M4 : Already on Vth+=0.62V (Upper logic threshold voltage)

Schmitt Trigger : Positive Input Sweep (3)


2' '

,62 20,

5 6 ,6

1 12 2(0.62 0.48)

2 211

0.4

C n DD z Tn nin T n z z z z

zDD z T C nz

C n

E L V V Vk kW WV V V V V V

VL L V V V E LVE L

2

0.4 1.2 0.48 0.524( 1.011 1.011)1

10 1.2 [0.48 0.524( 1.011 1.011)] 0.4

z z

z z

V V

V V

,4 , 40.62 0.1 0.52 0.51GS T nV V V

0.1zV V

Schmitt Trigger : Negative Input Sweep (1)1) Vin = 1.2V

M4, M5 : on VX=0V M1, M2 : off M3 : on (Saturation)


2'

,3

3 ,3

00

2 0

C p y Tp

y T C p

E L V Vk W

L V V E L

,3 0, 0.406 0.972 0.972y T T p DD yV V V V V

0.573yV V

2) Vin = 0.74V M1 : on M2 : off M3 : on (Saturation) Vout : unchanged

Schmitt Trigger : Negative Input Sweep (2)3) Vin=0.6V

M1, M3 : on (Saturation)

M2 : off (at this point)


2 2 2' '0, ,3

1 30, ,3

0 1.8 0.6 1.2 ( 0.46)

2 2 0.6 1.2 ( 0.46) 1.80

C p in DD T p C p y Tp p

in DD T p C p y T C p

E L V V V E L V Vk kW W

L LV V V E L V V E L

0.92yV V ,2 0,0.6 0.92 0.32 0.46GS T pV V

22 1.8 0 0.46 0.406 0.972 1.2 0.9721.8 0.6 1.2 ( 0.46) 1

0.6 1.2 ( 0.46) 1.8 10 0 0.46 0.406( 0.972 1.2 0.972) 1.8

y y

y y

V V

V V

Schmitt Trigger : Negative Input Sweep (3)4) Vin=0.52V

M2 : off (Assumption) M1 : on (Linear), M3 : on (Saturation)

M2 is already on Vth- : 0.52V (Lower logic threshold voltage)


2' '

2 ,3

0,1 3 ,3

012

2 2 01

C p y Tp pin DD T p y DD y DD

y T C py

C p

E L V Vk kW WV V V V V V V

L L V V E LV

E L

2

1.8 0 0.46 0.406 0.972 1.2 0.9721 1[2 (0.52 1.2 ( 0.46)) ( 1.2) 1.2 ]

10 0 0.46 0.406 0.972 1.2 0.972 1.811.8

y y

y yy

y y

V VV V

V V V

0.98Vy V

Schmitt Trigger : Simulation


ch08 sequential logic...wk (glwlrq &odvvlilfdwlrq ri orjlf flufxlwv %dvhg rq ehkdylru ... 7 $ hq...

Documents