Chapter 6

Frequency Response of Amplifiers

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[Review] MOS Device

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[Cutoff]

CGS=CGD=Wcov

CGB=C1|| C2

[Saturation] D : not much of channel near Drain

CGS=WLCox*2/3+WCov, CGD=WCov

CGB : negligible (S-D current path � shield)

[Triode] C1 is divided equally

CGS= CGD=WLCox/2+WCov

CGB : negligible

[Review] MOS Device

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[Accumulation mode]

CGS ~ WLCox = C1

[Weak Inversion]

CGB ~ C1|| C2

Q. What is the accumulation-mode varactor?

* D/S/B : tied to ground

Miller’s Theorem

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Y

X

YXY

X

Y

XYX

V

V

Z

Z

V

Z

VV

V

V

Z

Z

V

Z

VV

−

=→=−

−

=→=−

1

Z

1

Z

2

2

1

1

( ) ( ) ( )

( ) FFoutF

FinF

CA

CCA

sCZ

ACCAsCZ

~1

1 1

1//1

1 1//1

2

1

+=→

+=

+=→+=If X or Y is grounded,

Z1=0 & Z2=1/sCF

or Z1=1/sCF & Z2=0

(no Miller effect!)

Miller’s Theorem

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( ) ( )

)1(1)(

)(

)()(/)()(

)(/)(

ACsR

A

sV

sV

sVsVsCRsVsV

AsVsV

FSin

out

outXFSXin

Xout

++

−=

−=−

−=

Common-Source Stage

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Dominant pole � 3dB bandwidth

Miller multiplication of CGD � much lower bandwidth!

Common-Source Stage : two poles, one zero

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“Zero” is not predicted

by the simple approach.

Common-Source Stage : RHP zero

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A ‘zero’ indicates a frequency at which output

becomes zero. The two paths from input to

output may create signals that perfectly cancel

one another at one specific frequency.

Normally much

* RHP zero effects on stability � Chapter 10.

Source Followers

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Dominant pole

Source Followers : Input Impedance

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( )( )mbmGS

GSGS

ggCCAC

/1/ )gg/(g1)1(

)gg/(gA

mbmm

mbmm

+=+−=−

+=

“same as Miller”

Source Followers : Output Impedance

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KCL :

KVL :Typically, RS > 1/gm

(buffer)

“Inductive”

( )mS

m

GS

mS

m

/gRg

CL

/gRR/gR

1

11

1

2

−=

−==

If RS is large,

“ringing” to drive largre CL.

(Like RLC circuits)

Common-Gate Stage

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1. In a CG stage, input & output nodes are “isolated”.

No Miller multiplication of capacitances � potentially wide band(high speed).

2. Zin is dependent on ZL.

(Low input impedance affect the loading of the previous stage.)

Cascode Stage

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Casecode = CS + CG : high gain, high output impedance (Ch.3~5)

1. CS gain = -gm1/(gm2+gmb2) ~1 : suppress the Miller effect.

+ CG : high speed. � higher bandwidth!

2. Input stage = CG � high input impedance

� “high-gain high-frequency amplifier with high input impedance”

Every pole is much higher than CS pole.

Differential Pair

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Diff. mode

(half circuit)

Common

mode

Same as “CS”

(Miller multiplication of CGD)

M1&M2 mismatch

D

SSmm

mm

CMin

outDMCM R

Rgg

gg

V

VA

1)( 21

21

, ++

−−==−

Smaller CL, higher CP � worse CMRR (bigger CM gain)

Differential Pair : with Active Current Mirror

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Thevenin

Equivalence

Rx= 2ro

Vx=gmroVin

LHP zero at 2wp2

“mirror pole”

Differential Pair : Current-Source Loads

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CGD3&CGD4 effects

are equal & opposite

(canceled)

� G node : AC ground

Same as “CS”

(No mirror pole!)

Differential Pair : Symmetric

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Half circuit

( )

Dmv

inmDout

KRgA

VgKRV

1

111

=

⋅=

2-stage diff. amplifier

Only two CS stages

No mirror pole!

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MOS Cutoff Frequency (fT)

Frequency where iDS = iGS

Gain Bandwidth (GBW)

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Miller effect

Gain Bandwidth (GBW) : Cascode

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Gain = -gm1Rout, � different Rout

Gain Bandwidth (GBW)

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Gain Bandwidth (GBW)

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Single-pole system

Two-pole system

higher Ac

� more stable!

Current Mirror

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Homework #2 (Due : 03/27, Tue)

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(Hint) For amplifier design, choose L ~ 4Lmin, VGS-VT=0.2V

At single-stage amplifiers,