d5.3: report on the conclusions and outcomes of working ... · strain material option ! ... calibre...

INFORMATION AND COMMUNICATION TECHNOLOGIES

COORDINATION AND SUPPORT ACTION

EUROSOI+

European Platform for Low-Power Applications on Silicon-On-Insulator Technology

Grant Agreement nº 216373

D5.3: Report on the conclusions and outcomes of working group meeting dedicated to FDSOI

platform along the third EUROSOI+ workshop held at Grenoble.

Due date of deliverable: 28-02-2010 Actual submission date: 28-02-2010

Start date of project: 01-01-2008 Duration: 39 months

Project coordinator: Prof. Francisco Gámiz, UGR Project coordinator organisation: University of Granada, Spain Rev.1

Project co-funded by the European Commission within the Seventh Framework Programme (FP7) Dissemination Level

PU Public X PP Restricted to other programme participants (including the Commission Services) RE Restricted to a group specified by the consortium (including the Commission Services) CO Confidential, only for members of the consortium (including the Commission Services)

© CEA 2008. Tous droits réservés. Toute reproduction totale ou partielle sur quelque support que ce soit ou utilisation du contenu de ce document est interdite sans l’autorisation écrite préalable du CEA All rights reserved. Any reproduction in whole or in part on any medium or use of the information contained herein is prohibited without the prior written consent of CEA

1

2007

Process Design Kit FDSOI - PDK Team

FDSOI platform status

Olivier Faynot, January 24th 2010

2010


2

2007


EUROSOI+ Work plan

WP5. European platform for design LP SOI. 2008 2009 2010 2011

Task 5.1: Coordination of information exchange on LETI FDSOI technology

Task 5.2: Coordination of activities for the documentation, promotion and spreading of Research-dedicated Design Kit (RDK).

Task 5.3: Promotion of FDSOI technology

Task 5.4: Coordination of activities for the evaluation of the possible


3

2007


OUTLINE

! FDSOI technology status

! Circuit design platform

! Summary


4

2007


FDSOI technology

!  CMOS route (25nm gate lengths, 65nm BE design rules) !  No channel doping, No Pocket implant !  Selective Epitaxy process + implants !  Strain material option !  Ultra-thin BOX material option (for Bulk co-integration, and multi VT)

300mm


5

2007


VT variability vs spec.

!  World record VT mismatch !! !  It seems that undoped SOI is mandatory for 20nm

LP spec.

20nm LP specs

ETSOI, IBM

LETI/ST iedm’08

300mm, 2009

FDSOI

Bulk


6

2007


Performance

!  Reproducible results !  No strain incorporated ! UTBOX and strain options

w/o strain boosters CMOS route

PMOS NMOS


7

2007


OUTLINE

! FDSOI technology status

! Circuit design platform ! Summary


8

2007


PDK structure overview

!  PDK architecture: <Install_Path> |-----bin/ (Binary directory) |-----cad/ (PDK infrastructure directory) |-----cdsuser/ (User setup directory) |-----doc/ (Document directory) `-----tech/ (Technology specific directory)

!  PDK distribution: "  Installation procedure, "  Release notes, "  PDK LETI Reference Manual

# FTP CEA web site: ftp://ftp.cea.fr

Scripts, Instructions, User setup

UCL on going


9

2007


PDK technology package !  Technological library (Design & Layout)

"  Devices MOS (Symbol, CDF) "  Pcells MOS "  Scribe 22 pads, contacts

!  Electrical simulations (Eldo) "  Model cards, "  Device subcircuits, "  Corners setup

!  Physical verification and Layout finishing (Calibre) "  DRC verification file (Design Rules Checking), "  LVS verification file (Layout Versus Schematic), "  Dummies and Mask generation file

!  Parasitic extraction RC (Post-Layout, Star-RCXT) "  Process description file (itf # nxtgrd), "  Mapping files (devices, layers), "  Command file


10

2007


Prerequies CAD softwares ( for SNOW) !  Design (Schematic & Layout)

"  Cadence : 6.1.3.500.2

!  Electrical simulation "  Adms : 2009.2 (eldo)

!  Physical verification & Parasitic extraction "  Calibre : 2009.2_27.17 "  Star-rcxt : 2009.06

!  Platform system "  Solaris 2.8, Linux RHEL4.0 & 5.0

Eldo Model cards

Design Framework (Device, Pcell,…)

Calibre (DRC, LVS)

Star-RCXT (Post-Layout)


11

2007


Full custom Design flow - Methodology

Schematic Layout

Parasitic extraction

Layout finishing

Design entry

GDS

D R C

L V S

V E R I F

S I MU

Calibre DRC-LVS

files, runsets

Star-RCXT Map files

Calibre Dummies Gen file

Pcells MOS Pads

Tech Lib Devices

Eldo model cards

Layer map table

Cadence Design Framework

DRM : Design Rules Manual DRC : Design Rules Check LVS : Layout Versus Schematic

Mask Shop

Post-Layout


12

2007


Status (January 2010)

!  300mm technology available !  Wafers available for delivery. Already delivered to:

"  UCL (UTBOX wafers to be delivered soon) "  IMEP "  University of Granada "  Rovira University, Taragona

!  Design kit available: next release End of Q1, compatible with UTBOX

!  Circuit design opportunity for new LETI testchip (NDA required) $  SNOW testchip, coming end of Q2 ‘10

!  Introduction in EUROPRACTICE: to be adressed during 2010

!  For any information: [email protected]

d5.3: report on the conclusions and outcomes of working ... · strain material option ! ... calibre...

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