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1 ECE 667 Synthesis & Verification - Boo lean Functions ECE 667 ECE 667 Spring 2013 Spring 2013 Synthesis and Verification of Digital Circuits Boolean Functions and their Representations Slides adopted (with permission) from A. Kuehlmann, UC Berkeley 2003

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Page 1: ECE 667 Synthesis & Verification - Boolean Functions 1 ECE 667 Spring 2013 ECE 667 Spring 2013 Synthesis and Verification of Digital Circuits Boolean Functions

1

ECE 667 Synthesis & Verification - Boolean Functions

ECE 667ECE 667Spring 2013Spring 2013

Synthesis and Verificationof Digital Circuits

Boolean Functions

and their Representations

Slides adopted (with permission) from A. Kuehlmann, UC Berkeley 2003

Page 2: ECE 667 Synthesis & Verification - Boolean Functions 1 ECE 667 Spring 2013 ECE 667 Spring 2013 Synthesis and Verification of Digital Circuits Boolean Functions

ECE 667 Synthesis & Verification - Boolean Functions 2

The Boolean Space The Boolean Space BBnn

B = { 0,1}, B2 = {0,1} X {0,1} = {00, 01, 10, 11}

BB00

BB11

BB22

Karnaugh Maps: Boolean Cubes:

BB33

BB44

Page 3: ECE 667 Synthesis & Verification - Boolean Functions 1 ECE 667 Spring 2013 ECE 667 Spring 2013 Synthesis and Verification of Digital Circuits Boolean Functions

ECE 667 Synthesis & Verification - Boolean Functions 3

Boolean FunctionsBoolean Functions

1 2

1 2

1 1 2 2

1 2 1 2

Boolean Function: ( ) :

{0,1}

( , ,..., ) ;

- , ,... are

- , , , ,... are

- essentially: maps each vertex of to 0 or 1

Exampl

vari

e:

{(( 0, 0),0),(( 0,

ables

literals

1

n

nn i

n

f x B B

B

x x x x B x B

x x

x x x x

f B

f x x x x

1 2 1 2

),1),

(( 1, 0), 1),(( 1, 1),0)}x x x x

1x

2x

001

1

x2

x1

Page 4: ECE 667 Synthesis & Verification - Boolean Functions 1 ECE 667 Spring 2013 ECE 667 Spring 2013 Synthesis and Verification of Digital Circuits Boolean Functions

ECE 667 Synthesis & Verification - Boolean Functions 4

Boolean FunctionsBoolean Functions

1 1

1 0

1

0 1

- The of is { | ( ) 1} (1)

- The of is { | ( ) 0} (0)

- if , is the i.e. 1

- if ( ), is

Onset

Offset

tautology.

not satisfyabl , i.e. 0

- if ( ) ( ) , t

e

hen a

n

n

n

f x f x f f

f x f x f f

f B f f

f B f f f

f x g x for all x B f1

nd

- we say

are equiva

instea

le

nt

d of

g

f f

- literals: A is a variable or its negation , and represents a logic l functioniteral x x

Literal x1 represents the logic function f, where f = {x| x1 = 1}

Literal x1 represents the logic function g where g = {x| x1 = 0}

x1

x3

x2

f = x1

x1

x2

x3

f = x1

Notation: x’ = x

Page 5: ECE 667 Synthesis & Verification - Boolean Functions 1 ECE 667 Spring 2013 ECE 667 Spring 2013 Synthesis and Verification of Digital Circuits Boolean Functions

ECE 667 Synthesis & Verification - Boolean Functions 5

Set of Boolean FunctionsSet of Boolean Functions

• There are 2n vertices in input space Bn

• There are 22n distinct logic functions.

– Each subset of vertices is a distinct logic function: f Bn

x1x2x3

0 0 0 10 0 1 00 1 0 10 1 1 01 0 0 11 0 1 01 1 0 11 1 1 0

x1

x2

x3

• Truth Table or Function Table:

Page 6: ECE 667 Synthesis & Verification - Boolean Functions 1 ECE 667 Spring 2013 ECE 667 Spring 2013 Synthesis and Verification of Digital Circuits Boolean Functions

ECE 667 Synthesis & Verification - Boolean Functions 6

Boolean OperationsBoolean Operations - - AND, OR, COMPLEMENTAND, OR, COMPLEMENT

Given two Boolean functions:

f : Bn B

g : Bn B

• AND operation

f g = {x | f(x)=1 g(x)=1}

• The OR operation

f g = {x | f(x)=1 g(x)=1}

• The COMPLEMENT operation (^f or f’ )

f’ = {x | f(x) = 0}

Page 7: ECE 667 Synthesis & Verification - Boolean Functions 1 ECE 667 Spring 2013 ECE 667 Spring 2013 Synthesis and Verification of Digital Circuits Boolean Functions

ECE 667 Synthesis & Verification - Boolean Functions 7

Cofactor and QuantificationCofactor and Quantification

Given a Boolean function:

f : Bn B, with the input variables (x1,x2,…,xi,…,xn)

• Positive Cofactor of function f w.r.t variable xi

fxi = {x | f(x1,x2,…,1,…,xn)=1}

• Negative Cofactor of f w.r.t variable xi

fxi’ = {x | f(x1,x2,…,0,…,xn)=1}

• Existential Quantification of function f w.r.t variable xi,

xi f = {x | f(x1,x2,…,0,…,xn)=1 f(x1,x2,…,1,…,xn)=1}

• Universal Quantification of function f w.r.t variable xi,

xi f = {x | f(x1,x2,…,0,…,xn)=1 f(x1,x2,…,1,…,xn)=1}

Page 8: ECE 667 Synthesis & Verification - Boolean Functions 1 ECE 667 Spring 2013 ECE 667 Spring 2013 Synthesis and Verification of Digital Circuits Boolean Functions

ECE 667 Synthesis & Verification - Boolean Functions 8

Representations of Boolean FunctionsRepresentations of Boolean Functions

• We need representations for Boolean Functions for two reasons:– to represent and manipulate the actual circuit we are “synthesizing”– as mechanism to do efficient Boolean reasoning

• Forms to represent Boolean Functions– Truth table– List of cubes: Sum of Products, Disjunctive Normal Form (DNF) – List of conjuncts: Product of Sums, Conjunctive Normal Form (CNF)– Boolean formula– Binary Decision Tree, Binary Decision Diagram– Circuit (network of Boolean primitives)

• Canonicity – which forms are canonical?

Page 9: ECE 667 Synthesis & Verification - Boolean Functions 1 ECE 667 Spring 2013 ECE 667 Spring 2013 Synthesis and Verification of Digital Circuits Boolean Functions

ECE 667 Synthesis & Verification - Boolean Functions 9

Truth TableTruth Table

• Truth table (Function Table):The truth table of a function f : Bn B is a tabulation of

its values at each of the 2n vertices of Bn. (all mintems)

Example: f = a’b’c’d + a’b’cd + a’bc’d +

ab’c’d + ab’cd + abc’d +

abcd’ + abcd(Notation for complement: a’ = a )

The truth table representation is

- intractable for large n

- canonical

Canonical means that if two functions are the

same, then the canonical representations of each

are isomorphic (identical).

abcd f0 0000 01 0001 12 0010 03 0011 14 0100 05 0101 16 0110 07 0111 08 1000 0 9 1001 110 1010 011 1011 112 1100 013 1101 114 1110 115 1111 1

Page 10: ECE 667 Synthesis & Verification - Boolean Functions 1 ECE 667 Spring 2013 ECE 667 Spring 2013 Synthesis and Verification of Digital Circuits Boolean Functions

ECE 667 Synthesis & Verification - Boolean Functions 10

Boolean FormulaBoolean Formula

• A Boolean formula is defined as an expression with the following syntax:

formula ::= ‘(‘ formula ‘)’

| <variable>

| formula “+” formula (OR operator)

| formula “” formula (AND operator)

| ^ formula (complement)

Example:

f = (x1x2) + (x3) + ^^(x4 (^x1))

typically the “” is omitted and the ‘(‘ and ‘^’ are simply reduced by priority, e.g.

f = x1x2 + x3 + x4^x1

Page 11: ECE 667 Synthesis & Verification - Boolean Functions 1 ECE 667 Spring 2013 ECE 667 Spring 2013 Synthesis and Verification of Digital Circuits Boolean Functions

ECE 667 Synthesis & Verification - Boolean Functions 11

CubesCubes

• A cube is defined as the product (AND) of a set of literal functions (“conjunction” of literals).Example:

C = x1x’2x3

represents the following function

f = (x1=1)(x2=0)(x3=1)

x1

x2

x3

c = x1

x1

x2

x3

f = x1x2

x1

x2

x3

f = x1x2x3

Page 12: ECE 667 Synthesis & Verification - Boolean Functions 1 ECE 667 Spring 2013 ECE 667 Spring 2013 Synthesis and Verification of Digital Circuits Boolean Functions

ECE 667 Synthesis & Verification - Boolean Functions 12

CubesCubes

• If C f, C a cube, then C is an implicant of f.

• If C Bn, and C has k literals, then |C| covers 2n-k vertices.

Example:C = xy B3

k = 2 , n = 3 => |C| = 2 = 23-2.

C = {100, 101}

• In an n-dimensional Boolean space Bn, an implicant with n literals is a minterm.

Page 13: ECE 667 Synthesis & Verification - Boolean Functions 1 ECE 667 Spring 2013 ECE 667 Spring 2013 Synthesis and Verification of Digital Circuits Boolean Functions

ECE 667 Synthesis & Verification - Boolean Functions 13

List of Cubes - CoverList of Cubes - Cover

Sum of Products (SOP)Sum of Products (SOP)

• A function can be represented by a sum of cubes (products):

f = ab + ac + bcSince each cube is a product of literals, this is a “sum of products” (SOP) representation

• A SOP can be thought of as a set of cubes F

F = {ab, ac, bc}

• A set of cubes that represents f is called a cover of f.

Sets: F1={ab, ac, bc} and F2={abc, a’bc, ab’c, abc’}are some of possible covers of Boolean function

f = ab + ac + bc.

Page 14: ECE 667 Synthesis & Verification - Boolean Functions 1 ECE 667 Spring 2013 ECE 667 Spring 2013 Synthesis and Verification of Digital Circuits Boolean Functions

ECE 667 Synthesis & Verification - Boolean Functions 14

Binary Decision Diagram (BDD)Binary Decision Diagram (BDD)

f = ab+a’c+a’bd

1

0

c

a

b b

c c

d

0 1

c+bd b

root node

c+d

d

Graph representation of a Boolean function - vertices represent decision nodes for variables

- two children represent the two subfunctions

f(x = 0) and f(x = 1) (cofactors)

- restrictions on ordering and reduction rules

can make a BDD representation canonical

- function is evaluated as sum of paths from

root to constant node 1

- paths form disjoint cubes.

Page 15: ECE 667 Synthesis & Verification - Boolean Functions 1 ECE 667 Spring 2013 ECE 667 Spring 2013 Synthesis and Verification of Digital Circuits Boolean Functions

ECE 667 Synthesis & Verification - Boolean Functions 15

Boolean NetworksBoolean Networks

• Used for two main purposes

– as representation for Boolean reasoning engine

– as target structure for logic implementation which gets restructured in a series of logic synthesis steps until result is acceptable

• Efficient representation for most Boolean problems

– memory complexity is same as the size of circuits we are actually building

• Close to input representation and output representation in logic synthesis

Page 16: ECE 667 Synthesis & Verification - Boolean Functions 1 ECE 667 Spring 2013 ECE 667 Spring 2013 Synthesis and Verification of Digital Circuits Boolean Functions

ECE 667 Synthesis & Verification - Boolean Functions 16

Definitions Definitions –– Boolean NetworkBoolean Network

Definition:

A Boolean network is a directed graph C(G,N) where G are the gates and N GG is the set of directed edges (nets) connecting the gates.

Some of the vertices are designated:

Inputs: I G

Outputs: O G, I O =

Each node g is assigned a Boolean function fg which computes the output of the gate in terms of its inputs.

Page 17: ECE 667 Synthesis & Verification - Boolean Functions 1 ECE 667 Spring 2013 ECE 667 Spring 2013 Synthesis and Verification of Digital Circuits Boolean Functions

ECE 667 Synthesis & Verification - Boolean Functions 17

Definitions Definitions –– fanin, fanout, supportfanin, fanout, support

• The (immediate) fanin FI(g) of a gate g are all predecessor vertices of g:

FI(g) = {g’ | (g’,g) N}• The transitive fanin FIT (g) is defined as follows:

if a FI(b) and b FI(c) then a FIT (c)

• The fanout FO(g) of a gate g are all successor vertices of g:

FO(g) = {g’ | (g,g’) N} The transitive fanout is defined similarly

The cone CONE(g) of a gate g is the transitive fanin of g and g itself.

The support SUPPORT(g) of a gate g are all inputs in its cone:

SUPPORT(g) = CONE(g) I

Page 18: ECE 667 Synthesis & Verification - Boolean Functions 1 ECE 667 Spring 2013 ECE 667 Spring 2013 Synthesis and Verification of Digital Circuits Boolean Functions

ECE 667 Synthesis & Verification - Boolean Functions 18

Example Example –– Boolean NetworkBoolean Network

I

O

FI(6) = {2,4}

FO(6) = {7,9}

CONE(6) = {1,2,4,6}

SUPPORT(6) = {1,2}

6

1

5

3

4

78

9

2

Nodes = logic functions of arbitrary complexity

Page 19: ECE 667 Synthesis & Verification - Boolean Functions 1 ECE 667 Spring 2013 ECE 667 Spring 2013 Synthesis and Verification of Digital Circuits Boolean Functions

ECE 667 Synthesis & Verification - Boolean Functions 19

Boolean Network RepresentationsBoolean Network Representations

• Vertices can have arbitrary number of inputs and outputs– typically single-output functions are used

• Vertices can represent any Boolean function stored in different

ways, such as:– other circuits (hierarchical representation)– truth tables or cube representation – Boolean expressions read from a library description– BDDs, AIGs, etc.

• Data structure allow very general mechanisms for insertion and

deletion of vertices, pins (connections to vertices), and nets

Page 20: ECE 667 Synthesis & Verification - Boolean Functions 1 ECE 667 Spring 2013 ECE 667 Spring 2013 Synthesis and Verification of Digital Circuits Boolean Functions

ECE 667 Synthesis & Verification - Boolean Functions 20

AND-INVERTERAND-INVERTER Circuits Circuits

• Base data structure uses two-input AND function for vertices and INVERTER attributes at the edges (individual bit)– use De’Morgan’s law to convert OR operation etc.

• Hash table to identify and reuse structurally isomorphic circuits

f

g g

f

Means complement

Page 21: ECE 667 Synthesis & Verification - Boolean Functions 1 ECE 667 Spring 2013 ECE 667 Spring 2013 Synthesis and Verification of Digital Circuits Boolean Functions

ECE 667 Synthesis & Verification - Boolean Functions 21

Data RepresentationData Representation

• Vertex:– pointers (integer indices) to left and right child and fanout

vertices– collision chain pointer– other data

• Edge:– pointer or index into array– one bit to represent inversion

• Global hash table holds each vertex to identify isomorphic structures

• Garbage collection to regularly free un-referenced vertices

Page 22: ECE 667 Synthesis & Verification - Boolean Functions 1 ECE 667 Spring 2013 ECE 667 Spring 2013 Synthesis and Verification of Digital Circuits Boolean Functions

ECE 667 Synthesis & Verification - Boolean Functions 22

Data RepresentationData Representation

0456left

rightnext

fanout1345….

8456….

6423….

7463….

01

hash value

left pointer

right pointer

next in collision chain

array of fanout pointers

complement bits

Constant

One Vertex

zero

one

04560455

0457

...

...

Hash Table

0456left

rightnext

fanout

00