ece 667 - synthesis & verification - lecture 3 1 ece 697b (667) spring 2006 ece 697b (667)...

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1 ECE 667 - Synthesis & Verification - L ecture 3 ECE 697B (667) ECE 697B (667) Spring 2006 Spring 2006 Synthesis and Verification of Digital Circuits Scheduling Algorithms Scheduling Algorithms Analytical approach - ILP Analytical approach - ILP

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Page 1: ECE 667 - Synthesis & Verification - Lecture 3 1 ECE 697B (667) Spring 2006 ECE 697B (667) Spring 2006 Synthesis and Verification of Digital Circuits Scheduling

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ECE 667 - Synthesis & Verification - Lecture 3

ECE 697B (667)ECE 697B (667)Spring 2006Spring 2006

Synthesis and Verificationof Digital Circuits

Scheduling AlgorithmsScheduling AlgorithmsAnalytical approach - ILPAnalytical approach - ILP

Page 2: ECE 667 - Synthesis & Verification - Lecture 3 1 ECE 697B (667) Spring 2006 ECE 697B (667) Spring 2006 Synthesis and Verification of Digital Circuits Scheduling

ECE 667 - Synthesis & Verification - Lecture 3 2

Scheduling – a Combinatorial Optimization ProblemScheduling – a Combinatorial Optimization Problem

• NP-complete ProblemNP-complete Problem• Optimal solutions for special cases and ILPOptimal solutions for special cases and ILP

– Integer linear program (ILP)Integer linear program (ILP)– Branch and boundBranch and bound

• HeuristicsHeuristics– iterative Improvements, constructiveiterative Improvements, constructive

• Various versions of the problemVarious versions of the problem• Unconstrained minimum latencyUnconstrained minimum latency• Resource-constrained minimum latencyResource-constrained minimum latency• Timing constrained minimum latencyTiming constrained minimum latency• Latency-constrained minimum resourcesLatency-constrained minimum resources

• If all resources are identical, problem is reduced to If all resources are identical, problem is reduced to multiprocessor scheduling (Hu’s algorithm)multiprocessor scheduling (Hu’s algorithm)

• Minimum latency multiprocessor problem is intractable under Minimum latency multiprocessor problem is intractable under resource constraintresource constraint

Page 3: ECE 667 - Synthesis & Verification - Lecture 3 1 ECE 697B (667) Spring 2006 ECE 697B (667) Spring 2006 Synthesis and Verification of Digital Circuits Scheduling

ECE 667 - Synthesis & Verification - Lecture 3 3

Integer Linear ProgrammingInteger Linear Programming

• Given:

integer-valued matrix Am x n

vectors: B = ( b1, b2, … , bm ) and C = ( c1, c2, … , cn )

• Minimize: CT X

subject to:

A X B

X = ( x1, x2, … , xn ) is an integer-valued

vector

Page 4: ECE 667 - Synthesis & Verification - Lecture 3 1 ECE 697B (667) Spring 2006 ECE 697B (667) Spring 2006 Synthesis and Verification of Digital Circuits Scheduling

ECE 667 - Synthesis & Verification - Lecture 3 4

Integer Linear Programming - SchedulingInteger Linear Programming - Scheduling

• Problem (simple version)

Assumption: identical computations, each computation takes one cycle

For a set of (dependent) computations {v1,v2,...,vn}, find the minimum number of units needed to complete the execution in k control steps (MR-LCS problem)

• Integer Linear Programming (ILP):– Let y0 be an integer variable (# units to be minimized)

– for each control step l =1, …, k, define variable xil as

xil = 1, if computation vi is executed in the l-th control step

xil= 0, otherwise

– define variable yl (number of units in control step l )

yl = x1l + x2l + ... + xnl = i xil

Page 5: ECE 667 - Synthesis & Verification - Lecture 3 1 ECE 697B (667) Spring 2006 ECE 697B (667) Spring 2006 Synthesis and Verification of Digital Circuits Scheduling

ECE 667 - Synthesis & Verification - Lecture 3 5

ILP SchedulingILP Scheduling

• For each precedence relation:

– If vj has to be executed after vi - introduce dependency constraint:

xj1 + 2 xj2+ ... + k xjk xi1 + 2 xi2 + ... + k xik+ d(i)

( for unit delay, d(i) = 1)

Minimize: y0

Subject to: xj1+ xj2+ ...+ xjk = 1 for all j = 1,…, n (computations)

yl y0 for all l= 1,…, k (steps)

• 1st constraint: each computation vi can start only once:

xil= 1 for only one value of l (control step)

• Meaning of y0 : upper bound on the number of units, to be minimized

Page 6: ECE 667 - Synthesis & Verification - Lecture 3 1 ECE 697B (667) Spring 2006 ECE 697B (667) Spring 2006 Synthesis and Verification of Digital Circuits Scheduling

ECE 667 - Synthesis & Verification - Lecture 3 6

Example 1 - FormulationExample 1 - Formulation

n = 6 computationsk = 3 control steps

v1 v2 v3

v4

v6

v5

• Dependency constraints: e.g. v4 executes after v1

x41 + 2x42+ 3x43 x11 + 2x12 + 3x13 +1

. . . . . . . etc.

• Resource constraints:

yl = x1l + x2l + x3l+ x4l + x5l + x6l for l = 1,…, 3 (steps)

• Execution constraints:

xi1 + xi2 + xi3 = 1 for i = 1,…, 6

Page 7: ECE 667 - Synthesis & Verification - Lecture 3 1 ECE 697B (667) Spring 2006 ECE 697B (667) Spring 2006 Synthesis and Verification of Digital Circuits Scheduling

ECE 667 - Synthesis & Verification - Lecture 3 7

Example 1 - SolutionExample 1 - Solution

• Minimize: y0 • Subject to:

yl y0 for all l = 1,…, 3

Dependency constraints …

Execution constraints …

• One solution:

y0 = 2

x11 = 1, x21 = 1,

x32 = 1, x42 = 1,

x53 = 1, x63 = 1.

all other xil = 0

v1 v2

v3v4

v6 v5

Page 8: ECE 667 - Synthesis & Verification - Lecture 3 1 ECE 697B (667) Spring 2006 ECE 697B (667) Spring 2006 Synthesis and Verification of Digital Circuits Scheduling

ECE 667 - Synthesis & Verification - Lecture 3 8

ILP Model of SchedulingILP Model of Scheduling

• Binary decision variables xil

xil = 1 if operation vi starts in step l

i = 0, 1, …, n (operations)

l= 1, 2, … +1 (steps, with limit )

• Start time is unique:

l xil = xill=ti S

l=ti L

where:

t iS = time of operation I computed with ASAP

t iL = time of operation I computed with ALAP

Note:

Start time for vi:

Page 9: ECE 667 - Synthesis & Verification - Lecture 3 1 ECE 697B (667) Spring 2006 ECE 697B (667) Spring 2006 Synthesis and Verification of Digital Circuits Scheduling

ECE 667 - Synthesis & Verification - Lecture 3 9

ILP Model of Scheduling (contd.)ILP Model of Scheduling (contd.)

• Precedence relationships must be satisfied

• Resource bounds must be met– let upper bound on number of resources of type k be ak

Page 10: ECE 667 - Synthesis & Verification - Lecture 3 1 ECE 697B (667) Spring 2006 ECE 697B (667) Spring 2006 Synthesis and Verification of Digital Circuits Scheduling

ECE 667 - Synthesis & Verification - Lecture 3 10

Minimum-latency Scheduling under Minimum-latency Scheduling under Resource-constraintsResource-constraints

• Let t be the vector whose entries are start times• Formal ILP model

Page 11: ECE 667 - Synthesis & Verification - Lecture 3 1 ECE 697B (667) Spring 2006 ECE 697B (667) Spring 2006 Synthesis and Verification of Digital Circuits Scheduling

ECE 667 - Synthesis & Verification - Lecture 3 11

Example 2 – Example 2 – Multiple ResourcesMultiple Resources

• Two types of resources– Multiplier– ALU

• Adder• Subtraction• Comparison

• Both take 1 cycle of execution time

Page 12: ECE 667 - Synthesis & Verification - Lecture 3 1 ECE 697B (667) Spring 2006 ECE 697B (667) Spring 2006 Synthesis and Verification of Digital Circuits Scheduling

ECE 667 - Synthesis & Verification - Lecture 3 12

Example 2 (contd.)Example 2 (contd.)

• Heuristic (list scheduling) gives latency = 4 stepsHeuristic (list scheduling) gives latency = 4 steps• Use ALAP and ASAP (with no resource constraints) Use ALAP and ASAP (with no resource constraints)

to get bounds on start timesto get bounds on start times– ASAP matches latency of heuristicASAP matches latency of heuristic

• (so heuristic is optimum)(so heuristic is optimum)

• Constraints?Constraints?

Page 13: ECE 667 - Synthesis & Verification - Lecture 3 1 ECE 697B (667) Spring 2006 ECE 697B (667) Spring 2006 Synthesis and Verification of Digital Circuits Scheduling

ECE 667 - Synthesis & Verification - Lecture 3 13

Example 2 (contd.)Example 2 (contd.)

• Start time must be unique

l xil = xill=ti S

l=ti L

where:

t iS = time of operation i computed with ASAP

t iL = time of operation i computed with ALAP

Recall:

Page 14: ECE 667 - Synthesis & Verification - Lecture 3 1 ECE 697B (667) Spring 2006 ECE 697B (667) Spring 2006 Synthesis and Verification of Digital Circuits Scheduling

ECE 667 - Synthesis & Verification - Lecture 3 14

Example 2 (contd.)Example 2 (contd.)

• Precedence constraints– Note: only non-trivial ones listed

(those with more than one possible start time for at least one operation)

Page 15: ECE 667 - Synthesis & Verification - Lecture 3 1 ECE 697B (667) Spring 2006 ECE 697B (667) Spring 2006 Synthesis and Verification of Digital Circuits Scheduling

ECE 667 - Synthesis & Verification - Lecture 3 15

Example 2 (contd.)Example 2 (contd.)

• Resource constraints

MULT

a1=2

ALU

a2=2

Page 16: ECE 667 - Synthesis & Verification - Lecture 3 1 ECE 697B (667) Spring 2006 ECE 697B (667) Spring 2006 Synthesis and Verification of Digital Circuits Scheduling

ECE 667 - Synthesis & Verification - Lecture 3 16

Example 2 (contd.)Example 2 (contd.)

• Consider c = [0, 0, …, 1]T

– Minimum latency schedule

– since sink has no mobility (xn,5 = 1), any feasible schedule is optimum

• Consider c = [1, 1, …, 1] T

– finds earliest start times for all operations i l – or equivalently:

Page 17: ECE 667 - Synthesis & Verification - Lecture 3 1 ECE 697B (667) Spring 2006 ECE 697B (667) Spring 2006 Synthesis and Verification of Digital Circuits Scheduling

ECE 667 - Synthesis & Verification - Lecture 3 17

Example Solution 2: Example Solution 2: Optimum Schedule Under Resource ConstraintOptimum Schedule Under Resource Constraint

Page 18: ECE 667 - Synthesis & Verification - Lecture 3 1 ECE 697B (667) Spring 2006 ECE 697B (667) Spring 2006 Synthesis and Verification of Digital Circuits Scheduling

ECE 667 - Synthesis & Verification - Lecture 3 18

Example 3Example 3

• Assume multiplier costs 5 units of area, and ALU costs 1 unit of area

• Same uniqueness and sequencing constraints as before

• Resource constraints are in terms of unknown variables a1 and a2

• a1 = number of multipliers

• a2 = number of ALUs (add/sub)

Page 19: ECE 667 - Synthesis & Verification - Lecture 3 1 ECE 697B (667) Spring 2006 ECE 697B (667) Spring 2006 Synthesis and Verification of Digital Circuits Scheduling

ECE 667 - Synthesis & Verification - Lecture 3 19

Example 3 (contd.)Example 3 (contd.)

• Resource constraints

MULT

ALU

Page 20: ECE 667 - Synthesis & Verification - Lecture 3 1 ECE 697B (667) Spring 2006 ECE 697B (667) Spring 2006 Synthesis and Verification of Digital Circuits Scheduling

ECE 667 - Synthesis & Verification - Lecture 3 20

Example 3 - SolutionExample 3 - Solution

• MinimizecTa = 5.a1 + 1.a2

• Solution with cost = 12

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ECE 667 - Synthesis & Verification - Lecture 3 21

Precedence-constrained Precedence-constrained Multiprocessor SchedulingMultiprocessor Scheduling

• All operations performed by the same type of resourceAll operations performed by the same type of resource– intractable problem; even if operations have unit delayintractable problem; even if operations have unit delay