ece 667 - synthesis & verification - lecture 2 1 ece 667 spring 2011 ece 667 spring 2011...

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ECE 667 - Synthesis & Verification - Lecture 2

ECE 667ECE 667Spring 2011Spring 2011

Synthesis and Verificationof Digital Circuits

High-Level (Architectural)High-Level (Architectural)

SynthesisSynthesis

ECE 667 - Synthesis & Verification - Lecture 2 2

High Level Synthesis (HLS)High Level Synthesis (HLS)

• The process of converting a high-level description of a design to RTL– Input:

• High-level languages (C, system C, system Verilog)• Behavioral hardware description languages (Verilog, VHDL)• Structural HDLs (VHDL, Verilog)• State diagrams / logic networks

– Tools:• Parser• Library of modules

– Constraints:• Resource constraints (no. of modules of a certain type)• Timing constraints (Latency, delay, clock cycle)

– Output:• Operation scheduling (time) and binding (resource)• Control generation and RTL architecture


High Level SynthesisHigh Level Synthesis

DD

***

+ +

Signal Flow Database

MAPPING

GRAPHICS

ESTIMATIONS

TRANSFORMATIONSSCHEDULING

func fir (In) : Out =begin

endOut = In@1 * a;

DD

***

+ +

Adder

Mult

Time 1 2 3 4xx x

x xx

Min Bounds:2 adders1 multiplier16 registers

D

***

++reg

regmult

C

TEMPLATE MATCHING

DD

***

+ +

+


• A second-order digital filter /* A behavioral description of a digital filter

module digital_filter(x1,y1);

input x1;output y1;wire [7:0] r1,r2,r3,r4,t1,t2,c,a11,a21;

assign r1 = x1 + t2; assign r2 = r1 * a11 + t2; assign r4 = r2 + t1; assign r3 = r4 + a21 + t1;

assign y1 = c* (r1 + r2); assign t1 = r3; assign t2 = r3 + r4;

endmodule

Example – Digital Filter designExample – Digital Filter design

Algorithm:

Verilog code:


Example – Unscheduled DFGExample – Unscheduled DFG


Resource-constraint scheduling ( 1 adder , 1 multiplier)

Register mapping (left-edge algorithm)

Example – Scheduling and Regs mappingExample – Scheduling and Regs mapping


c1 c2 c3 c4

c5 c6 c7

n1 n2

n3 n4 n5

x1

const c

y1

Example – Final ArchitectureExample – Final Architecture

FSMcontroller


High-Level Synthesis Compilation FlowHigh-Level Synthesis Compilation Flow

Lex

Parse

Compilationfront-end

BehavioralOptimization

Intermediateform

Arch synthLogic synth

Lib BindingHLS backend

x = a + b c + d

+

+

a b c d

+

+

a d b c


Behavioral OptimizationBehavioral Optimization

• Techniques used in software compilation– Expression tree height reduction– Constant and variable propagation– Common sub-expression elimination– Dead-code elimination– Operator strength reduction (e.g., *4 << 2)

• Typical Hardware transformations– Conditional expansion

• If (c) then x=A else x=B compute A and B in parallel, x=(C)?A:B

– Loop unrolling• Instead of k iterations of a loop, replicate the

loop body k times

A

Bx

c


Optimization in Temporal DomainOptimization in Temporal Domain• Scheduling and binding can be done in different

orders or together• Schedule:

– Mapping of operations to time slots (cycles)– A scheduled sequencing graph is a labeled graph

[©Gupta]

+

NOP

+ <

-

-

NOP

1

2

3

4

+

NOP

+

<

-

-

NOP

1

2

3

4


Scheduling in Spatial DomainScheduling in Spatial Domain

• Resource sharing– More than one operation bound to same resource– Operations have to be serialized– Can be represented using hyperedges (define vertex partition)

[©Gupta]

+

NOP

+ <

-

-

NOP

1

2

3

4


Architectural OptimizationArchitectural Optimization

• Optimization in view of design space flexibility• A multi-criteria optimization problem:

– Determine schedule and binding .

– Under area , latency L and cycle time objectives

• Find non-dominated points in solution space• Solution space tradeoff curves:

– Non-linear, discontinuous

– Area / latency / cycle time (more?)

• Evaluate (estimate) cost functions• Unconstrained optimization problems for resource dominated

circuits:– Min area: solve for minimal binding

– Min latency: solve for minimum L scheduling

[©Gupta]


Typical High-Level Synthesis SystemTypical High-Level Synthesis System


Algorithm DescriptionAlgorithm Description


Control Data Flow Graph (CDFG)Control Data Flow Graph (CDFG)


Precedence GraphPrecedence Graph


Sequence Graph: Start and End NodesSequence Graph: Start and End Nodes


Hierarchy in Sequence GraphsHierarchy in Sequence Graphs


Hierarchy in Sequence Graphs (contd.)Hierarchy in Sequence Graphs (contd.)


ImplementationImplementation

Control/DataFlow Graph

(CDFG)Implementation

RegReg

Multiplier

Adder

RegReg2 1 1 ...2 3 2 ...

4 3 2 ...

0 4 7 ...

4 7 9 ...


Original specification

Un-scheduled DFG: one-to-one mapping from HDL spec.

RTL optimized for particular objective

Physical Implementation

HDL

DFG1 DFG2 DFGn

RTL1 RTL2

Circuit, SoC

Synthesis Flow – mapping & optimization stepsSynthesis Flow – mapping & optimization steps


x

+

a b c

F

Data Flow Graph (DFG)Data Flow Graph (DFG)

Precedence graph for computation F

F = a*b + a*cF = a*(b + c)Transformation

+

x

ab c

x

F


+

x

ab c

F=ab+ac

x

DFG Scheduling

X

+

a b c

F=a(b+c)

X

+

a b c

F

s0

s1

L=2, 1 Add, 1 Mult

+

x

ab c

F

xs0

s1

L=2, 1 Add, 2 Mult L=3, 1 Add, 1 Mult

+

x

ab c

F

x

s0

s1

s2


x

+

a b c

F

S0

S1+

x

ab c

F

x+

x

ab c

F

xs0

s1

s2

s0

s1

X

+

FF

b ca

F

CK

CTLlogic

+

X

FFCTLlogic

CK

a b c

F

FF

XX

FF

+

b a c

CTLlogic

CK

F

Scheduling affects RTL


(+):

(x):

(2x2)(4x1)

(3x5) (4x4)

(mux):

(2x1)(FF):

(4x1) (2x2)

Resources: Datapath Library

• Operators available from datapath library

- pre-synthesized, pre-characterized

- different layout, etc


mux

X

FF1

FF2

+

FF2

x

+

FF1

mux

Evaluate: area, wirelength, congestion, interconnect, …

+

X

FFCTLlogic

CK

a b c

F

FF

Floorplan Estimation

ece 667 - synthesis & verification - lecture 2 1 ece 667 spring 2011 ece 667 spring 2011...

Documents

high level synthesis

r3 assign t2

high level synthesis

r2 t1 assign r3

r1 r2 assign t1

x1 t2 assign r2

a21 assign r1

rtl architecture slide