ee141 © digital integrated circuits 2nd timing issues 1 digital integrated circuits a design...

EE141© Digital Integrated Circuits2nd Timing Issues1

Digital Integrated Digital Integrated CircuitsCircuitsA Design PerspectiveA Design Perspective

Timing IssuesTiming Issues

Jan M. RabaeyAnantha ChandrakasanBorivoje Nikolić

Revised from Digital Integrated Circuits, © Jan M. Rabaey el


Digital TimingDigital Timing All sequential circuits must have a well-defined ordering of the switching events to ensure the correct operation.

The very popular synchronous approach, in which all memory elements in the system are simultaneously updated using a globally distributed periodic synchronization signal, is an effective way to enforce correct ordering

But global synchronous clock might suffer from clock skew (spatial variation) and clock jitter (temporal variation)

Asynchronous design avoids the problem of clock uncertainty by eliminating the need for a globally distributed clock at expense of hardware and speed (not necessarily)


Synchronous TimingSynchronous Timing

CombinationalLogic

R1 R2Cin Cout Out

In

CLK


Timing Timing DefinitionsDefinitions


Latch ParametersLatch Parameters

D

Clk

Q

D

Q

Clk

tc-q

thold

PWmtsu

td-q

Delays can be different for rising and falling data transitions

T


Register ParametersRegister Parameters

D

Clk

Q

D

Q

Clk

tc-q

thold

T

tsu

Delays can be different for rising and falling data transitions


Clock UncertaintiesClock Uncertainties

2

4

3

Power Supply

Interconnect

5 Temperature

6 Capacitive Load

7 Coupling to Adjacent Lines

1 Clock Generation

Devices

Sources of clock uncertainty


Clock Non-idealitiesClock Non-idealities Clock skew

The spatial variation in arrival time of a clock transition on an integrated circuit is commonly referred to as clock skew

Clock skew is caused by static mismatches in the clock paths and differences in the clock load.

Clock skew is constant from cycle to cycle. Clock skew does not cause clock period

variation, but only phase shift deterministic + random, tSK


Clock NonidealitiesClock Nonidealities

Clock jitter Clock jitter refers to the temporal variation

of the clock period at a given spatial location on the chip: the clock period can reduce or expand from cycle to cycle

Jitter can be measured and characterized in a number of ways and is typically modeled as a zero-mean random variable


Clock Skew and JitterClock Skew and Jitter

Clk1

Clk2

tSK

tJS


Clock SkewClock Skew

# of registers

Clk delayInsertion delay

Max Clk skew

Earliest occurrenceof Clk edgeNominal – /2

Latest occurrenceof Clk edge

Nominal + /2

Clock skew might have strong effect for both the system performances and the functionality of sequential system


Positive and Negative SkewPositive and Negative Skew

R1In

(a) Positive skew

CombinationalLogicD Q

tCLK1CLK

delay

tCLK2

R2

D Q CombinationalLogic

tCLK3

R3• • •D Q

delay

R1In

(b) Negative skew

CombinationalLogicD Q

tCLK1

delay

tCLK2

R2

D Q CombinationalLogic

tCLK3

R3• • •D Q


Positive SkewPositive Skew

CLK1

CLK2

TCLK

TCLK

th

2

1

4

Minimum cycle time:T + >=tc-q + tsu + tlogic

This means that clock skew has the potential to improve the performance of the circuit (minimum required clock period reduces!). However, increasing clock skew makes the circuit more susceptible to race conditions.

To avoid race: th+ <tc-q,cd + tlogic,cd


Negative SkewNegative Skew

CLK1

CLK2

TCLK

TCLK +

2

1

4

3

Receiving edge arrives before the launching edge

On one hand, negative skew adversely impacts the performance (increase the clock period).

On the other hand, negative skew implies that the system never fails (since receiving edge happens before)


Summary for clock skew: Summary for clock skew: minimum clock periodminimum clock period

R1

D QCombinational

LogicIn

CLK tCLK1

R2

D Q

tCLK2

tc qtc q, cdtsu, thold

tlogict

Minimum cycle time:T + = tc-q + tsu + tlogic

Worst case is when receiving edge arrives early (negative )

Cd: contamination delay or minimum delay


R1

D QCombinational

LogicIn

CLK tCLK1

R2

D Q

tCLK2

tc qtc q, cdtsu, thold

tlogict

Hold time constraint:t(c-q, cd) + t(logic, cd) > thold +

Worst case is when receiving edge arrives lateRace between data and clock

Summary for clock skew: Summary for clock skew: hold time constrainthold time constraint


Impact of JitterImpact of Jitter

CLK

-tji tter

TC LK

t j itter

CLK

InCombinat ional

Logic

tc-q , tc-q, cdt log ict log ic, cdtsu, thold

REGS

tjitter

Clock period constraint:T-2tjitter>=tc-q + tlogic + tsetup


Impact of clock jitter: general caseImpact of clock jitter: general case

Clk

T

TSU

TClk-QTLM

Latest point of launching

Earliest arrivalof next cycle

TJI

Tc-q + TLM + TSU < T – TJI,1 – TJI,2


Combined impact of clock skew and Combined impact of clock skew and clock jitter: minimum clock periodclock jitter: minimum clock period

If launching edge is early and receiving edge is late, the data will not be too late if:

Tc-q + TLM + TSU < T – TJI,1 – TJI,2 + Tc-q + TLM + TSU - + 2 TJI < TSkew can be either positive and negative

But the equation shows that positive skew can provide a performance advantage

On the other hand, clock jitter always have a negative impact on the minimum clock period


Combined effect of clock Skew Combined effect of clock Skew and Jitterand Jitter

Clk

Clk

tSK

tJS


Earliest point of launching

Combined impact of clock skew and Combined impact of clock skew and clock jitter: minimum logic delayclock jitter: minimum logic delay

ClkTClk-Q TLm

Data must not arrivebefore this time

ClkTH

Nominalclock edge

jitter

jitterskew


Minimum logic delay:

If launching edge is early and receiving edge is late:

Tc-q + TLM – TJI,1 < T + TJI,2 +

Tc-q + TLM > TH + 2TJI+

Combined impact of clock skew and Combined impact of clock skew and clock jitter: minimum logic delayclock jitter: minimum logic delay

As before, negative skew increase the clock period, but made minimum logic delay constraint easier to met

On the other hand, clock jitter always have a negative impact on the minimum logic delay


How to counter Clock Skew?How to counter Clock Skew?

RE

G

RE

G

R

EG

.

RE

G

log Out

In

Clock Distribution

Positive Skew

Negative Skew

Data and Clock Routing


Clock Distribution TechniquesClock Distribution Techniques Clock skew and jitter affects the system performance, so it is important to design a clock network to minimize both.

When designing clock network, power consumption is a big issue. In today’s digital processors, a majority of the power is dissipated in the clock network.

To reduce power consumption, part of the clock network should conditionally shut down

Clock network design is a complicated task with many degrees of freedom, such as material used for wires, basic topology and hierarchy, sizing of wires and buffers, rise time and fall time, load capacitance etc.


Clock Distribution TechniquesClock Distribution Techniques

CLK

Clock is distributed in a tree-like fashion

Balance pathApproach:H-tree

The absolute delay from a central clock source to the clock elements is irrelevant, only the relative phase or delay between any two clock elements is important.


More realistic H-treeMore realistic H-tree The H-tree configuration is particularly useful for regular array networks in which all elements are identical and the clock can be distributed as a binary tree.

A more general approach, referred to as matched RC trees, represents a floorplan that distributes the clock signal so that the interconnections carrying the clock signals to the functional sub-blocks have equal time constants. (that is the general approach does not rely on a regular physical structure)


More realistic H-treeMore realistic H-tree

[Restle98]An RC-matched IBM microprocessor

10 balanced load segments

CLK


The Grid SystemThe Grid System

D r iv e r

D r iv e r

Dri

ver

Driv

er

G C L K G C L K

G C L K

G C L K

•No rc-matching•Rather, absolute delay is minimized•Allows for late design changes•Large power due to lengthy interconnect

Grids are typically used in the final stage of a clock network to distribute the clock to the clocking elements.

ee141 © digital integrated circuits 2nd timing issues 1 digital integrated circuits a design...

Documents

clock skew clock skew

digital timing

distributed clock

clock nonidealities

clock paths

clock transition

clock load

clock period variation