elg 2135 electronics i fifth chapter: field effect transistors

ELG 2135

ELECTRONICS I

FIFTH CHAPTER:

FIELD EFFECT TRANSISTORS

Session WINTER 2003

Dr. M. YAGOUB

Fifth Chapter: Field Effect Transistors V - 2_________________________________________________________________________________________________________________________________________________________

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In electronics, we have two major types of transistors, namely the Bipolar Junction Transistor and

the Field-Effect Transistor (FET) which has four terminals.

The field-effect transistor derives its name from the essence of its physical operation. Specifically, it

will be shown that the current-control mechanism is based on an electric field established by the

voltage applied to the control terminal.

It will also be shown that current is conducted by only one type of carrier (electrons or holes)

depending on the type of FET (n channel or p channel), which gives the FET another name, the

unipolar transistor.

Although the FET family of devices has many different types based on the used technology and/or

the substrate material (MOSFET, MESFET, SISFET, MISFET, MODFET or JFET devices, with single

or dual gates, using Si, AsGa, AsAlGa/AsGa, or InAsGa/InP substrates, …), it exists four major

different types of MOSFETs: enhancement-type or depletion-type device, and n-channel or p-

channel device. Since one of the most familiar FETs is the Metal-oxide semiconductor field effect

transistor or MOSFET, we will discuss mainly in this chapter on the n-channel enhancement-type

MOSFET.

Compared to BJTs, MOS transistors can be made quite small. Furthermore, digital logic and

memory functions can be implemented with circuits that use only MOSFETs (no resistors or diodes are

needed). For these reasons, most very-large-scale integrated circuits (VLSI technology) are made using

MOS technology. Examples include microprocessor and memory chips.

A – PHYSICAL OPERATION OF THE MOSFET

I – Structure of the enhancement-type MOSFET

The enhancement-type MOSFET is the most widely used field-effect transistor. Figure V-1 shows

the physical structure of the n-channel enhancement-type MOSFET.

The transistor is fabricated on a p-type substrate, which is a single-crystal silicon wafer that provides

physical support for the device (“The body”). Two heavily doped n-type regions, indicated as the n+

regions, are created in the substrate (“ The drain and the Source”).

A thin layer of silicon dioxide (SiO2) is grown on the surface of the substrate, creating an excellent

electrical insulation. Usual physical dimensions are 1 to 10 µm for the length L, 2 to 500 µm for the

width W and 0.02 to 0.1 µm for the thickness of the SiO2 layer.


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Metal is deposited on the top of the oxide layer to form the Gate electrode of the device. Thus, four

terminals are brought out:

→ Drain (D)

→ Gate (G)

→ Source (S)

→ Body (B)

Figure V-1


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Emphasizing the fact that the gate electrode is electrically insulated from the device body, another

name of the MOSFET is the IGFET or insulated-gate FET

Observe that the substrate (body) forms two PN junctions with the drain and source regions. In

normal operation these PN junctions are kept reverse-biased at all times. Since the drain will be at a

positive voltage relative to the source, the 2 junctions can be effectively cut off by simply connecting

the substrate terminal to the source terminal. We have thus a three-terminal device.

II – Gate voltage effect

With no bias voltage applied to the gate, two back-to-back diodes exist in series between drain and

source. These diodes prevent current conduction from drain to source when a voltage vDS is applied. In

fact, the path between drain and source has a very high resistance (of the order of 1012 Ω).

Consider now the situation where the source and the drain are grounded and where a positive gate

voltage is applied (Figure V-2). The positive voltage vGS on the gate causes the free holes to be repelled

from the region of the substrate under the gate (the channel region). These holes are pushed downward

into the substrate, leaving behind a carrier-depletion region.

As well, the positive gate voltage attracts electrons from the n+ source and drain regions into the

channel region. An n region is created, connecting the source and drain regions. The induced n region

thus forms a channel for current flow from drain to source.

Figure V-2


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Correspondingly, the MOSFET is called an n-channel MOSFET or alternatively an NMOS

transistor. The value of vGS at which a sufficient number of mobile electrons accumulate in the channel

region to form a conducting channel is called the threshold voltage and is denoted Vt (which is

different from the thermal voltage VT for diodes and bipolar junction transistors). The value of Vt is in

the range 1 to 3V.

Note 1: The voltage between gate and source controls the current flow between drain and source.

Note 2: The gate current is almost zero (≈ 10-15A)

Note 3: Although the transistor is an n-channel MOSFET, it is formed in a p-type substrate. The

channel is created by inverting the substrate surface from p type to n type. The induced

channel is also called an inversion layer.

III –vDS voltage

Having induced a channel, we now apply a positive voltage vDS. We have to consider two cases

depending on whether vDS is small or large.

1 – Small vDS

A small vDS (0.1 or 0.2V) causes a current iD to flow through the induced n channel (figure V-3).

Figure V-3


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This current depends on the density of electrons in the channel (i.e. vGS). Specifically, as vGS exceeds

Vt, more electrons are attracted into the channel. The result is a channel of reduced resistance. In fact,

the conductance of the channel is proportional to the excess gate voltage vGS – Vt also known as the

effective voltage. INCREASING the gate voltage ENHANCES THE CHANNEL.

Note: Since the gate current is negligible,

SD ii = (1)

and the drain or source current is denoted by iDS. For an enhancement-type NMOS

transistor, this current flows from drain to source.

2 – Large vDS

When vDS is increased, this voltage appears as a voltage drop across the length of the channel.

Starting from source, the voltage increases from 0 to vDS. Since the channel depth depends on this

voltage, the channel is no longer of uniform depth (figure V-4).

The channel resistance increases correspondingly and thus the iD-vDS curve does not continue as a

straight line but bends as shown in Figure V-5.

Figure V-4


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At the limit, when vDS is increased to the saturation value that reduces the voltage between gate and

channel at the drain end to Vt, i.e.

tGSDSDS Vvvv −== sat (2)

the channel depth at the drain end decreases to almost zero, and the channel is said to be pinched off.

The rain current thus saturates at this value, and the MOSFET is said to have entered the saturation

region of operation.

Note 1: Saturation in a MOSFET means a very different thing that it does in a BJT. In this region the

drain current is almost constant versus the drain-source voltage.

Note 2: The region obtained for vDS < VDT is called the triode region (referring to the triode vacuum

tube behavior).

IV – Summary

Taking into account the reference voltages shown on Figure V-6, we have:

vGS < Vt : The two junctions are reverse-biased. The iD current is very small

and follows an exponential law versus vGS :

→ Cut off mode (transistor is an open circuit)

Figure V-5


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vGS ≥ Vt and 0 < vDS << vGS - Vt : The current iD between drain and source is proportional to the

voltage vDS. The transistor is equivalent to a resistance:

→ Resistive Triode mode (used in mixers)

vGS ≥ Vt and 0 < vDS < vGS - Vt : The current iD is no more proportional to the voltage vDS. The

transistor is equivalent to a nonlinear resistance:

→ Nonlinear Triode Mode (used for nonlinear applications)

vGS ≥ Vt and vDS > vGS - Vt : The channel is pinched off at the drain end. This mode is

equivalent to the active mode for BJTs. The current iD is

practically independent of the voltage vDS. The transistor is

equivalent to a controlled source:

→ Saturation Mode (used for amplification)

Note 1 : The p-channel Enhancement-type MOSFET (or PMOS) device operates in the same manner as

the n-channel device except that:

P and N regions are inverted.

The threshold voltage is negative

The voltages vGS and vDS are negative.

The current iD enters the source terminal and leaves through the drain terminal.

Figure V-6

N+

N+

N

S

G

D

vDG

vGS

vDSP


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Note 2 : It is possible to combine p-channel (or PMOS) and n-channel Enhancement-type MOSFET (or

NMOS) to obtain a complementary MOSFET (or CMOS). Although their technology is more

complex, CMOS devices (Figure V-7) are widely used in VLSI circuits.

B –SYMBOLS AND CONVENTIONS

By convention, circuit symbols for Enhancement-type MOSFETs are shown in Figure V-8-a. Since

the Body (B) is usually connected to source, simplified circuit symbols for Enhancement-type

MOSFETs are shown in Figure V-8-b.

(a) (b)

II – Bias voltages

Figure IV-9 shows Enhancement-type MOSFETs with voltages vGS and vDS applied and with the

normal directions of current flow indicated.

Figure V-8

Figure V-7

NMOS

D

S

G

PMOS

D

S

G

NMOS

D

G B

SPMOS

D

G B

S


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C – TRANSISTOR CHARACTERISTICS

As for diodes, it is often useful to describe the transistor behaviors using its i-v characteristics.

I –iD – vDS characteristics

The description of physical operation can be used to derive the relationship between the drain

current iD and the drain-source voltage vDS. As depicted in Figure V-9, any variation of the drain-source

voltage v(x) along the x-axis produces an electrical field E along the channel in the negative x direction.

That causes the electron charge dq(x) to drift towards the drain with a velocity dx/dt.

The resulting drift current can now be found by multiplying the charge per unit length dq(x)/dx by

the drift velocity dv(x)/dx

[ ] ( )dx

xdvVxvvWCi tGSoxnD −−−= )(µ (3)

Figure V-9D

S

G

vGS

iD

iS = iD

iG = 0vDS

D

S

G

vGS

iD

vDS

iS = iD

iG = 0

Figure V-10


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where

µn Electron mobility in the channel (≈ 500 cm2/Vs)

Cox Capacitance per unit area of the parallel-plane capacitor formed by the gate electrode

and the channel

ox

oxox t

C ε= (4)

εox Permittivity of the silicon oxide (≈ 3.5 10-13 F/cm)

tox Thickness of the oxide layer.

W Transistor width

L Channel length

Depending on the operating mode, we can simplify expression (3)

- Triode region:

( ) ( )

−−=

−−= 2'2

21

21

DSDStGSnDSDStGSoxnD vvVvL

WkvvVvL

WCi µ (5)

and if vGS – Vt >> vDS, we have

( )[ ] ( )[ ]DStGSnDStGSoxnD vVvL

WkvVvL

WCi −=−= 'µ (6)

which show the resistance behavior of the transistor. This resistance rDS between drain and

source is equal to

( )1−

−== tGSoxn

D

DSDS Vv

LWC

iv

r µ (7)

- Saturation region

( ) ( )2'2

21

21

tGSntGSoxnD VvL

WkVvL

WCi −=−= µ (8)

The current is independent of the drain-source voltage.


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II – Determination of the iD – vDS curves

Figure V-11 shows an n-channel enhancement-type MOSFET with voltages applied and with the

normal directions of current flow indicated. The characteristic curves in Figure V-11 indicate that there

are three distinct regions of operation: the cutoff region, the triode region, and the saturation region.

The characteristic curves in Figure V-12 are similar to those of the BJT. Every curve depends on a

third variable, namely the voltage vGS .

This family of curves shows that the drain current follows equations (5), (6) and (8). Moreover, in

saturation, the MOSFET provides a drain current whose value is independent of the drain voltage vDS

and is determined by the gate voltage vGS according to the square-law relation (8) - Figure V-13.

Figure V-11

Figure V-12


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and the corresponding equivalent circuit model of the MOSFET operating in the saturation mode is

given in Figure V-14.

III – Output resistance in saturation: Channel-length modulation

As for BJTs, MOSFETs exhibit a phenomenon that is similar to the Early effect. In fact, in the

equivalent circuit shown in Figure V-14, the output transistor resistance is infinite. This is an

idealization based on the premise that once the channel is pinched off at the drain end, further increases

in vDS have no effect on the channel’s shape. In practice, increasing vDS beyond vDSsat does affect the

channel somewhat. Specifically, as vDS is increased, the channel pinch-off point is moved slightly away

from the drain towards the source.

Figure V-13

Figure V-14


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This is illustrated in Figure V-15, from which we note that the voltage across the channel remains

constant at vDSsat and the additional voltage applied to the drain appears as a voltage drop across the

narrow depletion region between the end of the channel and the drain region. This voltage accelerates

the electrons that reach the end of the channel and sweeps them across the depletion region into the

drain. Note, however that the effective channel length is reduced by ∆L, a phenomenon known as

channel-length modulation.

Since iD is inversely proportional to the channel length, it increases with vDS as

( ) ( )DStGSoxnD vVvL

WCi λµ +−= 121 2 (9)

where the positive constant λ is a MOSFET parameter. From Figure V-16, we observe that the straight-

line iD-vDS characteristics in saturation, when extrapolated, intercept the vDS axis at the point vDS = VA:

ADS Vv −=−=λ1 (10)

Typically, λ equal 0.005 to 0.03V-1, and correspondingly, VA is in the range 200 to 30V. Moreover,

VA is directly proportional to the length L and implies a finite value for the output resistance

( ) [ ] 11

21

Constant 21 −

−−

=

≈

−=

∂∂

= DtGSoxnvDS

Do IVv

LWC

vir

GS

λµλ (11)

where the current ID is the current corresponding to the particular value of vGS for which ro is being

evaluated.

Figure V-15


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This resistance can be approximated by

D

Ao I

Vr ≈ (12)

Thus, the equivalent-circuit in the saturation mode is shown in Figure V-17.

Note : For a PMOS, we have similar expressions to (5), (6) and (8), except that the electron mobility is

replaced by the hole mobility, i.e., µp. We have then

- Triode region:

( )

−−= 2

21

DSDStGSoxpD vvVvL

WCi µ (13)

Figure V-16

Figure V-17


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Here, the voltages vGS and vDS are negative and:

np µµ 4.0≈ (14)

- Saturation region:

( ) ( )DStGSoxpD vVvL

WCi λµ +−= 121 2 (15)

vGS, Vt, vDS and the constant λ are negative.

IV – Threshold voltage

In may applications, the substrate (or body) is connected to the source terminal, which results in the

pn junction between the substrate and the induced channel having a constant zero (cutoff) bias. In

integrated circuits, however, the substrate is usually common to many transistors. In order to maintain

the cutoff condition for all the substrate-to-channel junctions, the substrate is usually connected to the

most negative power supply in an NMOS circuit (or the most positive in a PMOS circuit). The resulting

reverse-bias voltage VSB between source and body will have an effect on device operation, i.e., a

change in the threshold voltage as

[ ]fSBftot VVV φφγ 22 −++= (16)

where φf is a physical parameter (2φf ≈ 0.6V) and Vto is the threshold voltage for VSB = 0. γ is a

fabrication-process parameter.

D – THE DEPLETION-TYPE MOSFET

I – Structure and operation

The structures of n-channel and p-channel depletion-type MOSFETs are similar to those of the

enhancement-type MOSFETs, with one important difference: the depletion MOSFET has a

physically implanted channel. Thus, an n-channel depletion-type MOSFET has an n-type silicon

region connecting the n+ source and drain regions at the top of the p-type substrate. Thus, if a voltage

vDS is applied between drain and source, a current iD flows for vGS = 0.


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The channel depth and hence its conductivity can be controlled by vGS in exactly the same manner as

in the enhancement-type device. Applying a positive vGS enhances the channel by attracting more

electrons into it. On the other hand, a negative vGS causes electrons to be repelled from the channel;

and thus the channel becomes shallower and its conductivity decreases. The negative vGS is said to

deplete the channel of its charge carriers, and this mode of operation is called depletion mode.

As the magnitude of vGS is increased in the negative direction, a value is reached at which the

channel is completely depleted of charge carriers and iD is reduced to zero even though vDS may be still

applied. This negative value of vGS is the threshold voltage of the n-channel depletion-type

MOSFET.

Note : The depletion-type MOSFET can be operated in the enhancement mode by applying a

positive vGS and in the depletion mode by applying a negative vGS..

II – Symbols and conventions

As for enhancement-type MOSFETs, depletion-type MOSFETs have distinguished circuit symbols

as shown in Figure V-18-a for the four-terminal transistor and Figure V-18-b for a three-terminal

device when the Body (B) is connected to the source.

(a) (b)

The simplified circuit symbol for the depletion-type differs from the corresponding one for the

enhancement device in that a shaded area is included to denote the implanted channel.

III –iD-vDS characteristics

The iD-vDS characteristics of a depletion-type n-channel MOSFET are sketched in Figure V-19.

Figure V-18

NMOS

D

S

G

PMOS

D

S

G

NMOS

D

G B

SPMOS

D

G B

S


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These characteristics are obtained from the circuit shown in Figure V-20 where the MOSFET is

represented by a four-terminal device but operates as a three-terminal transistor (body is grounded).

IV –iD-vGS characteristics

Even if the iD-vDS characteristics are similar, the iD-vGS characteristics are different since the

threshold voltage is negative (Figure V-21). Here, a special parameter for the depletion MOSFET is the

value IDSS of drain current obtained in saturation with vGS = 0 (i.e., the value from which we switch

from the enhancement mode to the depletion mode).

Figure V-19

Figure V-20


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In Figure V-19, it belongs to the curve vDS = vGS - Vt that delimits the triode and the saturation

regions.

E – DC ANALYSIS OF THE MOSFET

I – Example I

Let us consider the circuit shown in Figure V-22 with VDD = -VSS = 5V.

Figure V-21

Figure V-22

ID RD

VDD

VD

ID

RS

VSS


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The NMOS transistor operates at ID = 0.4 mA and VD = 1V. The parameters are µnCox = 20 µA/V2,

Vt = 2V, L = 10µm and W = 400µm. We neglect the channel length modulation effect (i.e., λ = 0).

For a complete circuit design, we have to determine the value of each element used in the circuit,

i.e., the two resistances RD and RS. Thus

( )2

21

tGSoxnD VVL

WCI −= µ (17)

This second order equation yields two values for VGS 1V and 3V. The first value does not make

physical sense since it is lower than the threshold voltage. Thus

VGS = -3 V

Since the gate is at ground potential, the source must be at –3V, thus the required value of RS is

( ) kΩ 50004.0

53=

−−−=

−=

D

SSSS I

VVR (18)

To establish a dc voltage of 1V at the drain, we must select

kΩ 100004.0

15=

−=

−=

D

DDDD I

VVR (19)

II – Example II

Analyze the circuit shown in Figure V-23 to determine the voltages at all nodes and the currents

through all branches.

Figure V-23

ID RD

VDD

ID

RS

RG1

RG2

VS

VD

VG

IGG


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Let Vt = 1V and µnCox (W/L) = 1 mA/V2. We have

VDD = +10V RD = RS = 6 kΩ RG1 = RG2 = 10 MΩ

and we neglect the channel-length modulation effect.

Since the gate current is zero, the voltage at the gate is simply determined by the voltage divider

formed by the two RG resistors

V 51010

101021

2 =+

=+

=GG

GDDG RR

RVV (20)

and the current is equal to

µA 5.010*10

56

1

==−

=G

GDDGG R

VVI (21)

With a positive voltage at the gate, the NMOS transistor will be turned on. BUT we do not know

whether the transistor will be operating in the saturation region or in the triode region.

The principle is to assume saturation-region operation, solve the problem, and then check the

validity or the assumption. If the assumption is not valid, the transistor will operate in the triode

region.

With the above assumption, we have

SDSDSS VIRIRI === *10*6** 3 (22)

thus

DGS IV 65 −= (23)

and

( ) ( ) ( )222 32165*1*21

21

DDtGSoxnD IIVVL

WCI −=−−=−= µ (24)

→ 08*25*18 2 =+− DD II (25)

This second order equation yields two values for ID: 0.89 mA and 0.5 mA.


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The first value gives a negative source voltage of

089.0*6565 <−=−= DGS IV (26)

Thus

mA5.0=DI (27)

and

V 36*5.0 ==SV V 75.0*610 =−=DV (28-a)

V 235 =−=GSV (28-b)

Since VD > VG – Vt the transistor is operating in saturation (as initially assumed).

III – Example III

For this last example, we have to determine the dc Q point of the circuit shown in Figure V-24 with

µnCox (W/L) = 0.25mA/V2, Vt = 1.5V, and VA = 50V.

We have

( ) ( ) ( ) ( )DSGSDStGSoxnD VVVVVL

WCI *02.015.1*25.0*211

21 22 +−=+−= λµ (29)

Since the dc gate current is zero, VGS = VD.

Figure V-24


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Thus, the above equation can be reformulated as

( ) ( )DDD VVI *02.015.1*125.0 2 +−= (30)

The voltage VD must satisfy the relation

DDDDDD IIRVV *1015 −=−= (31)

then, we obtain a third order equation from which the physically correct solution is ID = 1.09 mA.

Usually, because solving a third order equation is relatively complex, it is preferable to neglect the

modulation effect in order to obtain a second order equation (λ = 0.02). In this case, the drain current

will be 1.06 mA and

V4.406.1*1015 =−=DV (32)

F – THE MOSFET AS AN AMPLIFIER

To study the operation of the MOSFET as an amplifier, we will consider the conceptual amplifier

circuit shown in Figure V-25. This is not a practical circuit for two reasons. First, biasing a MOSFET

with a separate battery VGS is impractical. Second, a resistor RD is used in the drain circuit. Since most

MOSFET amplifiers are fabricated in integrated-circuit form where resistors are difficult to realize,

MOS transistors are used as load devices.

Figure V-25


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I – Calculation of the dc bias point

To operate the MOSFET as an amplifier, it must be biased at a point in the saturation region. We set

the input ac signal to zero and find the dc drain current from

DDDDD IRVV −= , tGSD VVV −> (33)

and

( )2

21

tGSoxnD VVL

WCI −= µ (34)

where we have neglected channel-length modulation.

II – MOSFET transconductance

Applying an ac signal vgs at the gate gives the following instantaneous gate-to-source voltage

gsGSGS vVv += (35)

Thus, the total instantaneous drain current is

( ) ( )

( )

( )2

22

21

21

21

gsoxn

gstGSoxn

tGSoxntgsGSoxnD

vL

WC

vVVL

WC

VVL

WCVvVL

WCi

µ

µ

µµ

+

−+

−=−+=

(36)

The first term is the bias current (equation (34)). The second term is directly proportional to vgs and

the last term, proportional to the square of the input signal, represents the undesirable nonlinear

distortion. To reduce the nonlinear distortion, the input signal should be kept small so that

( ) ( )221

gsoxngstGSoxn vL

WCvVVL

WC µµ >>− (37)

→ ( ) gstGS vVV >>−2 (38)


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This is the small-signal condition. Figure V-26 presents a graphical interpretation of the small-

signal operation of the enhancement MOSFET amplifier where the characteristic i-v curve is

approximated by its slope at the Q operating point. Here, we can write

dDD iIi +≈ (39)

with

( ) gstGSoxnd vVVL

WCi −= µ (40)

The parameter that relates the current id and the voltage vgs is the MOSFET transconductance gm

that is equal to the slope of the characteristic at the bias point and defined as

( )tGSoxngs

dm VV

LWC

vi

g −=≡ µ (41)

→ GSGS VvGS

Dm v

ig=

∂∂

≡ (42)

A large transconductance is obtained for short transistors (W/L >>1).

Figure V-26


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Note : An increase of the gate-source voltage results in a higher transconductance value. However,

that increasing gm by biasing the device at a larger VGS has the disadvantage of reducing the

allowable voltage signal swing at the drain.

Another useful expression for gm can be obtained by substituting for ( )tGS VV − by (equation (34))

( )WL

CIVV

oxn

DtGS µ

2=− (43)

→L

WCIg oxnDm µ2= (44)

This expression shows that, in contrast with the BJT, the transconductance is not proportional to the

dc bias current by to its square root. Moreover, at a given bias current, gm is proportional to the

transistor geometry.

A last expression for gm can be obtained by substituting for LWCoxn /µ by (equation (34))

( )2

2

tGS

Doxn VV

IL

WC−

=µ (45)

Thus

( )tGS

Dm VV

Ig−

=2 (46)

Compared to the transconductance of the BJT IC/Vt , we denote that

• ( )tGS VV − is much more higher than VT. Whereas VT is about 25 mV practical values for

( )tGS VV − is at least 0.2V or so.

→ The transconductance of the MOSFET is much lower than that of the BJT.

III – Voltage gain

The total instantaneous drain voltage can be expressed as

DDDDD iRVv −= (47)


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Under the small-signal condition, we have

( ) dDDdDDDDD iRViIRVv −=+−= (48)

which can be rewritten

gsDmdDd vRgiRv −=−= (49)

The voltage gain is given by

Dmgs

d Rgvv

−= (50)

The minus sign indicates that the output is 180o out of phase with respect to the input signal. As an

illustration, for a triangular input signal, Figure V-27 shows that the output is 180o out of phase with

respect to the input signal.

Note 1: We must verify that the small-signal condition is valid to ensure linear operation

( )tGS VVV−<< 2

2(51)

Note 2: We must verify that the transistor operates in the saturation region at all times, i.e., the Q

point did not enter the triode region during the ac signal swing

tGD Vvv −≥ maxmin (52)

Note 3: We must verify that the transistor operates in the saturation region at all times, i.e., the Q

point did not enter the cutoff region during the ac signal swing

DDD Vv ≤max (53)

IV – Small-signal equivalent circuit models

1 – π equivalent circuit

From a signal point of view, the FET behaves as a voltage-controlled current source. The input

resistance is very high (ideally infinite). The output resistance also is high. Putting all together, we

obtain the simplified Small-signal hybrid-π equivalent circuit shown in Figure V-28.


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However, the output resistance is not infinite (channel-length modulation). Its value is given

approximately by (Figure V-29)

D

Ao I

Vr ≈ (54)

Figure V-27

Figure V-28


________________________________________________________________________________________________________________________________________________________

The resulting voltage gain is expressed by

( )oDmgs

d rRgvv

//−= (55)

Note that the hybrid-π equivalent circuit of the FET is identical to the hybrid-π model of the BJT

except that for the FET rπ is infinite.

2 – T equivalent circuit

Through a simple circuit transformation, we can develop an alternative equivalent-circuit model

known as the T model (Figure V-30). Starting from the circuit in Figure V-30-a, we add a second

current source. This addition obviously does not change the terminal currents. The newly created

circuit node, labeled X (Figure V-30-b), is joined to the gate terminal G (Figure V-30-c). Observe that

the gate current does not change; that is, it remains equal to zero, and thus this connection does not

alter the terminal characteristics.

We have now a controlled-current source connected across its control voltage. We can replace it by

a resistance

mgsm

gs

gvgv 1

= (56)

as long as this resistance draws an equal current as the source (see the source absorption theorem). This

replacement is shown in Figure V-30-d, which depicts the alternative T model. Observe that the current

iG is still zero, so the parameters are all the same as in the original model

gsmd vgi = and gsmm

gss vg

gv

i ==/1

(57)

Figure V-29


________________________________________________________________________________________________________________________________________________________

If needed, the resistance ro can be added to complete the model (Figure V-31).

Figure V-31

Figure V-30


________________________________________________________________________________________________________________________________________________________

3 – Equivalent circuit with the Body

As mentioned above, the body effect occurs in a MOSFET when the substrate is not tied to the

source, but is connected to the most-negative power supply in the integrated circuit (Figure V-32).

In this case, we define a body transconductance as

constantconstant==∂

∂=

DSGS

vvBS

Dmb v

ig (58)

Recalling that iD depends on vBS through the dependence of Vt on VBS, this transconductance can be

related to gm by a parameter χ (typically between 0.1 and 0.3)

mmb gg χ= (59)

4 – Example I

Adding an ac source (Figure V-33) to one of the previous examples we already study in dc (Figure

V-24), we can deduce the ac gain and the input resistance using the equivalent ac circuit. From the dc

analysis, we have

( ) ( ) mA/V725.05.14.4*25.0 =−=−= tGSoxnm VVL

WCg µ (60)

thus

kΩ4706.1

50==or (61)

Figure V-32


________________________________________________________________________________________________________________________________________________________

The ac equivalent circuit is shown in Figure V-34.

Since vgs = vi, and :

( )oLDgsmo rRRvgv ////−= (62)

we obtain

( ) V/V 3.3//// −=−== oLDmgs

o

i

o rRRgvv

vv (63)

To determine the input resistance, we have to express the input current

( )( )G

ioLDm

G

i

i

o

G

i

G

oii R

vrRRg

Rv

vv

Rv

Rvv

i*3.4

////11 =+=

−=

−= (64)

Figure V-34

Figure V-33


________________________________________________________________________________________________________________________________________________________

Thus

MΩ33.23.4/ == Gin RR (65)

G – MOSFET BIAS CIRCUITS

An appropriate dc operating point is essential for a correct design.

I – Biasing of discrete MOSFET amplifiers

Figure V-35 shows four circuits for biasing the MOSFET in discrete-circuit design. Compared to

their counterparts in the BJT case, these bias circuits are somewhat easier to design because the gate

current is zero. On the other hand, VGS varies among devices a great deal more than does VBE of the

BJT, which usually falls in a narrow range.

1 – Bias circuit with a single power supply

The circuit in Figure V-35-a is the classic arrangement employed when a single power supply is

utilized. The voltage divider RG1+RG2 establishes a fixed voltage at the gate, and a self-bias resistor RS

is connected in the source. Since IG is zero, RG1 and RG2 can be selected to be very large allowing the

input resistance presented by the circuit to a signal source to be correspondingly high.

Resistor RS, like its counterpart RE in the BJT case, provides negative feedback that helps stabilize

the value of ID. Finally, RD is selected to be as large as possible to obtain high gain but small enough to

allow for the desired signal swing at the drain while keeping the MOSFET in saturation at all times.

2 – Bias circuit with two power supplies

When two power supplies are available, the somewhat simpler bias arrangement of Figure V-35-b

can be utilized. This circuit is based on the same principle as the circuit in Figure V-35-a.

Resistor RG establishes a dc ground on the gate and presents a high input resistance to a signal

source that may be capacitively coupled to the gate.

3 – Bias with a constant-current dc source

An even simpler bias arrangement is shown in Figure V-35-c.


________________________________________________________________________________________________________________________________________________________

Here, a constant-current source I feeds the source terminal, thus establishing

ID = I (66)

Figure V-35


________________________________________________________________________________________________________________________________________________________

4 – Bias circuit with feedback

A large feedback resistor RG (Figure V-35-d) can force the dc voltage at the gate to be equal to that

at the drain. Observe that in this circuit the output signal swing should be limited in the negative

direction to |Vt|.

II – Biasing in integrated circuit MOS amplifiers

The above dc bias circuits are not suitable for biasing MOSFET amplifiers that are to be fabricated

using IC technology. This is because they make extensive use of resistors. In MOS IC design, the use

of resistors is discouraged, for a resistor of even a modest value requires a relatively large area of the

silicon chip and thus is considered “expensive” in terms of the economics of IC fabrication.

Furthermore, the values of IC resistors exhibit large tolerances. By contrast, a MOSFET can be

fabricated in a very small area on the IC chip. Another reason is that the circuits shown anticipate that

the input signal source would be capacitively coupled to the amplifier input, that the output signal

would be capacitively coupled to either another amplifier stage or a load, and that bypass capacitors

could be employed to establish ac grounds as required. Although capacitors of few pF can be fabricated

in IC form, large coupling and bypass capacitors cannot be used. Rather, alternative bias circuits are

used in the design of IC MOS and BJT amplifiers (Figure V-36).

In this constant-current source circuit, the transistor Q1 whose drain is shorted to its gate (connected

as a diode) operates in the saturation region

( )2

11 2

1tGSoxnD VV

LWCI −

= µ (67)

Figure V-36


________________________________________________________________________________________________________________________________________________________

Since the gate currents are zero,

RVV

II GSDDRefD

−==1 (68)

The value of the reference current Iref is based on that of the resistance R. Now, for transistor Q2, the

output current Io will be

( )2

22 2

1tGSoxnDo VV

LWCII −

== µ (69)

We can then relate the output current to the reference current

( )( )1

2

//

LWLW

II

ref

o = (70)

In the special case of identical transistors, the circuit replicates or mirrors the reference current in the

output terminal. This, has given the circuit the name current mirror. In the above description of the

operation of this current source, we assumed that Q2 is operating in saturation because he has to

provide a constant current to the output. To ensure that Q2 is saturated, the drain voltage should satisfy

the relationship

tGSo VVV −≥ (71)

If in addition, we have to consider the channel–length modulation, the drain current of Q2, Io, will

equal the current in Q1, Iref, only at the value of Vo that causes the two devices to have the same VDS,

that is at Vo = VGS. As Vo is increased above this value, Io will increase according to the incremental

output resistance ro2 of Q2 (Figure V-37).

In summary, the current source and the current mirror have finite output resistance Ro

o

A

o

oo I

VrIV

R 202 ===

∆∆

(72)


________________________________________________________________________________________________________________________________________________________

III – Example of a current mirror circuit design

Given VDD = 5V and using Iref = 100µA, it is required to design the circuit of Figure V-36 to obtain

an output current whose nominal value is 100µA. We assume the two transistors are identical

(matched) with channel lengths of 10µm and channel widths of 100µm. k’n is equal to 20 µA/V2 and

Vt = 1V. VA in volts is equal to 10*L.

The choice of the output current value is based on the minimum allowed value of Vo

tGSo VVV −=min (73)

Knowing that

( )21 1

10100*20*

21100 −

=== GSDref VII (74)

we deduce VGS = 2V and Vomin = 1V. This result gives a resistance R of

kΩ30=−

=Ref

GSDD

IVV

R (75)

For the transistors used, L = 10µm, VA = 10*10 = 100V. Thus

MΩ1µA100V100

==or (76)

The output current will be 100µA at Vo = VGS. This current is constant because if the output voltage

changes by +3V (150% variation !!), the corresponding change in Io will be 3% or

µA310

36 ===

o

oo r

VI

∆∆ (77)

Figure V-37


________________________________________________________________________________________________________________________________________________________

H – MOSFET AMPLIFIERS

MOSFET amplifiers are named accordingly to the terminal which is grounded. Figure V-38 shows

the three basic configurations: the common-source - CS - (Figure V-38-a), the common-gate - CG -

(Figure V-38-b) and the common-drain - CD - (Figure V-38-c). This last configuration is also known

as the source-follower circuit - SF -.

As current-sources are used to bias the MOSFET, the resulting amplifiers are said to be active

loaded.

Note : For CS and CG configurations, we will need the PMOS version of the current source, whereas

for the source-follower, the NMOS circuit of Figure V-36 can be employed.

→ It follows that implementation of the basic amplifier circuits requires both n-channel and

p-channel devices and thus requires the use of CMOS technology.

I – CMOS common-source amplifier

Figure V-39 shows the circuit of the CMOS common-source amplifier. If we assume that the

transistors Q2 and Q3 (current mirror) are matched, the i-v characteristic of the load device will be that

shown in Figure V-40. This is simply the iD-vSD characteristics of the transistor Q2 for a constant

source-gate voltage VSG (VSG and not VGS because we have a p-channel).

Figure V-38


________________________________________________________________________________________________________________________________________________________

As expected, Q2 behaves as a current source when it operates in saturation (obtained when v = vSD

exceeds VSG - |Vtp|) and exhibits a finite incremental resistance ro2 :

ref

Ao I

Vr 2

2 = (78)

Before determining the small-signal voltage gain, it is instructive to examine its transfer

characteristic. This can be determined using the graphical construction shown in where the iD-vDS

characteristics of the transistor Q1 (Figure V-40) are superimposed on the load curve (Figure V-41).

Now since vGS1 = vI, each of the iD-vDS characteristics corresponds to a particular value of vI. The

intersection of each particular curve with the load curve gives the corresponding value of vDS1, which is

equal to the output voltage vo. In this way, we can obtain the transfer characteristic point by point

(Figure V-42).

Figure V-39

Figure V-40


________________________________________________________________________________________________________________________________________________________

The resulting transfer characteristic has four distinct segments labeled I to IV and obtained for one

of four combinations of the modes of operation of Q1 and Q2. Note also that we have labeled two

important breakpoints A’ and B’ in the transfer characteristic in correspondence with the intersection

points A and B in Figure V-41.

For amplifier operation, segment III is the one of interest. Observe that in region III, the transfer

curve is almost linear and is very steep, indicating large voltage gain.

In this segment, both Q1 and Q2 operate in saturation. The small-signal voltage gain can be

determined by replacing Q1 by its small-signal model and replacing Q2 with its output resistance ro2.

Since the load is ro1//ro2, the voltage gain is equal to

( )211 // oomi

ov rrg

vv

A −== (79)

Figure V-42

Figure V-41


________________________________________________________________________________________________________________________________________________________

Using physical parameters of the transistor in (41), we have

refoxnm IL

WCg1

2

= µ (80)

and :

ref

Ao I

Vr 1

1 = (81)

Thus

21

1 11112

AA

refoxnv

VVIL

WCA+

−= µ (82)

The MOSFET common-source amplifier can be designed to provide

• A large voltage gain (20 to 100),

• A very high input resistance 1/gm1,

• However, its output resistance is also high.

II – CMOS common-gate amplifier

Figure V-43 shows the CMOS common-gate amplifier. Note that it is very similar to the common-

source circuit except that here the gate is connected to a constant dc voltage Vbias and the input signal is

applied to the source.

Replacing Q1 with its small-signal model and replacing Q2 with its output resistance ro2 results in the

amplifier equivalent circuit shown in Figure V-44. Observe that since the source of Q1 is not grounded,

a signal voltage vbs1 develops between the body and the source. The current source gmb1 vbs1 is therefore

included in the model. Similarly, the body is at signal ground and thus vI = -vb1. Thus, we can express

the controlled sources in terms of vi (Figure V-45).

The node equation at the output node can be written as

211

1 o

oimbim

o

oi

rv

vgvgr

vv=++

−(83)


________________________________________________________________________________________________________________________________________________________

Figure V-43

Figure V-44

Figure V-45


________________________________________________________________________________________________________________________________________________________

Thus, the voltage gain is

( )211

11 //1oo

ombm

i

ov rr

rgg

vv

A

++== (84)

Normally, 1/ro1 << gm :

( )( )2111 // oombmv rrggA +≈ (85)

This result is similar to that for the CS amplifier given in equation (79) with two exceptions: the CG

amplifier is non-inverting and its gain is influenced by the body effect. The input resistance Ri of the

CG amplifier can be determined from the input current

( )1

111o

oiimbm r

vvvggi

−++= (86)

Substituting for vo by using the gain expression of (84) results in

( )

+

+≈=

1

2

11

11

o

o

mbmi

ii r

rggi

vR (87)

This expression differs from the expected value1/gm1 by the factor 1 + ro2/ro1.

The MOSFET common-gate amplifier can be designed to provide

• A voltage gain of magnitude similar to that of the CS amplifier

• A much lower input resistance

The most important application of the common-gate amplifier is in a configuration called the

cascode circuit.

III – CMOS common-drain or source-follower configuration

Like the emitter follower, the source follower is used as a buffer amplifier (Figure V-46). Although

its voltage gain is less than unity, it has a low output resistance and is thus capable of driving low-

impedance loads with little loss of gain. In this circuit, the transistor Q1 is biased by the constant-

current source formed by the current mirror Q2-Q3. Transistor Q2 acts also as an active load for Q1

through its output resistance ro2 as shown in Figure V-47.


________________________________________________________________________________________________________________________________________________________

The input resistance is very high because the signal is applied to the gate of Q1. This is a significant

advantage over the emitter follower whose input resistance, though high, is limited by the finite β of

the BJT. Moreover, since vbs1 = - vs1, the current-source gmb1*vs1 is controlled by the input voltage vs1.

We can therefore replace the current source by a resistance (1/gmb1) connected between S1 and

ground (apply the source-absorption theorem). We can then combine the three parallel resistances

1/gmb1, ro1, and ro2, to obtain a simplified circuit (Figure V-48). The output voltage can now be written

as

111 gsSmso vRgvv == (88)

and

11111 gsSmgssgsi vRgvvvv +=+= (89)

Figure V-46

Figure V-47


________________________________________________________________________________________________________________________________________________________

Thus

Sm

Sm

i

ov Rg

Rgvv

A1

1

1+== (90)

Usually, Sm Rg 1 >>1, and the voltage gain is less than but close to unity. Thus the signal at the source

follows the input signal rather closely, giving the circuit the name source follower. An alternative

expression for Av that yields additional insight into the operation of the source follower is

χ+=

+≈

+++=

11

11 11

1

2111

1

mbm

m

oombm

mv gg

g

rrgg

gA (91)

The output resistance is determined by short-circuiting the input signal thus applying a test voltage

vx to the output terminal

( )χ+=

≈

=

111//1////1//1

11121

11 mmbmoo

mbmo ggg

rrgg

R (92)

IV – Other applications of MOSFETs

1 – NMOS load devices

In NMOS technology, two types of load elements are used: the Enhancement-type MOSFET with

the drain connected to the gate (Figure V-49-a), and the depletion MOSFET with the gate connected to

the source (Figure V-49-b).

Figure V-48


________________________________________________________________________________________________________________________________________________________

(a)

(b)

In the first circuit, the diode-connected enhancement MOSFET has a small-signal resistance equal to

1/gm and

( ) ttoxn VvVvL

WCi ≥−= 2

21 µ (93)

In the second circuit, the diode-connected depletion MOSFET operates in the saturation region if the

voltage across the two terminal device exceed –VtD. Let IDSS be the drain-to-source current with the gate

shorted to the source. In saturation the current is then equal to

+=

+=

ADSS

AtDoxn V

vIVvV

LWCi 11

21 2µ (94)

2 – NMOS amplifier with enhancement load

Figure V-50 shows the NMOS amplifier with an enhancement load. A graphical construction

(Figure V-51) allows to obtain the voltage transfer characteristic vo versus vI (Figure V-52). Observe

that although the load transistor Q2 operates in saturation at all times, the amplifying transistor Q1 can

be operated in cutoff (segment I), in saturation (segment II), or in the triode region (segment III).

i

v

i

v

Figure V-49

i

v

Vt

i

v

-VtD

IDSS


________________________________________________________________________________________________________________________________________________________

Figure V-51

Figure V-50

Figure V-52


________________________________________________________________________________________________________________________________________________________

In segment II, we have

( )( )

( )( ) IttDDo v

LWLW

VLWLW

VVv2

1

2

1

//

//

−

+−= (95)

Thus, the voltage gain is

( )( )2

1

//LWLW

Av −= (96)

when the body effect has been neglected for transistor Q2. In the other hand, with this effect, we obtain

( )( )2

1

2 //

11

LWLW

Av χ+−= (97)

3 – NMOS amplifier with depletion load

Using a depletion load results in an amplifier (Figure V-53) with performance superior to that of the

enhancement load circuit.

Neglecting the body effect in the load transistor Q2, we can use the graphical construction illustrated

in Figure V-54 to obtain the amplifier transfer characteristic sketched in Figure V-55. As shown, the

characteristic is steep, indicating a high voltage gain in region III, which is obtained when both Q1 and

Q2 are operated in saturation. Using the equivalent circuit in Figure V-56, we obtain

( )( )2

1

2

1

2

121

21 /

/1////1LWLW

gg

gg

rrg

gAm

m

mb

moo

mbmv χχ

−=−=−≈

−= (98)

Figure V-53


________________________________________________________________________________________________________________________________________________________

Comparison of equations (96) and (98), reveals that the gain of the depletion-load amplifier is a

factor (1+χ)/χ greater.

Figure V-54

Figure V-55

Figure V-56


________________________________________________________________________________________________________________________________________________________

Note : Nevertheless, the CMOS amplifier gain is the highest. On the other hand, the depletion-load

amplifier circuit is simpler than the CMOS circuit.

I – OTHER APPLICATIONS OF THE MOSFET

There are many applications of the MOSFET: the inverter, which will be studied in the next chapter,

the analog switch, and the transmission gate.

I – NMOS analog switch

The MOSFET is widely used to switch digital circuits. Examples of such applications include the

design of analog-to-digital and digital-to-analog converters and switched-capacitor filters. To

appreciate the requirements placed on an analog switch as compared to a digital switch, consider the

circuit in Figure V-57.

When the switch is open, its resistance should be very high (ideally infinite). In the closed position,

the switch should act as close to a short circuit as possible. A more appropriate circuit is the one shown

in Figure V-58 that uses an NMOS transistor. As an illustration, let Vt be equal to +2V and VA in the

range ±5V. In order to keep the substrate-to-source and substrate-to-drain pn junctions reverse-biased

at all times, the substrate terminal is connected to –5V. Since the MOSFET is a symmetric device

(source and drain are interchangeable) the operation of the device as a switch is based on this

interchangeability of roles. The purpose of the control signal vC is to turn the switch on and off.

In order to turn the transistor on for all possible input signals levels, the high value of vC should be at

least + 7V 5 + 2 = +7V and the value of vC to turn the transistor off should be a maximum of –3V.

However, these levels are not sufficient in practice, since the transistor will be barely on and barely off

at the limits.

Figure V-57


________________________________________________________________________________________________________________________________________________________

Thus, the range of the control voltage has to be at least equal to the range of the analog input signal

being switched. Unfortunately, though, the on resistance of the switch will depend to a large extent on

the value of the analog input signal, an undesirable characteristic.

II – The CMOS transmission gate

To improve the above circuit, we utilize a CMOS switch shown in (Figure V-59) commonly known

as a transmission gate. As in the previous case, the analog signal lies in the range –5V to +5V. To

prevent the substrate junctions from becoming forward-biased at any time, the substrate of the p-

channel device is connected to the most positive voltage level (+5V) and that of the n-channel device is

connected to the most negative voltage level (–5V).

The two gates are controlled by two complementary signals denoted vC and Cv . Unlike the NMOS

switch, the levels of vC can be the same as the extremes of the analog signal. When vc is at the low

level, the gate of the n-channel will be at –5V, thus preventing the n-channel device from conducting

for any value of the input signal. Simultaneously, the gate of the p-channel device will be at +5V,

which prevents that device from conducting for any value of vA. Thus with vC low the switch is open.

In order to close the switch, we have to raise the control signal vC to the high level of +5V.

Correspondingly, the n-channel device will have its gate at +5V and will thus conduct for any value of

the input signal in the range –5V to +3V. Simultaneously, the p-channel device will have its gate at

–5V and will thus conduct for any value of vA in the range –3V to +5V.

Furthermore, we can see that as one device conducts more heavily, conduction on the other device is

reduced. Thus as the resistance rDS of one device decreases, the resistance of the other increases, with

the parallel equivalent remaining approximately constant.

Figure V-58


________________________________________________________________________________________________________________________________________________________

Note 1 : The operation of the transmission gate (in the closed position) can be better understood from

the two equivalent circuits shown in Figure V-60. Note the interchangeability of the roles

played by the source and drain of each of the two devices.

Note 2 : Compared to the single NMOS switch, the transmission gate provides better performance at

the expense of greater circuit complexity and chip area.

Figure V-59

Figure V-60


________________________________________________________________________________________________________________________________________________________

Finally, it is useful to show in Figure V-61 the transmission gate together with its commonly used

circuit symbol.

With:

• C = 0 : Bi-directional open circuit

• C = 1 : Bi-directional short circuit

Figure V-61

C

Output

C

Input

C

Output

C

Input

elg 2135 electronics i fifth chapter: field effect transistors

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