elg 2135 electronics i sixth chapter: digital circuits

ELG 2135

ELECTRONICS I

SIXTH CHAPTER:

DIGITAL CIRCUITS

Session WINTER 2003

Dr. M. YAGOUB

Sixth Chapter: Digital Circuits VI - 2_________________________________________________________________________________________________________________________________________________________

________________________________________________________________________________________________________________________________________________________

This last chapter is devoted to digital circuits and particularly to MOS digital integrated circuits, by

far the most popular technology for the implementation of digital systems.

A – INTRODUCTION

The concept of logic circuits refers to different families depending on the used technology and/or,

structure (Figure VI-1).

Each logic-circuit family offers a unique set of advantages and disadvantages. A comparison

between the different technologies can highlight some points:

• CMOS Technology: It is by a large margin the most dominant of all the IC technologies available

for digital-circuit design. Such circuits exhibit many advantages:

- They dissipate much less power than bipolar logic circuits, and thus one can pack

more CMOS circuits on a chip than is possible with bipolar circuits.

- They exhibit a high input impedance, which allow the designer to use charge storage

as a means for the temporary storage of information in both logic and memory

circuits.

- Their feature size (that is, MOS transistor minimum channel length) has decreased

dramatically over the years. This permits very tight circuit packing and,

correspondingly, very high levels of integration.

CMOS Bipolair BiCMOS AsGa

TTL ECLComplementaryCMOS

Pass-TransistorLogic

PseudoNMOS

DynamicLogic

Digital integrated circuit technologies and logic-circuit families

Figure VI-1


________________________________________________________________________________________________________________________________________________________

• Bipolar Technology: Two logic-circuit families based on the bipolar junction transistor are in use:

TTL (Transistor-Transistor Logic) and ECL (Emitter-Coupled Logic). TTL was for many years

the most widely used logic-circuit family. Its decline was precipitated by the advent of the VLSI

ear. TTL manufacturers, however, fought back with the introduction of low-power and high-speed

versions (e.g., utilizing Schottky diodes). ECL logic-circuit family is based on the current-switch

implementation of the inverter we will study later. Since ECL is the fastest family, it is used in

VLSI circuit design when very high operating speeds are required.

• BiCMOS Technology: This technology combines the high operating speeds possible with BJTs

(because of their higher conductance) with the low power dissipation and other excellent

characteristics of CMOS. Like CMOS, BiCMOS allows for the implementation of both analog and

digital circuits on the same chip.

• AsGa Technology: Gallium arsenide devices exhibit a high carrier mobility which results in very

speeds of operation.

B – DIGITAL LOGIC INVERTER

The logic inverter is the most basic element in digital circuit design. As its name implies, the logic

inverter inverts the logic value of the input signal (for a logic « 1 » input, the output will be a logic

« 0 » and vice versa). In terms of voltage levels, a low input will generate a high output and vice versa.

I – Operation

Inverters are implemented using transistors operating as voltage controlled switches (figure VI-2).

Figure VI-2

VC

R

vi

vo

VC

R Faible vi

vo

VC

R Forte vi

vo

Ron

Voffset


________________________________________________________________________________________________________________________________________________________

In this Figure, when the input voltage vi is low, the switch is open and vo = VC. When vi is high, the

switch will be closed and vo is almost zero. Since transistor switches are not perfect, the “on” switch

has a finite closure resistance and an offset voltage (Voffset).

II – Inverter voltage transfer characteristic

To understand the inverter behavior, let us consider the voltage transfer characteristic shown in

Figure VI-3.

For a low input vi, the output is high and equal to VOH. This value does not depend on the value of vi

as long as vi does not exceed the value labeled VIL. This value is the maximum value that vi can have

while being interpreted by the inverter as representing a logic « 0 ».

From this value, the inverter enters its amplifier region also called the transition region. On the

other hand, VIH is the minimum value that vi can have while being interpreted by the inverter as

representing a logic « 1 ».

III – Noise margins

The insensitivity of the inverter output to the exact value of vi within allowed regions is a great

advantage that digital circuits have over analog circuits. In other words, if some reason, a disturbing

signal (called noise) is superimposed on the output of the driving inverter, the driven inverter would not

be “bothered” so long as this noise does not decrease the voltage at its input below VIH.

Figure VI-3

vo

NML

VOH

vi VOL VIL VIH VOH

VOL

NMH


________________________________________________________________________________________________________________________________________________________

Thus, we can define a noise margin for high input, NMH of

IHOHH VVNM −= (1)

Similarly, a noise margin for low input can be defined as

OLILL VVNM −= (2)

The four parameters, VOH, VOL, VIH and VIL define the voltage transfer characteristic (VTC) of an

inverter and determine its noise margins.

Note: In the case of an ideal VTC (Figure VI-4), a steep transition gives

2C

IHILV

VV == (3)

0=OLV (4)

COH VV = (5)

Thus

2C

HLV

NMNM == (6)

Figure VI-4

vo

VOH = VC

vi VIL = VIH =VC /2 VC

VOL = 0


________________________________________________________________________________________________________________________________________________________

III – The BJT logic inverter

The circuit of a BJT logic inverter is shown in Figure VI-5.

The operation of the circuit as a logic inverter makes use of the cutoff and saturation modes. In fact,

if the input voltage is high, representing a logic “1”, the transistor will saturate. Thus, the output will be

VCEsat (approximately 0.2V) representing a logic “0”.

Conversely, if the input voltage is low, representing a logic “0”, the transistor will be cutoff. The

collector current will be zero, and the output voltage will be VCC , which represent a logic “1”.

Thus, the transfer characteristic (VTC) is approximated by three straight-line segments

corresponding to the operation of the BJT in the cutoff, active and saturation regions (figure VI-6). To

illustrate this concept, let us consider the circuit in figure VI-5 with

RB = 10 kΩ

RC = 1 kΩ

β = 50

VCC = 5V

Figure VI-5


________________________________________________________________________________________________________________________________________________________

• At vi = VOL (low amplitude), we have

V2.0=== CEsatOLi VVv (7)

V5=== CCOHo VVv (8)

• At vi = VIL, the transistor begins to turn on, thus

V7.0≈= ILi Vv (9)

• For VIL < vi < VIH, the transistor is in the active mode. It operates as an amplifier whose

small-signal gain is

π

βrR

Rvv

AB

C

i

ov +

−== (10)

The gain depends on the value of rπ, which in turn is determined by the collector current and

hence by the value of vi. As the current through the transistor increases, rπ decreases and we

can neglect rπ relative to RB.

Figure VI-6


________________________________________________________________________________________________________________________________________________________

Thus

V/V 5−=−≈B

Cv R

RA β (11)

• At vi = VIH, the transistor enters the saturation region. Thus

( )mA 096.0

/=

−=

βCCEsatCC

BRVV

I (12)

and

V 66.1=+= BEBBIH VRIV (13)

• At vi = VOH (high amplitude), the transistor will be deep into saturation

V5== OHi Vv (14)

V2.0=== CEsatOLo VVv (15)

Thus

( )( ) 1.1

//

forced =−

−=

BBEOH

CCEsatCC

RVVRVV

β (16)

The noise margins can now be computed

V 34.366.15 =−=−= IHOHH VVNM (17)

V 5.02.07.0 =−=−= OLILL VVNM (18)

Obviously, the circuit is not an ideal inverter.

• The voltage gain in the transition region can be computed from the coordinates of the

breakpoints X and Y

V/V 57.066.1

2.05−=

−−

−=vA (19)

which is equal to the approximate value found with equation (11).


________________________________________________________________________________________________________________________________________________________

IV – CMOS digital logic inverter

The basic CMOS inverter is shown in Figure VI-7.

It utilizes two matched enhancement-type MOSFETs. One, QN, with an n channel and the other, Qp,

with a p channel, is assimilated to a load. As the body of each device is connected to its source, we can

use the simplified circuit schematic diagram shown in Figure VI-8.

Figure VI-7

Figure VI-8


________________________________________________________________________________________________________________________________________________________

1- Circuit Operation

• When the input is « 1 », vi = VDD (Figure VI-9) and

DDGSN Vv = and oDSN vv = (20)

corresponding to the curve in figure VI-10.

Moreover, since vSGP < |Vt|, the load curve will be a horizontal straight line at almost zero

current level. This means that the power dissipation in the circuit is very small.

Figure VI-10

Figure VI-9


________________________________________________________________________________________________________________________________________________________

However, that although QN is operating at nearly zero current and zero drain-source voltage,

it provides a low resistance path between the output terminal and ground

( )tnDDn

n

DSN

VVL

Wkr

−

='

1 (21)

Figure VI-11 shows the equivalent circuit of the inverter when the input is high.

• When the input is « 0 », vi = 0 V (Figure VI-12) and

0=GSNv and DDDSN Vv = (22)

Figure VI-11

Figure VI-12


________________________________________________________________________________________________________________________________________________________

In this case, the load curve is shown in Figure VI-13 with vSGP = VDD (high voltage and small

current).

Thus the power dissipation in the circuit of the inverter is very small in both extreme cases.

QP provides a low-resistance path between the output terminal and the dc supply

( )tpDDp

p

DSP

VVL

Wkr

−

='

1 (23)

The equivalent circuit is shown in Figure VI-14.

Figure VI-13

Figure VI-14


________________________________________________________________________________________________________________________________________________________

Note 1: With the input high, QN, with its low output resistance can sink a relatively large load current

which can quickly discharge the load capacitance. Thus, it will pull the output voltage down

and hence is called « pull-down » device. Similarly, with the input low, QP can source a

relatively large load current which can quickly charge up a load capacitance, thus pulling the

output voltage up. Hence this transistor is known as the « pull-up » device.

Note 2: The output voltage levels are 0 and VDD, and thus the signal swing is the maximum possible.

Note 3: The low-resistance paths ensure that the inverter is less sensitive to the effects of noise or

other disturbances.

Note 4: The input impedance of the inverter is infinite. Thus the inverter can drive an arbitrarily large

number of similar inverters with no loss in signal level.

2- Voltage transfer characteristic

The voltage transfer characteristic of the CMOS inverter can be obtained by repeating the graphical

procedure for al intermediate values of vi. Thus, for QN we have

( )

−−

= 2'

21

ootnin

nDN vvVvL

Wki for vo ≤ vi - Vtn (24)

and

( )2'

21

tnin

nDN VvL

Wki −

= for vo ≥ vi - Vtn (25)

Similarly for QP we have

( )( ) ( )

−−−−−

= 2'

21

oDDoDDtpiDDp

pDP vVvVVvVL

Wki

for vo ≥ vi + |Vtp| (26)and

( )2'

21

tpiDDp

pDP VvVL

Wki −−

= for vo ≤ vi + |Vtp| (27)


________________________________________________________________________________________________________________________________________________________

The inverter is usually designed to have

tptn VV = (28)

and

pp

nn L

WkL

Wk

=

'' (29)

thus the inverter will have a symmetric transfer characteristic (Figure VI-15) where the vertical line is

limited by

( ) tDD

o VVBv +=2

and ( ) tDD

o VVCv −=2

(30)

To determine VIH and VOL we note that QN is in the triode region and QP in the saturation region.

Using the current equations (respectively (24) and (27)) we obtain

( ) ( )22

21

21

tiDDooti VvVvvVv −−=−− (31)

Figure VI-15


________________________________________________________________________________________________________________________________________________________

Differentiating both sides relative to vi results in

( ) ( )tiDDi

ooo

i

oti VvV

dvdv

vvdvdv

Vv −−−=−+− (32)

With

IHi Vv = (33)

and

1−=i

o

dvdv

(34)

we have

2DD

IHoVVv −= (35)

Substituting in equation (31), we obtain

( )tDDIH VVV 2581

−= (36)

Similarly, knowing that

ILDDDD

IH VVVV −=−22

(37)

we have

( )tDDIL VVV 2381

+= (38)

The noise margins can now be determined as follows

( ) ( )tDDtDDDDIHOHH VVVVVVVNM 238125

81

+=−−=−= (39)

and

( ) ( )tDDtDDOLILL VVVVVVNM 2381023

81

+=−+=−= (40)


________________________________________________________________________________________________________________________________________________________

As expected, the symmetry of the voltage transfer characteristic results in equal noise margins.

3- Dynamic operation

The speed of operation of a digital system is determined by the propagation delay of the logic gates

used to construct the system. The basic circuit is shown in Figure VI-16.

With an ideal pulse excitation (Figure VI-17), the response shows rise and fall times due to the

charge and discharge of the capacitance.

Since the two times are equal, we can write

( )2'

21

tDDn

n

tPLH

VVL

Wk

CVt

−

= (41)

Figure VI-16

Figure VI-17


________________________________________________________________________________________________________________________________________________________

and

( )

−+

−−

=DD

tDD

tDD

t

tDDn

n

PHL VVV

VVV

VVL

Wk

Ct43

ln212

'(42)

These points are reported in the characteristic (Figure VI-18).

C – DYNAMIC OPERATION

One of the applications of CMOS inverters is the one shown in Figure VI-19, where a first inverter

Q1-Q2 drives a second inverter Q3-Q4.

The propagation delay of the inverter Q1-Q2 can be determined using the circuit in figure VI-16.

We can show that the total capacitance of the load inverter Q3-Q4 is equal to

wggdbdbgdgd CCCCCCCC ++++++= 432121 22 (43)

which leads to the circuits in figures VI-20. Thus,

DDn

n

PHL

VL

Wk

Ct

='

6.1 (44)

for a value of Vt = 0.2 VDD.

Figure VI-18


________________________________________________________________________________________________________________________________________________________

Figure VI-19

Figure VI-20


________________________________________________________________________________________________________________________________________________________

An alternative approximate expression for this time

DDn

n

PHL

VL

Wk

Ct

≈'

7.1 (45)

allows to obtain a similar relation for the second delay time

DDp

p

PLH

VL

Wk

Ct

≈'

7.1 (46)

The total propagation delay time is then

( )PLHPHLP ttt +=21 (47)

The dynamic power dissipation is

2DDD VCfP = (48)

for an input signal of frequency f.

C – LOGIC GATES CIRCUITS

I – Single input gate

From the inverter circuit, it is possible to construct different logic circuits that exhibit logic

functions. In fact, since the inverter consists of an NMOS pull-down transistor, and a PMOS pull-up

transistor, operated by the input voltage in a complementary fashion, we have built a CMOS logic gate

that consists of two networks: the pull-down network (PDN) constructed of NMOS transistors, and the

pull-up network (PUN) constructed of PMOS transistors.


________________________________________________________________________________________________________________________________________________________

1- PDN Gates

The PDN conducts for all input combinations that require a low input. We can built a NOR logic

function

BAY += or BAY += (49)

shown in Figure VI-21. In this configuration, QA will conduct when A is high (vA = VDD), and will then

pull the output node Y down to ground (vY = 0). Similarly, when QB will conduct, Y is zero (vY = 0).

The circuit shown in Figure VI-22 is equivalent to the NAND function

BAY = or BAY = (50)

Figure VI-21

Figure VI-22


________________________________________________________________________________________________________________________________________________________

which will conduct only when A and B are both high simultaneously. As a final example, the circuit in

Figure VI-23, gives

CBAY += or CBAY += (51)

2- PUN Gates

Similarly, the circuits in Figures VI-24, VI-25 and VI-26 gives the following logic functions :

BAY += (52)

BAY = (53)

CBAY += (54)

Figure VI-23


________________________________________________________________________________________________________________________________________________________

Figure VI-24

Figure VI-25

Figure VI-26


________________________________________________________________________________________________________________________________________________________

II – Two-input circuits

From the above examples, we can built logic circuits that have two inputs.

1- Two-input NOR gate

The circuit in Figure VI-27 shows a two-input NOR function

BABAY =+= (55)

2- Two-input NAND gate

The two-input NAND function is described by (Figure VI-28)

BABAY +== (56)

Figure VI-27


________________________________________________________________________________________________________________________________________________________

III – Exclusive-OR function

Form the above functions, it is possible to construct the logic exclusive-OR (Figure VI-29) :

BABAY += (57)

Using the Morgan’s law, we can reformat this expression to

BABAY += (58)

The corresponding circuit is shown in Figure VI-30.

Once the gate synthesized, the significant step remaining in the design is to decide on W/L ratios

for all devices. Let W/L = p for a PMOS transistor and W/L = n for a NMOS transistor. The

purpose is to find the worst-case gate delay for a circuit.

This is done when the PDN will be able to provide a capacitor discharge current at least equal to

that of an NMOS transistor, and the when the PUN will be able to provide a capacitor discharge current

at least equal to that of an PMOS transistor. The derivation of the equivalent W/L ratio for the

circuit is based on the fact that the on resistance is inversely proportional to W/L.

Figure VI-28


________________________________________________________________________________________________________________________________________________________

If a number of MOSFETs are connected in series, the equivalent series resistance is equal to

...21 ++= DSDSseries rrR (59)

resulting in the following expression

( ) ( )

( ) ( ) ( )equivalentseries

series

LWLWLWR

LWLWR

/Constant...

/1

/1Constant

.../

Constant/

Constant

21

21

=

++=→

++=

(60)

Thus

( )

( ) ( ) .../1

/1

1/

21

++=

LWLW

LW equivalent (61)

Similarly, a parallel connection of transistors results in an equivalent W/L of

( ) ( ) ( ) .../// 21 ++= LWLWLW equivalent (62)

Figure VI-29


________________________________________________________________________________________________________________________________________________________

From these expressions, a logic circuit can be built. As an example of proper size, consider the four-

input NOR gate shown in Figure VI-31 where the resulting equivalent W/L is equal to 2 when

connected in series and 8 when connected in parallel.

This result means that we have to select the W/L ration of each PMOS transistor to be 4 times that

of QP of the basic inverter, that is 4p.

As another example, we show in Figure VI-32 the proper size for a four-input NAND gate.

Note: Because p is usually two or three times n, the NOR gate will require much greater area than the

NAND gate. For this reason, NAND gates are preferred for implementing combinational logic

functions in CMOS.

D – PSEUDO-NMOS LOGIC CIRCUITS

Despite its many advantages, CMOS suffers from increased area, and correspondingly, increased

capacitance and delay, as the logic gates become more complex. For this reason, digital integrated-

circuit designers have been searching for forms of CMOS logic circuits that can be used to supplement

the complementary-type circuits studied above.

Figure VI-30


________________________________________________________________________________________________________________________________________________________

I – Pseudo-NMOS inverter

Figure VI-33 shows a modified form of the CMOS inverter. Here, only QN is driven by the input

voltage while the gate of QP is grounded, and QP acts as an active load for QN. Each input must be

connected to the gate of only one transistor or, alternatively, only ONE additional transistor will be

needed for each additional gate input.

Figure VI-31

Figure VI-32


________________________________________________________________________________________________________________________________________________________

Since we have a driver transistor and a load transistor, this kind of circuit is called a pseudo-NMOS

inverter. For comparison purposes, we shall briefly mention the two older forms of NMOS logic. The

earliest form utilized an enhancement MOSFET for the load element. Such circuits suffer from a

relatively small logic swing, small noise margins, and high static power dissipation.

This technology was replaced with depletion-load NMOS circuits. It was initially expected that the

depletion NMOS with VGS = 0 would operate as a constant-current source and would thus provide an

excellent load element. However, the body effect in the depletion transistor causes its i-v characteristic

to deviate considerably from that a constant-current source.

Although depletion-load NMOS has been virtually replaced by CMOS, one can still see some

depletion-load circuits in specialized applications.

The pseudo-NMOS inverter we are about to study is similar to depletion-laod NMOS but has the

advantage of being directly compatible with complementary CMOS circuits.

Its static characteristics are given by

Transistor N :

- Saturation region (vi – Vt ≤ vo) :

( )2

21

tinDN Vvki −= (63)

Figure VI-33


________________________________________________________________________________________________________________________________________________________

- Triode region (vi – Vt ≥ vo) :

( )

−−= 2

21

ootinDN vvVvki (64)

Transistor P :

- Saturation region (vo ≤ Vt ) :

( )2

21

tDDpDP VVki −= (65)

- Triode region (vo ≥ Vt) :

( )( ) ( )

−−−−= 2

21

oDDoDDtDDpDP vVvVVVki (66)

with

nnn L

Wkk

= ' and

ppp L

Wkk

= ' (67)

To obtain the voltage transfer characteristic, we superimpose the load curve on the i-v characteristics

of QN (Figure VI-34).

Figure VI-34


________________________________________________________________________________________________________________________________________________________

In this characteristic, we show the QN curves for only the two extreme values of vI, namely, 0 and

VDD. We observe that

- The load curve represents a much lower saturation current than is represented by the

corresponding curve for QN (that for vI = VDD). This is a result of the fact that the pseudo-

NMOS inverter is usually designed so that kn is greater than kp by a factor of 4 to 10. Since the

ratio

p

n

kk

r = (68)

determines all the breakpoints of the VTC, i.e., VIH, VIL, …, and thus determines the noise

margins. Selection of a relatively high value for r reduces VOL and widens the noise margins.

- QP operates in saturation for only a small range of vo (vo ≤ Vt), For the remainder, it operates in

the triode region.

When vI is zero, QN is cut off and QP is in the triode region, though with zero current

→ Point A (Figure VI-35)

→ vo =VDD = VOH.

→ No static power dissipation.

When vI is equal to VDD

→ Point E (Figure VI-35)

→ vo = VOL (the circuit is not symmetric, which is an obvious disadvantage).

→ The static power dissipation exists with

DDstatD VIP *= (69)


________________________________________________________________________________________________________________________________________________________

The inverter characteristic is divided into four distinct regions listed in the following table:

Region Segment QN QP Condition

I AB Cut off Triode vI < Vt

II BC Saturation Triode vI - Vt ≤ vo

III CD Triode Triode Vt ≤ vo ≤ vI - Vt

IV DE Triode Saturation vo ≤ Vt

Figure VI-35


________________________________________________________________________________________________________________________________________________________

This curve was plotted for

V 1 and 9 V,5 =−=== tptnDD V VrV

Region I (segment AB) :

vo is constant

vo = VOH = VDD (70)

Region II (segment BC) :

Using equations (64) and (67) with the ratio r defined by equation (68), we obtain

( ) ( )22tItDDto VvrVVVv −−−+= (71)

The value of VIL can be obtained by differentiating this equation and substituting

ILII

o Vvvv

=−=∂∂

and 1 (72)

as

( )1+

−+=

rrVV

VV tDDtIL (73)

The threshold voltage VM is by definition the value of vI for which vo = vI,

1+

−+=

rVV

VV tDDtM (74)

Finally, the end of the region II, point C, can be found by substituting the value of vo (vo = vI - Vt) in

equation (71).

Region III (segment CD) :

This short segment has no great interest. Point D is characterized by vo = Vt.


________________________________________________________________________________________________________________________________________________________

Region IV (segment DE) :

Using equations (65) and (66) gives

( ) ( ) ( )22 1tDDtItIo VV

rVvVvv −−−−−= (75)

The value of VIH can be found by differentiating this equation and setting the derivative equal to -1 :

( )r

VVVV tDD

tIH 32 −

+= (76)

The value of VOL can be obtained by substituting vI = VDD in equation (75)

( )

−−−=

rVVv tDDOL

111 (77)

The static current Istat conducted by the inverter in the low-output state is found from equation (65)

( )2

21

tDDpstat VVkI −= (78)

Finally, NML and NMH are determined as follow:

NML: use equations (73) and (77)

( )( )

+−−−−−=

11111rrr

VVVNM tDDtL (79)

NMH : use equations (70) and (76) :

( )

−−=

rVVNM tDDH 3

21 (80)

When the inverter is loaded by a capacitance C, the times are obtained by

DDpPLH Vk

Ct 7.1= (81)


________________________________________________________________________________________________________________________________________________________

where we assume that Vt = 0.2 VDD for vo value over the range 0 to 0.2VDD, and

DDn

PHL

Vr

k

Ct

−

=46.01

7.1 (82)

Note : The ratio r determines all the breakpoints. The larger the value of r, the lower VOL is and the

wider the noise margins are. However, a larger r increases the asymmetry in the dynamic

response and, makes the gate larger. Usually, r is selected in the range 4 to 10.

As an example, we show in Figure VI-36 a NOR gate and in Figure VI-37 a NAND gate with

pseudo-NMOS transistors.

Figure VI-36


________________________________________________________________________________________________________________________________________________________

E – PASS-TRANSISTOR LOGIC CIRCUITS

A conceptually simple approach for implementing logic functions utilizes series and parallel

combinations of switches that are controlled by input logic variables to connect the input and output

nodes (Figure VI-38). For series connections, the realized function is

ABCY = (83)

Figure VI-37

Figure VI-38Y

B C

A


________________________________________________________________________________________________________________________________________________________

For parallel connections (Figure VI-39), the realized function is

( )CBAY += (84)

Because this form of logic utilizes MOS transistors in the series path from input to output, to pass or

block signal transmission, it is known as pass-transistor logic (PTL). As mentioned, CMOS

transmission gates is also employed to implement the switches. Two possible implementations of a

switch are the one with single NMOS transistor (Figure VI-40) and with CMOS transmission gate

(Figure VI-41).

Figure VI-39YA

B

C

Figure VI-40

Figure VI-41


________________________________________________________________________________________________________________________________________________________

A basic design requirement of PTL circuits is that every node must have at all times a low-resistance

path to either ground or VDD. To appreciate this point, let us consider the circuit shown in Figure VI-42.

In this circuit, the switch S1 is used to form the AND function of its controlling variable B and the

variable A available at the output of a MOS inverter. The output of the PTL circuit is shown connected

to the input of another inverter.

If S1 is closed, B is high and the output Y is equal to A. Node Y will then be connected either to VDD

(through Q2 if A is high) or to ground (through Q1 if A is low).

If S1 is open, B is low and the node Y will now become a high-impedance node. If initially vY was

zero, it will remain so. However, if initially vY was high at VDD, this voltage will be maintained by the

charge on the parasitic capacitance C but for only a time. Thus the capacitance will be discharged and

vY diminish correspondingly.

→ In any case, the circuit can no longer be considered a static logic circuit.

The problem is solved by establishing for node Y a low-resistance path that is activated when B goes

low as shown in Figure VI-43. Here another switch S2 closes when B goes low and establishes a low-

resistance path between Y and ground.

→ We have a low-resistance path between Y and ground.

Figure VI-42


________________________________________________________________________________________________________________________________________________________

I – Operation with NMOS transistors as switches

Implementing the switches in a PTL circuit with single NMOS transistors results in a simple circuit

with small area and small node capacitances.

To illustrate, consider the circuit shown in Figure VI-44, where an NMOS transistor Q1 is used to

implement a switch connecting an input node and an output node. When the switch is closed (vc is

high), at t = 0, the output voltage vo is initially zero and the capacitance is fully discharged.

When vI is high, the transistor operates in the saturation mode and delivers a current iD to charge C

( ) ( )22'

21

21

toDDntoDDn

nD VvVkVvVL

Wki −−=−−

= (85)

Figure VI-43

Figure VI-44


________________________________________________________________________________________________________________________________________________________

Vt is determined by the body effect (using equation (16) of chapter V) since the source is at a voltage

vo relative to the body

( )ffotot vVV φφγ 22 −−+= (86)

where φf is a physical parameter (2φf ≈ 0.6V) and Vto is the threshold voltage for VSB = 0. γ is a

parameter related to the fabrication process.

Thus initially, at t = 0, Vt is equal to Vto and the current iD is relatively large. However, as C charges

up and vo rises, Vt increases and iD decreases (equation (85)). It follows that the process of charging the

capacitor will be relatively slow.

The current reduces to zero when vo = VD - Vt. Thus

→ VOH < VDD

We refer to a « poor 1 ». This effect can cause QP of the load inverter to conduct. The inverter will

have a finite static current and static power dissipation. Moreover, the propagation delay tPLH can be

determined for vo = VDD/2.

When vI is low (Figure VI-45), the transistor is in saturation and

( ) ( )22'

21

21

tDDntDDn

nD VVkVVL

Wki −=−

= (87)

As C discharges, the transistor enters the triode region vo = VD - Vt. Thus VOL = 0: The NMOS

provides a « good 0 ». Again, the delay tPHL is determined for vo = VDD/2.

Figure VI-45


________________________________________________________________________________________________________________________________________________________

II – Use of CMOS transmission gates as switches

We use the transmission gate as a switch.

When vI is high (Figure VI-46), i.e., when the switch is in the « on » position, we assume that at

t = 0 the output is zero. QN will be operating in saturation and providing a charging current

( ) ( )22'

21

21

tnoDDntnoDDn

nDN VvVkVvVL

Wki −−=−−

= (88)

where

( )ffototn vVV φφγ 22 −−+= (89)

QN will conduct a diminishing current that reduces to zero at

tnDDo VVv −= (90)

However, that QP operates with VSG = VDD and is initially in saturation

( ) ( )22'

21

21

tpDDptpDDp

pDP VVkVVL

Wki −=−

= (91)

Since the substrate of QP is connected to VDD, |Vtp| remains constant at the value Vto (assumed to be

the same value as for the n-channel device).

→ The total capacitor charging current is the sum of iDN and iDP.

Figure VI-46


________________________________________________________________________________________________________________________________________________________

When QP will enter the triode region at vo = |Vtp|, it will continue to conduct until C is fully

charged and vo = VOH = VDD. Thus, the p-channel device will provide the gate with a « good 1 ».

When vI goes low (Figure VI-47), QN and QP interchange roles. QP will cease conduction when vo

falls to |Vtp| given by

( )ffoDDtotp vVVV φφγ 22 −+−+= (92)

However, QN will continue to conduct until C is fully discharged and vo = VOL = 0. Thus providing

a « good 0 ».

→ Transmission gates provide far superior performance.

III – Pass-transistor logic circuit examples

Figure VI-48 shows a PTL realization of a two-to-one multiplexer. Based on the logic value of C,

either A or B is connected to the output Y, we obtain the Boolean function

BCCAY += (93)

Another example is an efficient realization of the exclusive-OR (XOR) function. The circuit, shown

in Figure VI-49, utilizes four transistors in the transmission gates and another four for the two inverters

needed to generate the complements A and B , for a total of eight transistors.

Figure VI-47


________________________________________________________________________________________________________________________________________________________

This should be compared to the twelve transistors needed in the realization with complementary

CMOS to have the same function

BABAY += (94)

Figure VI-49

Figure VI-48


________________________________________________________________________________________________________________________________________________________

A last example is the circuit shown in Figure VI-50 that uses NMOS switches with low or zero

threshold. Both the input variables and their complements are employed and that the circuit generates

both the Boolean function and its complement. Thus this circuit is known as CPL (Complementary

Pass-transistor Logic). The circuit consists of two identical networks of pass transistors with the

corresponding transistor gates controlled by the same signal (B and B ). The inputs of the PTL are

complemented: A and B for the first network, and A and B for the second network. The circuit shown

realizes both the AND and NAND functions.

F – DYNAMIC LOGIC CIRCUITS

The logic circuits we have studied thus far are of the static type. In a static logic circuit, every node

has all times a low-resistance path to VDD or ground. Static circuits do not need clocks (i.e., periodic

timing signals) for their operation although clocks may be present for other purposes.

In contrast, the dynamic logic circuits rely on the storage of signal voltages on parasitic capacitances

at certain circuit nodes. Since charge will leak with time, the circuits need to be periodically refreshed,

and thus the presence of a clock with a certain specified minimum frequency is essential.

To place dynamic logic-circuit techniques into perspective, we have to recall that :

- Complementary CMOS excels in nearly every performance category: it is easy to design, has the

maximum possible logic swing, is robust from a noise-immunity standpoint, dissipates no static

power, and can be designed to provide equal low-to-high and high-to-low propagation delays.

Figure VI-50


________________________________________________________________________________________________________________________________________________________

Its main disadvantage is the requirement of two transistors for each additional gate input, which

increases the total capacitance and correspondingly the propagation delay and the dynamic

power dissipation.

- Pseudo-NMOS reduces the number of required transistors at the expense of static power

dissipation.

- Pass-transistor logic can result in simple, small area circuits but is limited to special applications

and requires the use of complementary inverters to restore signal levels, especially when the

switches are simple NMOS transistors.

The dynamic logic techniques studied in the next section maintain the low device count of pseudo-

NMOS while reducing the static power dissipation to zero. But this will be achieved at the expense of

more complex and less robust design.

I – Basic principles

Figure VI-51 shows the basic dynamic logic gate. It consists of a pull-down network (PDN) that

realizes the logic function in exactly the same way as the PDN of a complementary CMOS gate or a

pseudo-NMOS gate. However, we have here two switches in series that are periodically operated by

the clock signal φ whose waveform is shown in Figure VI-52.

When φ is low, QP is turned on and the circuit is said to be in the setup or precharge phase. QP

charges capacitance CL so that at the end of the precharge interval the voltage at Y is equal to VDD.

Also, the inputs A, B and C are allowed to change and settle to their proper values. Observe that

because QE is off, no path to ground exists.

When φ is high, Qp is off and QE turns on, and the circuit is in the evaluation phase. Now, if the

input combination is one that corresponds to a high output, the PDN does not conduct and the output

remains high at VDD. Thus VOH = VDD. Observe that no low-to-high propagation delay is required,

thus tPLH = 0.

On the other hand, if the combination of inputs is one that corresponds to a low output, the

appropriate NMOS transistors in the PDN will conduct and establish a path between the output node

and ground through the on transistor QE. Thus CL will be discharged through the PDN, and the voltage

at the output node will reduce to VOL = 0.


________________________________________________________________________________________________________________________________________________________

The high-to-low propagation delay tPHL can be calculated in exactly the same way as for a

complementary CMOS circuit expect that here we have an additional transistor in the series path to

ground.

As an example, we show in Figure VI-53 the circuit that realizes the function

CBAY += (95)

Figure VI-51

Figure VI-52


________________________________________________________________________________________________________________________________________________________

II – Non ideal effects

1 – Noise margins

Various sources of non ideal operation of dynamic logic circuits have to be considered. Since during

the evaluation phase the NMOS transistors begin to conduct for vI = Vtn,

tnIHIL VVV ≈≈ (96)

Thus

tnL VNM = (97)and

tnDDH VVNM −= (98)

The noise margins are far from equal.

2 – Output voltage decay

In the absence of a path to ground through the PDN, the output voltage will ideally remain high at

VDD. This, however, is based on the assumption that the charge on CL will remain intact. In practice,

there will be leakage current that will cause CL to slowly discharge and vY to decay.

Figure VI-53


________________________________________________________________________________________________________________________________________________________

Thus the circuit can malfunction if the clock is operating at a very low frequency and the output

node is not “refreshed” periodically.

3 – Charge sharing

There is another and often more serious way for CL to lose some of its charge and thus cause vY to

fall significantly below VDD. To see how this can happen, refer to Figure VI-54 which shows only the

two top transistors Q1 and Q2 of the PDN together with the precharge transistor QP.

Here, C1 is the capacitance between the common node of Q1 and Q2 and ground. The figure shows

the situation at the beginning of the evaluation phase after Qp has turned off and with CL charged to

VDD. In this particular situation, we assume that C1 is initially discharged and that the inputs are such

that at the gate of Q1 we have a high signal, whereas at the gate of Q2 the signal is low.

We can see that Q1 will turn on, and its drain current iD1 will flow as indicated. Thus this current will

discharge CL and charge C1. Although eventually this current will reduce to zero, CL will have lost

some of its charge, which will be transferred to C1. This is the charge sharing phenomenon.

In order to minimize this effect, one approach involves adding a p-channel device that continuously

conducts a small current to replenish the charge lost by CL (Figure VI-55).

Figure VI-54


________________________________________________________________________________________________________________________________________________________

4 – Cascading dynamic logic gates

Consider the circuit in Figure VI-56 where two single input dynamic gates are connected in cascade.

During the precharge phase, CL1 and CL2 will be charged through QP1 and QP2, respectively. Thus, at

the end of the precharge phase,

DDY Vv =1 (99)

and

DDY Vv =2 (100)

Figure VI-55


________________________________________________________________________________________________________________________________________________________

In the evaluation phase, if A is high, the output Y1 should be low (vY1 = 0) and Y2 high (vY2 = VDD).

However, as the evaluation phase begins, Q1 turns on and CL1 begins to discharge. But, simultaneously,

Q2 turns on and CL2 also begins to discharge. Only when vY1 drops below Vtn will Q2 turn off.

Unfortunately, by that time, CL2 will have list a significant amount of its charge, and vY2 will be less

than the expected value of VDD.

This problem make simple cascading an impractical proposition. In this case, Domino CMOS logic

circuits have overcome this limitation.

5 – Domino CMOS logic circuits

Domino CMOS logic circuits are a form of dynamic logic circuits that results in cascadable gates.

Figure VI-57 shows the structure of the Domino CMOS logic gate which is simply the basic dynamic

logic gate of Figure VI-51 with a static CMOS inverter. During precharge, X will be raised to VDD, and

the gate output Y will be at 0V. During evaluation, depending on the combination of input variable,

either X will remain high and thus the output Y will remain low, or X will be brought down to 0V and

the output Y will rise to VDD.

To see why Domino CMOS gates can be cascaded, consider the situation in Figure VI-58.

Figure VI-56


________________________________________________________________________________________________________________________________________________________

In this circuit, at the end of the precharge, X1 and X2 will be at VDD and Y1 and Y2 will be at 0V. As in

the previous case, if A is high at the beginning of the evaluation, thus, as φ goes up, capacitor CL1 will

begin discharging, pulling X1 down. Meanwhile, the low input at the gate of Q2 keeps the transistor off,

and CL2 remains fully charged.

When vX1 falls below the threshold voltage of inverter I1, Y1 will go up turning Q2 on, which in turn

begins to discharge CL2 and pulls X2 low (eventually, Y2 rises to VDD).

Then, we see that because the output of the domino gate is low at the beginning of evaluation, no

premature capacitor discharge will occur. As indicated in Figure VI-59, output Y1 will make a 0-to-1

Figure VI-57

Figure VI-58


________________________________________________________________________________________________________________________________________________________

transition tPLH seconds after the rising edge of the clock. Subsequently, output Y2 makes a 0-to-1

transition after another tPLH interval. The propagation resembles dominoes falling over in a cascade

manner, which is the origin of the name DOMINO CMOS logic.

G – LATCHES

The logic circuits considered thus far are called combinational (or combinatorial). Their output

depends only on the present value of the input. Thus, these circuits do not have memory. Memory is a

very important part of digital systems. Its availability in digital computers allows for storing programs

and data. Furthermore, it is important for temporary storage of the output produced by a combinational

circuit for use at a later time in the operation of a digital system.

Logic circuits that incorporate memory are called sequential circuits. That is, their output depends

not only on the present value of the input but also on the input’s previous values. Such circuits require a

timing generator (a clock) for their operation.

There is basically two approaches for providing memory to a digital circuit. The first relies on the

application of positive feedback that can be arranged to provide a circuit with two stable states: the

bistable circuit which can be used to store one bit of information. One stable state would correspond to

a stored 0, and the other to a stored 1. A bistable circuit can remain in either state indefinitely and thus

belongs to the category of static sequential circuits.

The other approach to realizing memory utilizes the storage of charge on a capacitor. When the

capacitor is charged, it would be regarded as storing a 1; when it is discharged, it would be storing a 0.

Since the inevitable leakage effects will cause the capacitor to discharge, such a form of memory

requires the periodic recharging of the capacitor, a process known as refresh. Thus, memory based on

charge storage is known as dynamic memory and the corresponding sequential circuits as dynamic

sequential circuits.

Figure VI-59


________________________________________________________________________________________________________________________________________________________

In this section, we shall study the basic memory element, the latch.

I – Latch

The basic memory element, the latch, is shown in Figure VI-60.

It consists of two cross-coupled logic inverters that form a positive-feedback loop. To investigate the

operation of the latch we break the feedback loop at the input of one of the inverters (Figure VI-61).

Assuming that the input of G1 is large, breaking the feedback loop will not change the loop voltage

transfer characteristic, which can be determined by plotting vZ-vW (Figure VI-62). This VTC consists of

three segments, with the middle segment corresponding to the transition region of the inverters.

The straight line vZ = vW is realized by reconnecting Z to W to close the feedback loop. Here, the

points A and C are stable operating points while the point B is unstable. The latch cannot operate at B

for any period of time. The reason point B is unstable can be seen by considering the circuit in Figure

VI-59 and taking account of the interference or noise that is inevitably present in any real circuit.

Figure VI-60

Figure VI-61


________________________________________________________________________________________________________________________________________________________

Let the voltage vW increase by a small increment vw. The voltage at point X will increase

significantly (product vw*G1, where G1 is the incremental gain) The resulting signal will rise to an even

larger signal at node Z vw*G1*G2. Since this point is related to the input, the regenerative process

continues, shifting the operating point from B upward to point C (If we assume a negative voltage

increment the operating point will move downward from B to A).

At point C, vW is high, vX is low, vY is low, and vZ is high. The reverse is true at point A. Thus, we

see that in one of the stable states (e.g., that corresponding to point A), a high vW gives a low output vZ

and in the other state (point C), a low input vW implies a high output. We have two stable states and

thus the latch is a bistable circuit having two complementary outputs. Moreover, the latch operates

depends on the external excitation. It memorizes this external action by staying indefinitely in the

acquired state.

II – Flip-Flop

It now remains to devise a mechanism by which the latch can be triggered to change state. The latch

together with the triggering circuitry forms a flip-flop. The simplest type of flip-flop ids the set/reset

(SR) flip-flop shown in Figure VI-63. It is formed by cross-coupling two NOR gates, and thus it

incorporates a latch. The second input of each NOR gate together serve as the trigger inputs of the flip-

flop. These two inputs are labeled S (for set) and R (for Reset). The output are labeled Q and Q

emphasizing the fact that these are complementary. The flip-flop is considered set (that is storing a

logic 1) when Q is high and Q is low.

Figure VI-62


________________________________________________________________________________________________________________________________________________________

When the flip-flop is in the other state (Q low, Q high), it is considered reset (storing a logic 0).

In the case of logic 0, Q will be low and thus both inputs to the NOR gate G2 will be low. To set the

flip0-flop we raise S to the logic-1 level while leaving R at 0. The 1 at the S terminal will force the

output of G2 to « 0 ». Thus the two inputs to G1 will be « 0 » and its output Q will go to « 1 ».

The operation of the flip-flop is summarized by the following truth table

III –CMOS implementation of SR flip-flops

The SR flip-flop can be implemented in CMOS by replacing each of the NOR gates by its CMOS

circuit realization. Specifically, Figure VI-64 shows a clocked version of an SR flip-flop.

→ This circuit works perfectly, but it is relatively complex.

A simpler circuit can be found by using pass-transistors to implement the clock circuit. This circuit

is called the data or D flip-flop (Figure VI-65).

Figure VI-63


________________________________________________________________________________________________________________________________________________________

IV – D Flip-Flop

Figure VI-66 shows a D flip-flop circuit. It has two inputs, the data input D and the clock input φ

and two outputs (Q and its complementary). When the clock is low, the flip-flop is in the memory, or

rest, state. As the clock goes high, the flip-flop acquires the logic level that exited on the D line just

before the riding edge of the clock. Such a flip-flop is said to be edge-triggered.

Figure VI-64

Figure VI-65


________________________________________________________________________________________________________________________________________________________

A simple implementation is shown in Figure VI-67. It consists of two inverters for the two

complementary phases of the clock (Figure VI-68).

When φ is high, the loop is opened, and D is connected to the input of inverter G1. The capacitance

at the input node of the inverter is charged to the value of D, and the capacitance at the input node of

G2 is charged to the value of D .

Figure VI-66

Figure VI-67

Figure VI-68


________________________________________________________________________________________________________________________________________________________

Then, when the clock goes low, the input line is isolated from the flip-flop, the feedback loop is

closed, and the latch acquires the state corresponding to the value of D just before the clock went down,

providing an output Q = D.

However, the proper operation of this circuit is based on the assumption that φ and φ must not be

simultaneously high at any time. To solve this problem, we use the master-slave configuration

(Figure VI-69) that gives the clock waveforms shown in Figure VI-70 where there is non overlapping.

Figure VI-69

Figure VI-70

elg 2135 electronics i sixth chapter: digital circuits

Documents