Session S2G 0-7803-9077-6/05/$20.00 2005 IEEEOctober 19 22, 2005, Indianapolis, IN 35th ASEE/IEEE Frontiers in Education Conference S2G-7 Digital Electronics Learning System Based on FPGA Applications Camilo Quintans, M. Dolores Valdes, M Jose Moure, Luis Fernandez-Ferreira, Enrique Mandado Instituto de Electrnica Aplicada Pedro Barri de la Maza, Universidad de Vigo (Spain) quintans@uvigo.es Abstract-FPGAs(FieldProgrammableGateArrays) constitutethebaseofmanycomplexelectronicsystems withdifferentapplicationsrangingfromtheautomotive sector to the multimedia market. Due to integrated circuits fabricationprogress,currentFPGAsincludesvery complexembeddeddigitalblocksasserialtransceiversor memoryblocks.ThereforeFPGAfundamentalsand characteristicsarenoteasytoexplainconsideringthat therearealsoalotofdevicesandfamiliesfromdifferent manufacturers.Bythisreason,FPGAlearningisusually basedondescribingafamilyanddoesntgiveageneral view of the wide range of commercial devices. Due to that itisessentialfortheelectroniclearningcommunityto disposeoftoolsfacilitatingthelearningprocessofthe FPGAfundamentalsandthedesignofsystemsbasedon them.Thelearningsystemcombinesatutorialwith hardware and software tools to achieve a friendly interface withacomputerintendedtofacilitateFPGAdistance learningforstudentswithabasicknowledgeofdigital electronics and VHDL. Index Terms - FPGA, distance learning, software, hardware. INTRODUCTION Figure1showstheblockdiagramofthesystem,includinga hypermediatutorialandhardwareandsoftwaretoolsrelated bymeansofasetofpracticalexamples.Thehardwaretools are:A main board with a FPGA and a USB2.0 driver [1]. Anexpansioncardincludingspecificperipheraldevices (analog to digital and digital to analogue converters, LCD display, keyboard, etc.). The software tools are:ThemainboardcontrolsoftwarefortheFPGA configurationandthecommunicationchannel implementation. TheAlterasQuartusIIWebEditiontoolfordescribing andsynthesizingcircuitsusingaschematiccapturetool and a VHDL language compiler. Thetutorialisahypermediaapplicationrunningona personalcomputer.Itdrivesthestudentfromthedifferent FPGAbasicconceptstoactualFPGAdigitalsystemdesign. Thesetofpracticalexamplesincludedinthehypermedia tutorialareorientedtotheAPEXfamilycircuitsandtools fromAlterabuttheirfunctionalityisgenerallyenoughtobe used with devices of different manufacturers. USB2.0 USB2.0USB2 USB2- -FPGA FPGADevelopment system Development systemDevelopment boardUSBControllerFPGAExpansionCards. .. .. .Tutorial TutorialControl Panel Control PanelDesignvSoftware DesignvSoftwareUSB2.0 USB2.0USB2 USB2- -FPGA FPGADevelopment system Development systemDevelopment boardUSBControllerFPGAExpansionCards. .. .. .. .. .. .. .. .. .Tutorial TutorialControl Panel Control PanelDesignvSoftware DesignvSoftware FIGURE 1 BLOCK DIAGRAM OF THE FPGA LEARNING SYSTEM. HYPERMEDIA TUTORIAL DuetothefactthatFPGAconstituteacomplextechnology [2],thehypermediasystemhasbeendoneusingthemethod developedbytheInstitutodeElectrnicaAplicadaofthe UniversityofVigo[3]toobtainthedescriptivemodelofa complextechnology.Figure2showsthismethodcomprising four main stages: Firstly,manydifferentrepresentativesystemsordevices are chosen.Inthesecondstagetheselectedsystemsareanalyzedin detail to define the concepts associated to the technology. This task is carried out in two different phases. In the first phaseallthecommoncharacteristicsaredeterminedand classifiedtodefinethegeneralcharacteristicsorbasic concepts of the complex technology. In the second phase thebasicconceptsarecharacterized(including functionality,implementation,architecture,etc.)taking into account the specific characteristics of each particular systeminsuchawaythatthesubconceptsofthe descriptivemodelareobtainedaswellasitsdependence relations. The same subconcept can be present in different systemsbutthesetofsubconceptsassociatedtoeach system can be different. Inthethirdstageallthebasicconceptsandsubconcepts are structured to obtain the descriptive model.Finally, the descriptive model must be tested to verify its abilitytodescribenotonlythesystemschosentoobtain the model but, all the commercial systems known. Developing descriptive models is a tedious task requiring a lot of time and effort, nevertheless the result is a very useful toolfortheanalysisofcomplextechnologiesaswellasthe particularsystemsincludedinthem.Besides,ifnewsystems aredeveloped,updatingthemodelwiththeinclusionofnew characteristics is very easy. Session S2G 0-7803-9077-6/05/$20.00 2005 IEEEOctober 19 22, 2005, Indianapolis, IN 35th ASEE/IEEE Frontiers in Education Conference S2G-8 Once the descriptivemodel is obtained, it is necessary to useagraphicalrepresentationofit.Sowestudiedthe applicationofconceptualmapsbeingusedatpresentonlyto describe general human knowledge areas [4][5][6][7]. Figure3showsthedevelopedFPGAsconceptualmap. The concepts are interrelated and due to that it is interesting to describethemapwith hypermediausingthemapconceptsas keywordstoachieveanonsequentialaccesstothe information.Everyconceptisexplainedusingwebpages combinedwithabrowsertoimplementthehypermedia system.Everyconceptisdescribedusingtext,pictures,diagrams and videos. The user can navigate through the lessons using a friendly interface [8]. To simplify navigation, every lesson has linkages with a glossary, including a multimedia definition of thedifferentconcepts.Theinterfaceincludesabuttonto experimentwhichisactiveinthosepagescombiningtheory with the development board described next. FIGURE 2 COMPLEX TECHNOLOGIES CHARACTERIZING METHODOLOGY FPGAs circuitsConfigurablelogic blocksInterconnectionresourcesConfigurableconnectionsAre composed byOrganizationTypes oflogic blocksConfigurableconnectionstechnologyIncluded conceptsTerracedFPGAsManhattanFPGAsSea gatesFPGAsgeneratesSimple orhomogeneusFPGAsComplex orheterogeneusFPGAsFusetechnologyFPGAsPassivememorytechnologyFPGAsActive memory(SRAM)technologyFPGAsgeneratesAntifusetechnologyFPGAsEPROMFPGAsOTP FPGAsFLASHFPGAsE2PROMFPGAsCan beCan beUltravioletlighterasableFPGAsElectricallyerasableFPGAsMaskprogrammableFPGAsProgrammingand erasingmodegenerates FIGURE 3 CONCEPTUAL MAP OF FPGA CIRCUITS USB2: FPGA DEVELOPMENT SYSTEM I. Hardware Description ActualFPGA developmentsystemsdonot havea highspeed communicationchannelfordatatransferbetweentheFPGA and the computer. To overcome this limitation, the authors of thispaperdevelopedtheUSB2-FPGAboardwiththe following features: AcommunicationchannelbasedontheUSB2bus: Thischannelcanbeusedfortheconfigurationofthe FPGA as well as to support a high speed general purpose communicationchannelbetweentheUSB2-FPGAboard and the PC. In comparison to other hardware platforms it reducestheconfigurationtimeprovidingahighspeed channelsupporttocommunicatetheconfigurabledevice with the PC. The control of the bidirectional data transfer isimplementedintheFPGAbutsuchasystemisvery simple and consumes just a few logic resources. Theinput/outputpinsoftheFPGAareaccessible:In order to facilitate the connection of peripherals required in differentapplicationsalltheinput/outputpinsofthe FPGA can be accessed through standard connectors. Session S2G 0-7803-9077-6/05/$20.00 2005 IEEEOctober 19 22, 2005, Indianapolis, IN 35th ASEE/IEEE Frontiers in Education Conference S2G-9 Figures4and5showaphotoandaschematicofthe developed board. The main parts are: The FPGA APEX EP20K100EQC240-2X from Altera. The USB2.0 controller from Cypress.TheEEPROMEPC2LC20fromAlterafor thestorageof the configuration file. A+5VDCvoltagesourcecomingfromanexternal AC/DCadaptororfromtheUSBconnection.1,8Vand 3,3VDCvoltagescanbeobtainedfromthe+5VDC voltage source.Configurationmodeselector.Theboardsupportsthree configurationmodes:fromthePCthroughtheUSB channel, from the PC through the JTAG interface (passive serial mode) and from an EEPROM memory.A USB connector. A JTAG connector. Three64pinsconnectorstoaccessalltheinput/output pinsoftheFPGA.Differentexpansioncardscontaining specific peripheral devices can be connected to the FPGA through the connectors. FIGURE 4 THE USB2-FPGA DEVELOPMENT BOARD USB ControllerUSBSIEUSBPort BPort DPort CCParallel BusControlPort AFPGACommunicationController (IP)UserApplication.rbf .exeUserExpansion Cards...USB2-FPGA Development KitDataPSE2PROMJTAGPPUSB ControllerUSBSIEUSBPort BPort DPort CCParallel BusControlPort AFPGACommunicationController (IP)UserApplication.rbf .exeUserExpansion Cards......USB2-FPGA Development KitDataPSE2PROMJTAGPP FIGURE 5 BLOCK DIAGRAM OF THE USB2-FPGA DEVELOPMENT BOARD II. Software Description AprogramnamedUSB2-FPGAControlPanelhasbeen developedtosupporttheUSB2-FPGAboardconfiguration and communication. As can be observed in Figure 6 the main functionsoftheprogramaretheFPGAconfigurationor programming. The supervising of the data transfer between the FPGA and the PC is shown in Figure 7. FIGURE 6 USB2-FPGA CONTROL PANEL: PROGRAMMING MODE FIGURE 7 USB2-FPGA CONTROL PANEL: COMMUNICATION MODE FPGA configuration timing is an important parameter for applicationswheretheFPGAmustbereconfiguredmany times. The programmer included in the USB2-FPGA Control Panelshowsasignificantreductionoftheprogramming timing.Inordertoverifyitsperformanceacomparisonwith theAlteraQuartusIIprogrammerwasmade.Thetest conditionsandtheresultsdemonstratethesuperiority(in termsofprogrammingtime)ofthedevelopedsystem.These results are included in Table 1. Session S2G 0-7803-9077-6/05/$20.00 2005 IEEEOctober 19 22, 2005, Indianapolis, IN 35th ASEE/IEEE Frontiers in Education Conference S2G-10 TABLE I PERFORMANCE COMPARISON BETWEEN PROGRAMMERSTest conditionsQuartus II:USB2.0-FPGA Windows XP Pentium IV 2.40GHz. RAM: 256 MB DDR FPGA Device:APEX20K100EQC240-2X BYTEBLASTERMV : FILE FORMAT: *.SOF SIZE: 121 KB TIMING-> 4.1 SEG. CONTROL PANEL: FILE FORMAT : *.RBF SIZE: 123 KB TIMING-> 1.31 SEG. In the communication mode (Figure 7b) the USB2-FPGA ControlPanel verifiesthe datatransferbetweenthecomputer and the FPGA and supervises the transfer rate and the state of theFIFOmemories(insidetheUSBcontroller)that temporally store the received and sent data.To use the USB2-FPGA development system the channel communication between the computer and the FPGA must be establishandtheFPGAmustbeprogrammed.Figure8 describes this process including the following stages:The PC initializes the USB controller through the USB2.0 channel. The PC configures the SIE unit of the USB controller and its internal microcontroller takes the control. The SIE unit includestheFIFOmemoriessupportingthetemporal storage of the transferred data. TheinternalmicrocontrolleroftheUSBcontroller programstheFPGAtransferringtheconfigurationfile fromthePCtothedevicethroughtheSIEunitandthe JTAG interface. TheUSBcontrollergivesthecontroloftheSIEunitto theFPGAandthecommunicationbetweentheuser application and the PC is established. USB controllerUSB controller initialization initializationBegin BeginConfiguration of theConfiguration of the SIE unit SIE unitThe USB controllerThe USB controller takes the control oftakes the control of the SIE unit the SIE unitFPGA configuration FPGA configurationThe communicationThe communication channel is established channel is establishedThe USB controller givesThe USB controller gives the control to the FPGAthe control to the FPGA End EndYes YesNo NoFPGAreconfiguration? FPGA FPGAreconfiguration reconfiguration? ?USB controllerUSB controller initialization initializationBegin BeginConfiguration of theConfiguration of the SIE unit SIE unitThe USB controllerThe USB controller takes the control oftakes the control of the SIE unit the SIE unitFPGA configuration FPGA configurationThe communicationThe communication channel is established channel is establishedThe USB controller givesThe USB controller gives the control to the FPGAthe control to the FPGA End EndYes YesNo NoFPGAreconfiguration? FPGA FPGAreconfiguration reconfiguration? ? FIGURE 8 FPGA COMMUNICATION CONFIGURATION DIAGRAM FPGA APPLICATIONS SELF-LEARNING LABORATORY The USB2-FPGA development system can be considered as a self-learninglaboratoryintendedforFPGAapplicationsby meansoftheresolutionofpracticalexercisesofincreasing complexity. It is supposed that the user knows the basic digital blocks(logicgates,flip-flops,multiplexers,decoders, counters,memories,etc.)aswellasthebasisoftheVHDL hardware description language. Inthiswaythedevelopmentsystemhasthefollowing objectives: MakeeasythelearningofFPGAbasedsystemsdesign methods.ApplythedesignmethodsusingtheQuartusIIWeb Edition design tools from Altera. Improve the VHDL design skills. Asetofpracticalexerciseshasbeendevelopedwiththe before objectives. Simple digital systems of the first exercises are part of the more complex systems of the final exercises.Exercise 1: Digital control system of a 4x4 keyboard. Exercise 2: Digital interface of a PS2 keyboard. Exercise 3: Digital control system of a LCD display. Exercise 4: LIFO and FIFO memories. Exercise 5: Basic calculator using the systems of exercise 2 and 3. Exercise 6: Manchester serial transceiver with CRC. Exercise7:ControlsystemofaPWManalogtodigital converter. Exercise8:Digitalcontrolsystemofasuccessive approximation analog to digital converter. Exercise9:Homealarmemulatorusingthesystemsof exercises 2, 3, 6, 7 and 8. Exercise10:FIRfilterusingthesystemsofexercises7 and 8. ThedesignprocessofFPGAbasedsystems(Figure9) includesthemainstagesreferrednext.IntheUSB2-FPGA development system most of the design stages use the Quartus II Web Edition design tools from Altera.Description:Thesystembehavioror/andstructureis/are definedfromthedesignspecifications.Schematicsare usedtodescribethesystemstructureandhardware description languages, like VHDL or Verilog, are used for thebehavioraldescription.Usuallyajointdescription combiningbothstructuralandbehavioralonesisusedto define a specific system.Compilation:Duringcompilationanetlistcontainingall thesystemcomponentsandtheirinterconnectionsis obtained,therightconnectionofthecomponentsis verifiedandpossiblesyntaxerrorsaredetected. Optionally,thenetlistcanbeoptimizedinorderto improvethelogicandinterconnectionresourcesusage. Theresultantnetlistisusedfortheimplementationand verification stages. Session S2G 0-7803-9077-6/05/$20.00 2005 IEEEOctober 19 22, 2005, Indianapolis, IN 35th ASEE/IEEE Frontiers in Education Conference S2G-11 IMPLEMENTACINIMPLEMENTACINCONFIGURACINCONFIGURACINCOMPILACINCOMPILACINESPECIFICACIONESESPECIFICACIONESSILenguaje de descripcinde sistemas digitales (HDL)MinimizacinGeneracin de lalista de conexionesInformacin de la jerarquaOptimizacin de lalista de conexionesComprobacin de erroresAsignacin de recursos, posicionamiento yenrutadoEleccin del dispositivoActualizacin de lalista de conexionesConfiguracin de la FPGAVerificacin de la FPGAFINALFINALResultadosprevistosVectores de pruebaSimulacin funcionalResultadosprevistosNOSI NODESCRIPCINOpciones de compilacinOpciones de implementacinVERIFICACINGeneracin del ficherode configuracinSimulacintemporalEsquemaAnlisisestticotemporalVectores de pruebaIMPLEMENTACINIMPLEMENTATIONCONFIGURACINPROGRAMMINGCOMPILACINCOMPILATIONESPECIFICACIONESSPECIFICATIONSYESHardware Description Language (HDL)MinimizeNetlist generationHierarchy informationNetlist optimizationErrors checkingMapping, Fitting,Place&RouteDevice choiceNetlist updateFPGA programmingFPGA verificationFINALEndExpectedresultsTest vectorsFunctional simulationExpectedresultsNOYES NODESCRIPTIONCompilation optionsImplementation optionsVERIFICATIONProgramming filegenerationTimingsimulationSchematicTiming orstaticanalysisTest vectorsIMPLEMENTACINIMPLEMENTACINCONFIGURACINCONFIGURACINCOMPILACINCOMPILACINESPECIFICACIONESESPECIFICACIONESSILenguaje de descripcinde sistemas digitales (HDL)MinimizacinGeneracin de lalista de conexionesInformacin de la jerarquaOptimizacin de lalista de conexionesComprobacin de erroresAsignacin de recursos, posicionamiento yenrutadoEleccin del dispositivoActualizacin de lalista de conexionesConfiguracin de la FPGAVerificacin de la FPGAFINALFINALResultadosprevistosVectores de pruebaSimulacin funcionalResultadosprevistosNOSI NODESCRIPCINOpciones de compilacinOpciones de implementacinVERIFICACINGeneracin del ficherode configuracinSimulacintemporalEsquemaAnlisisestticotemporalVectores de pruebaIMPLEMENTACINIMPLEMENTATIONCONFIGURACINPROGRAMMINGCOMPILACINCOMPILATIONESPECIFICACIONESSPECIFICATIONSYESHardware Description Language (HDL)MinimizeNetlist generationHierarchy informationNetlist optimizationErrors checkingMapping, Fitting,Place&RouteDevice choiceNetlist updateFPGA programmingFPGA verificationFINALEndExpectedresultsTest vectorsFunctional simulationExpectedresultsNOYES NODESCRIPTIONCompilation optionsImplementation optionsVERIFICATIONProgramming filegenerationTimingsimulationSchematicTiming orstaticanalysisTest vectors FIGURE 9 DESIGN PROCESS OF FPGA-BASED SYSTEMS Implementation:InthisstageFPGAlogicresourcesare assignedtothedifferentelementsofthenetlist(mapping process),placedandinterconnected(place&route processorfittingprocess).Besides,theFPGA programmingfileisgeneratedandanewnetlist containingthedelayofallsignalsisobtained.Usingthe updatednetlistatimingsimulationoratiminganalysis can be accomplish in order to verify the right operation of thedesignedsystem.Ifverificationresultsarethe expectedonestheFPGAcanbeprogrammedandthe design is finished.Verification:Thisstagecanbedividedintothree differentprocesses:functionalsimulation,timing simulationandtiminganalysis.Bymeansoffunctional simulationthesystembehaviorcanbeverifiedwithout anytimingconsideration.Whengoodresultsarereached the system can be implemented and if not the description mustbemodified.Timingsimulationandanalysistake placeaftertheimplementation.Ifthesystemdoesnot workproperlydue,forexample,toexcessivesignal delays,theimplementation/compilationoptionsmustbe changed in previous stages. Programming:TheFPGAisprogrammedusingthe USB2-FPGA Control Panel tool. I. Virtual Logic Analyzer Besides the hardware and software resources described above, a virtual logic analyzer intended to verify the designed system behavior have been developed. The logic analyzer combines a hardwaresupportandasoftwarehumanmachineinterface (HMI) that runs in the PC.ThehardwaresupportisimplementedintheFPGA.Itis made up of the analyzer input pins (data acquisition channels), adataacquisitionmemoryandthecommunicationprocessor thattakechargeoftheacquireddatatransferfromtheFPGA to the PC through the USB2.0 connection. This hardware is a module of a design library and must be included in the system thatisbeingdesignedduringthedescriptionstage.It consumesfewlogicandinterconnectionresourcesanddoes notinhibittheimplementationoftheproposedpractical exercises. Tousethelogicanalyzertheacquisitionchannels(input pinsofthelogicanalyzer)mustbeconnectedtothedesired nodesoftheimplementedsystem.Thenodescanbeexternal Session S2G 0-7803-9077-6/05/$20.00 2005 IEEEOctober 19 22, 2005, Indianapolis, IN 35th ASEE/IEEE Frontiers in Education Conference S2G-12 (FPGAoutputpins)orinternalsignals.Inthefirstcasethe outputsignalsofthedesignedsystemmustbewiredtothe input channels of the analyzer, just like an external instrument. Inthecaseofinternalnodeverificationconnectionsmustbe definedduringthedescriptionstage.Thistypeofverification can not be achieved with an external measurement system. Figure10showsthelogicanalyzerhumanmachine interface(HMI).ItisaVisualC++applicationforWindows, combiningagraphiceditor,whereacquiredsignalsare represented,withacontrolpaneltoconfigurethelogic analyzer operation modes. FIGURE 10 LOGIC ANALYZER HUMAN MACHINE INTERFACE CONCLUSIONS The main characteristics of the system are: Itprovidesanefficientlearningmethodcombininga multimediatutorialsystemwithhardwaretoachievenot only a theoretical education but a practical training with a good cost/performance relation. Itisappropriatetoachieveasynchronousdistance learningduetothelowcostofthedevelopmentboard components and the free available software. Thesystemconfigurabilityincludingahighnumberof input/output pins. The diversity of internal and external resources providing a high flexibility. TheUSB2.0interfaceprovidingaveryfast communication channel between the board and the PC. Thevirtuallogicanalyzertotestinternalandexternal nodes of the designed system. ACKNOWLEDGMENT This work has been funded by Xunta de Galicia (Spain). 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[8]Alessi S.M., Trollip S.R.: Multimedia for learning, Alling and Bacon, Massachusetts, 3 ed., 2000