glitch reduction

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Glitch Analysis and Reduction in Register Transfer Level Power Optimization

Anand Raghunathan

Department of EEPrinceton UniversityPrinceton, NJ 08544

Sujit Dey

C&C Research LabsNEC USA, Inc.Princeton, NJ 08540

Niraj K. Jha y

Department of EEPrinceton UniversityPrinceton, NJ 08544

ABSTRACT: We presentdesign-for-low-powertechniques based

on glitch reduction for register-transferlevel circuits. We analyze

the generation and propagation of glitches in both the control

and data path parts of the circuit. Based on the analysis, we

develop techniques that attempt to reduce glitching power con-

sumption by minimizing generation and propagation of glitches

in the RTL circuit. Our techniques include restructuring multi-

plexer networks (to enhance data correlations, eliminate glitchy

control signals, and reduce glitches on data signals), clocking

control signals, and inserting selective rising/falling delays. Our

techniques are suited to control-flow intensive designs, where

glitches generated at control signals have a significant impact on

the circuits power consumption, and multiplexers and registers

often account for a major portion of the total power. Application

of the proposed techniques to several examples shows significant

power savings, with negligible area and delay overheads.

I. Introduction

Most savings in power consumption can be obtained through acombination of various techniques at different levels of the designhierarchy. We focus on techniques to reduce average power con-sumption in register-transfer level (RTL) circuits. Power estimationtechniques for RTL designs, and high-level synthesis techniques forreducing powerconsumptionhavebeenpreviouslyinvestigated [1, 2].

Several studies have reported the importance of considering glitchingpower during power estimation and optimization [3, 4]. However,very few automated design and synthesis techniques exist for reduc-ing glitching power consumption. At the architecture and behaviorlevels, previous work on power estimation and optimization ignoresthe effects of glitch generation and propagation across the bound-aries of blocks in the architecture. While accurate library modelingapproaches can be used to account for the effect of glitches withinarchitectural blocks, they typically assume that inputs to these blocksare glitch-free. Most previous work at the architecture and behaviorlevels has also sought to focus on data-flow intensive designs, wherearithmetic units like adders and multipliers account for most of thetotal power consumption. However, our experiments with control-flow intensive designs reveal that functional units may constitute amuch smaller fraction of total power than multiplexer networks andregisters.

In this paper,we analyzethe generationand propagationof glitchesin both the control and data path parts of the circuit, and proposetechniques to reduce glitch power consumption. In order to minimizethe generation and propagation of glitches from control as well asdata signals, we propose several techniques including restructuringmultiplexer networks, clocking control signals, and insertingselectiverising/falling delays. These techniques do not rely upon the existence

Supported by NEC C&C Research Labsy Supported by NSF under Grant No. MIP-9319269.

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OUTPUT

X Y

XIN XY YIN

ZERO

C20

C20

contr[0] = x1 + x3

contr[1] = x0

contr[2] = x0 + x1.c11 + x3.c10

contr[3] = x0 + x1.c11

contr[4] = x0 + x1.c11 + x3.c10

contr[5] = x1.c11.c15 + x2.c15 + x3.c10.c15

contr[6] = x0 + x4

contr[7] = x1.c11 + x2 + x3.c10

contr[8] = x1.c11.c15 + x2.c15 + x3.c10.c15

contr[9] = x0 + x1.c11.c15 + x2.c15 + x3.c10.c15 + x4

c11 = c9 + c10


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decode logic (see Figure 1) are fed by the outputs of comparatorsand the state flip-flops of the controller. The previous subsectionhas already demonstrated that outputs of comparators can be glitchy.The glitches at comparator outputs can propagate through the decodelogic andcause glitches on thecontrol signals. In addition, the decodelogic can itself generate a lot of glitches, as shown next. Let us focuson control signal contr[2] in the GCD RTL circuit, which is highly

glitchy according to thestatisticsofTable 2. Theportion of thedecodelogic that implements this control signal is shown in Figure 4(a).We observe that though the inputs are nearly glitch-free, significantglitches are generated at AND gates G 1 and G 2. After careful analysis,

x 0

x 1

c 1 1

x 3

c 1 0

contr[2]

22/22

22.5/22.5

/5049.5

/50.5 49.5

49.5/19.5

22.5/2.5

72/20G1

G2

54/53.5

G1G3

(a) (b)

Figure 4: (a) Implementation of control signal contr[2], and (b)

generation of glitches at gate G 1

the generation of glitches atG

1 was attributed to two conditions that

are depicted graphically in Figure 4(b):

C1: A rising transition on signal x 1 was frequently accompaniedbya falling transition on c 11. Thus, the rising transition on x 1 andthe falling transition on c 11 are highly correlated.

C2: Transitions on signal x 1 arrive earlier than transitions on c 11.

Condition C1 arises due to the functionality of the design: most of thetimes when state s 1 is entered (rising transition on x 1), comparatorsfeeding c 9 and c 10 produce a 0, changing from 1 in the previous state.On the other hand, condition C2 is a result of the delay/temporalcharacteristics of the design. A similar explanation holds for theoutput of gate

G

2 being glitchy. Generation of glitches in the controllogic has been described in detail in [7].

IV. Glitch Reduction Techniques

In this section, we describe our techniques for reducing glitchpower consumption in RTL circuits, by minimizing the generationand propagation of glitches through different blocks of the circuit.

A. Reducing glitch propagation from control signals

As shown before, control signals to the data path can be veryglitchy. Ouraim is tostop glitcheson controlsignalsfrom propagatingas close to their source as possible in order to reap the maximum ben-efits in terms of power savings. We illustrate each of our techniquesseparately through examples in this subsection, and later integratethese techniques into a single power optimization framework.

Y

glitch reduction

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