how to clock your computer: digital logic design 1/3 · 2021. 2. 15. · • flip-flop and clock...
TRANSCRIPT
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How to Clock Your Computer:Digital Logic Design 1/3Moti Medina
Slides, slides material, and figures are taken from “Digital Logic Design : a rigorous approach” lecture
slides and book by Guy Even and M (Chapters: 10, 11, 12, 14). 1
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Our Journey: From Transistors to Computers
Transistors GatesGates+wires+acyclicity= combinational circ.
+Flip-flops=Synchronous
circ.CPUs
Today + what is the best we can do?! Picture taken from here. 2
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Today’s plan
• 40 min lecture session (~pages 1-9, 15-16 in the “reading material”). • Transistors
• From transistors to gates
• Combinational gates
• Wires
• Combinational circuits
• Equivalence to Boolean functions.
• Rest of the lecture:• Discuss, solve and present Question 1, Question 2 &3, or Question 4.
• Questions appear on Page 17 in the reading material.
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Transistors
• A lot to say about these devices.
• Let’s keep it simple in the 1st 3 sessions.
• Let’s view transistors as “switches”
• N-transistor:• “turn it on” → drain=source (i.e., conducting).
• “turn off” → drain and source are not connected. (i.e., not conducting)
• P-transistor:• “turn it off” → drain=source.
• “turn on” → drain and source are not connected.
• “Turn on/off” = depends on the voltage at the gate.
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From Transistors to Gates
• How does an inverter look like?• ∀𝑏 ∈ 0,1 : 𝐼𝑁𝑉 𝑥 = 1 − 𝑥
• Every gate has its propagation delay• 𝑡𝑝𝑑• Time from stable logical inputs to
stable logical outputs.• There are more parameters…
• Gates are “analog”• We interpret voltages as 0 and 1
according to some thresholds.• There are noises in any system.• → Thresholds has to be separate• → there is a “non-logical” area.• More about this later in the course.
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Combinational Gates
• Computes a simple Boolean function
• AND, OR, XOR, NXOR, NOT,…
• Takes 𝑡𝑝𝑑 time so that the output equal to the stable inputs.
• What happens when the inputs stop being stable?
• 𝑡𝑐𝑜𝑛𝑡 time after that the gate’s output becomes “garbage”
• Let’s throw in MUX as a gate as well.
• All our gates have a single output.
• Inputs & outputs of a gate aka• Terminals, ports, and pins.
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Combinational Gates
• All out gates have a single output.
• Inputs & outputs of a gate aka• Terminals, ports, and pins.
• Fan-in of a gate = • number of input ports =• number of bits in the gate’s Boolean
function =• in-degree of a node that represents
the gate.
• Our “basic” gates have fan-in 1-3.
• Let’s add input and output gates• Get the “inputs” from the outer world
and feed the output back to it. • Fan-in is 0-3
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Wires
• Simply a connection between two terminals.
• Fan-out of a gate = number of input ports it feeds.
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Combinational Circuits
• Wires “have direction”: from an output port to an input port.
• Each input port is fed by a single output port.
• Map gates to vertices, wires to arcs = Directed (labeled) Graph.
• Directed graph is acyclic (DAG) = Combinational Circuit.
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Bad Circuits
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Comb. Circuits = Boolean function
• Given stable input to a Combinational Circuit 𝐶 (or its graph representation 𝐺𝐶), we can:
1. Simulate the circuit in linear time (w.r.t. to the size of 𝐺𝐶),2. Analyze the delay of 𝐶 in linear time.
• How? Topological sorting.
• Every Combinational circuit 𝐶 implements a Boolean function.• Given that we can simulate, this argument is obvious. • Remove the MUX from our “basic gates” to make things easier (i.e., fan-in ≤ 2).
• For every Boolean function 𝑓: 0,1 𝑛 → {0,1} there is a Comb. Circuit 𝐶that implements 𝑓
• That is, ∀𝑥 ∈ 0,1 𝑛: SIMUL 𝐶, 𝑥 = 𝑓(𝑥).• Question #1 on Page 17.
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Complexity Measures: Cost and Delay
• Each gate has its cost.
• We are interested in the asymptotic behavior of our measures.
• Basic gates are of constant cost we treat them as cost=1.
• The cost of a Comb. Circ. 𝑪 is the number of its gates.
• Each gate has its propagation delay.
• Again, we are interested in the asymptotic behavior of our measures.
• Basic gates are of constant delay we treat them as 𝑡𝑝𝑑=1.
• The delay of a Comb. Circ. 𝑪 is the length of the longest input to output path in 𝑪.
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Lower Bounds: Cost and Depth
• Reminder I: The depth of a rooted tree with 𝒏 leaves is ≥ ⌈𝐥𝐨𝐠𝟐 𝒏⌉.
• Reminder II: The #nodes of every rooted tree with 𝒏 leaves is 𝟐𝒏 − 𝟏.
• Reminder III: Cost of every gate is 1 (input and output gates have 0 cost)
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The Cone of a Boolean Function
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An Example
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Composition of Functions & Graphical Cone
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Functional Cone ⊆ Graphical Cone
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“Hidden” Rooted Trees
𝑞𝑢 𝑞𝑢19
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Putting things together! LB on Cost
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Lower Bound on Delay
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Effect of fan-in≤ 𝑘 on Lower Bounds
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See you on Monday!Enjoy the discussion ☺
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How to Clock Your Computer:Digital Logic Design 2/3Moti Medina
Slides, slides material, and figures are taken from “Digital Logic Design : a rigorous approach” lecture
slides and book by Guy Even and M (Chapters: 17-20). 24
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Our Journey: From Transistors to Computers
Transistors GatesGates+wires+acyclicity= combinational circ.
+Flip-flops=Synchronous
circ.CPUs
Today
Picture taken from here.
25
≡Boolean Functions
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Today’s plan• 40 min lecture session (~pages 9-17 in the “reading material”).
• The clock (2 min)
• Clock cycles (2 min)
• Flip-flop and Clock enabled Flip-Flops (4 min)
• The Zero-delay model (2 min)
• Example: Sequential XOR. (4 min)
• Canonic form of a synch. Circuit. (5 min)
• FSMs (4 min)
• Analysis and Synthesis (4 min)
• Example 1: analysis of a counter (4 min)
• Example 2: analysis of shift register (4 mins)
• Example 3: synthesis of a 2-state FSM (6 min)
• Rest of the lecture:• Discuss, solve and present Question 5, Question 6, or Question 10, 12.
• Questions appear on Page 17 in the reading material. 26
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The Clock
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Clock Cycles
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Flip-flop
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Clock-enabled Flip-Flops
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The Zero-delay Model
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Example: Sequential XOR
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• How much a comb. circuit that imp. 𝑋𝑂𝑅𝑛 costs at best? Delay?
• Sequential version has cost of 𝑂(1)! How can that be?
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Canonic Form of a Synch. Circuit
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Functionality (without proof):
• Logical value of a signal 𝑋during the 𝑖th clock cycle by 𝑋𝑖
• Claim: For 𝑖 ≥ 0• 𝑆𝑖 = 𝑁𝑆𝑖−1• 𝑁𝑆𝑖 = 𝛿(𝐼𝑁𝑖 , 𝑆𝑖)
• 𝑂𝑈𝑇𝑖 = 𝜆(𝐼𝑁𝑖 , 𝑆𝑖)
• Why every Synch. Circuit can be represented in this Canonic Form?
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FSMs
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What does an FSM do?
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Analysis and Synthesis
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𝑆𝑦𝑛𝑐ℎ. 𝐶𝑖𝑟𝑐.⇒ 𝐹𝑆𝑀
𝐹𝑆𝑀 ⇒ 𝑆𝑦𝑛𝑐ℎ. 𝐶𝑖𝑟𝑐.
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Example 1: Analysis of a Counter
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Counter Implementation
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Counter Analysis
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Example 2: Analysis of Shift Register
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Example 2: Analysis of Shift Register
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Example 3: Synthesis of a 2-state FSM
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Example 3: The circuit
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See you on Thursday!Enjoy the discussion ☺
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How to Clock Your Computer:Digital Logic Design 3/3Moti Medina
Slides, slides material, and figures are taken from “Digital Logic Design : a rigorous approach” lecture
slides and book by Guy Even and M (Chapters: 15, 17-22). 45
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Our Journey: From Transistors to Computers
Transistors GatesGates+wires+acyclicity= combinational circ.
+Flip-flops=Synchronous
circ.CPUs
Today
Picture taken from here. 46
≡ Boolean Functions
≡ FSM
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Today’s plan
• 45 min lecture session (~pages 9-17 in the “reading material”).• Sequential Adder (4 min)
• Binary Adder (2 min)
• Ripple Carry Adder (RCA) (4 min)
• Relation between Ripple Carry Adder and Seq. Adder (2 min)
• Recursive Def. of RCA(n) (2 min)
• Registers: parallel load and serial load (aka Shift registers) (6 min)
• Random Access Memory (RAM) (10 min)
• A simplified CPU example – the DLX. (14 min)
• Recap (1 min)
• Rest of the lecture:• Discuss, solve and present Question 7, Question 8, or Question 9.
• Questions appear on Page 17 in the reading material. 47
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Sequential Adder
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Sequential Adder: Implementation
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Assume 𝑟𝑒𝑠𝑒𝑡𝑖= 1 ↔ 𝑖 = 0
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Sequential Adder: Correctness
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Complete the Pf. (Ex. 7)
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Binary Adder
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Ripple Carry Adder RCA(n)
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Relation between RCA(n) and Seq. Adder
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Recursive Definition of RCA(n)
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Can We Do Better?
• Cost and Delay of RCA(n) are Θ(𝑛).
• Lower bound of Binary Adder Ω log 𝑛 for the delay and Ω(𝑛) for the cost
• What is the cone of the 𝑆[𝑛 − 1]?• What is the cone of 𝐶[𝑛]?• Again: How did we manage to get a const.
size seq. adder then?
• Can you somehow “break” RCA(n) and make it more “parallel”?
• Almost optimal design CSA(n)• Cost is Θ(𝑛log2 3)
• Optimal design uses Parallel-Prefix Comp.• Next semester.
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Registers
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Parallel Load Register - specification
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Parallel Load Register - design
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Random Access Memory (RAM)
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RAM - definition
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Memory Cell - specification
• Wait a minute…how do we do this for a single bit?
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RAM -design
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Only the 𝐴𝑑𝑟𝑒𝑒𝑠 th bit
is “on”
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We are ready…
• We are now ready to start talking about a high-level implementation of a simplified processor (don’t get confused – this is a huge achievement).
• We know how to implement FSMs and how to implement any Boolean function.
• We also have some (more than) rough idea on how a RAM looks like.
• Let us assume a processor that interacts with a RAM which stores both instructions and data that the processor operates on.
• These instructions have some syntax and semantics, that we won’t discuss here.
• Nevertheless, we will see how to combine all the things that we saw in this series of lectures to implement a “system” that reacts to the bits that encode instructions and we shall see how that data flows in the processor. 65
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The Datapath of the Simplified DLX Machine
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ALU Environment
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Shifter Environment
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LLS: Left shiftLRS: Right shift
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The GPR Environment
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Addresses are coming from
the instruction
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Special Registers• A, B, C, MAR, MDR, PC, and IR are (ce-)
registers• With some additional logic (e.g., MUXes) for reg’s
with env’s.
• IR (Instruction Reg.) holds the instruction brought from memory.
• A,B,C are used as “interface” registers to the GPR env.
• PC (Program Counter) simply holds a “pointer” to memory which (unless the programmer affects it) advances by 1 after bringing an instruction from memory (e.g., PC env is a CE Counter).
• MAR, MDR (Mem. Add. Reg, Mem. Data. Reg.)holds a memory address that some data should be brought from and MDR holds data that is brought from memory.
• All registers in this processor are 32 bit wide70
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DLX Control• The control is an FSM that interprets the DLX
instructions.
• For every DLX instruction the control output a sequence of control signals that are input to the data-path (clock enables, MUX select bits, etc.)
• These control signals are output according to the state in which the FSM is at and according to the executed instruction…as in every FSM.
• Essentially, these control signals control the way the bits are routed between the registers.
• Let us stop here.
• By now, you know that you can implement any
FSM. The complete processor consists of
the Control and the DATA path.71
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Our journey is over: From Transistors to Computers
Transistors GatesGates+wires+acyclicity= combinational circ.
+Flip-flops=Synchronous
circ.CPUs
Picture taken from here. 72
≡ Boolean Functions
≡ FSMCan be imp by a
Synch. Circ.!
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Good Luck!Enjoy the discussion ☺
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