impact of advanced electronics for dod today · 7/19/2017 · 65 nm cmos. 14 nm cmos pixel with...

Impact of Advanced Electronics for DoD Today

Dr. Jay Lewis, Deputy DirectorDARPA Microsystems Technology Office (MTO)

Electronics Resurgence Initiative Workshop – Day 2July 19, 2017

Reference herein to any specific commercial product, process, or service by trade name, trademark or other trade name, manufacturer or otherwise, does not necessarily constitute or imply endorsement by

DARPA, the Defense Department or the U.S. government, and shall not be used for advertising or product endorsement purposes.

DISTRIBUTION STATEMENT A. Approved for public release. Distribution is unlimited.

Leading-edge ASICs under development in MTO programs could deliver revolutionary capabilities to the warfighter

CLASS Disguise and dynamically vary signals for inexpensive LPI/LPD comms

SHIELD Verify the authenticity of components at every point in the supply chain

CLASIC Distinguish and classify RF signals for 180 hours on a cellphone battery

Enable real-time machine learning for object recognition on UAVs

DAHI 10x higher dynamic range arbitrary waveform generator for RF applications

ACT** Capture unprecedented volumes of RF data at 64Gs/sec for next-gen arrays

ReImagine Collect different data in a single camera frame with a reconfigurable ROIC

RF-FPGA A software-defined front end that works for 20GHz or below

Build trusted circuits through split integration

DISTRIBUTION A. Approved for public release: distribution unlimited.

ASIC – application specific integrated circuit RF – radio frequency

Example ASIC* Capability

ROIC – readout ICLPI/LPD – low probability of intercept/detection

*ASICs from MTO programs

SPADE

UPSIDE

**Program acronyms are later slide





Enable real-time machine learning for object recognition on UAVs


ACT** Capture unprecedented volumes of RF data at 64Gs/sec for next-gen arrays



Build trusted circuits through split integration


ASIC – application specific integrated circuit RF – radio frequency


ROIC – readout ICLPI/LPD – low probability of intercept/detection

*ASICs from MTO programs

SPADE

UPSIDE

**Program acronyms on later slide





UPSIDE Enable real-time machine learning for object recognition on UAVs


ACT Capture unprecedented volumes of RF data at 64Gs/sec for next-gen arrays



SPADE Build trusted circuits through split integration


ASIC – application specific integrated circuitRF – radio frequency


ROIC – readout ICLPI/LPD – low probability of intercept/detection*ASICs from MTO programs

6.8m

m

6.5mm

5mm

4mm

Area: 44.2mm2

50% Less Area: 20mm2

40% Less Power

32nm 14nm

ACT

• Enable digital re-use forphased arrays

• Capture unprecedentedvolumes of RF data at 64Gs/sec for next-gen arrays

• Leverage the world’s best digital beamforming system

32nm SOI vs. 14nm FinFet















SHIELD

• Ensure the authenticityof genuine military electronic components

• Tag electronics at low cost with an encrypted 100µm x 100µm ASIC

• Personalization of millions of die at wafer-scale

14nm FinFet

Full AES encryption~30 µm x 30 µm

100

µm

100 µm

MicroscopicSHIELD dielet















25 µm

SOA digital ROIC pixel

layout using 65 nm CMOS

14 nm CMOS pixel with

computation

~10 µm

~6

µmImages courtesy: MIT Lincoln Laboratory

ReImagine

• Achieve full battlespaceawareness with a single reconfigurable ROIC

• Simultaneously collect diverse data types from multiple regions of interest

• ADC with signalprocessing in every pixel

14nm CMOS

Program Names

CLASS Computational Leverage Against Surveillance Systems

SHIELD Supply Chain Hardware Integrity for Electronics Defense

CLASIC Cognitive radio Low-energy signal Analysis Sensor Integrated Circuits

UPSIDE Unconventional Processing of Signals for Intelligent Data Exploitation

DAHI Dense Accessible Heterogeneous Integration

ACT Arrays at Commercial Timescales

ReImagine Reconfigurable Imaging

RF-FPGA Radio Frequency – Field Programmable Gate Array


Ongoing FY18 Programs in AdvancedComputing and Design

Dr. William Chappell, DirectorDARPA Microsystems Technology Office (MTO)

Electronics Resurgence Initiative Workshop – Day 2July 19, 2017

Reference herein to any specific commercial product, process, or service by trade name, trademark or other trade name, manufacturer or otherwise, does not necessarily constitute or imply endorsement by

DARPA, the Defense Department or the U.S. government, and shall not be used for advertising or product endorsement purposes.


$141 million in Current Efforts (FY18)

$75 millionOf New Funding

(FY18)

$216 MILLION TOTAL (FY18)


materials architectures designs

JUMP + Traditional Programs

NATIONAL ELECTRONICS CAPABILITY

2025 - 2030

materials architectures designs• JUMP – Joint University Microelectronics Program

• CHIPS – Common Heterogeneous Integration and IP Reuse Strategies

• HIVE – Hierarchical Identify Verify Exploit

• L2M – Lifelong Learning Machines

• N-ZERO - Near-Zero Power Radio Frequency Receivers

• CRAFT – Circuit Realization at Faster Time Scales

• SSITH – System Security Integrated Through Hardware and firmware

Traditional Programs Currently Funded



8/22/2016JUMP

Approved

MTO Electronics Timeline

4/2017HIVE

Kickoff


4/2016CRAFT Kickoff

1/2017L2M

Approved

11/2015

N-ZEROKickoff

2016 2017 2018 2019

Today

4/2017SSITH

BAA Released

6/2016CHIPS

Approved

• Ultra Low Power Design

• Reduced Design Time

• Pseudolithic Design

• Broad University Support

• In Field Machine Learning

• Graph Processing

• Built in Security

Joint University Microelectronics Program(JUMP)

RF to THz Distributed Computing

Cognitive Computing

IntelligentMemory/Storage

Advanced IC Architectures

Devices/Materials

Industry

40% 60%


Joint University Microelectronics Program (JUMP)

Predecessor Program STARnet

• 646 Graduate students

• 184 Faculty researchers

• 46 Universities

• 6,118 Research publications

Circuit Realization at Faster Time Scales (CRAFT)

Driving a design methodology that can be used to quickly design flexible, high

performance custom integrated circuits using leading-edge CMOS technology while

driving DoD to use the best commercial fabrication and design practices

Sharply reduce barriers to DoD use of leading-edge custom integrated circuits (ICs) for orders-of-magnitude higher performance

at low power for DoD systems.

DoD (Today)

CRAFT(Future)

Chip Design and Fabrication Time (weeks)


N-ZERO passive sensor wake-up

Devices are off (zero power consumption) yet continually alert.

10000

1000

100

10

10.01 0.1 1.0 10 100

Unattended Ground Sensors

1 mo.

1 yr.

10 yrs.

Life

time

(Day

s)

Event Activity (% of Time)

Battery leakage, active processing and

N-ZERO wake-up

Battery drainage by active wake-

up circuitry

• Continuous operation and near-zero power processing• Persistent sensing with greatly extended lifetime and reduced cost• Multiple sensing modalities with sensor fusion


Acoustic Sensor Wake-up

Wake-up to generator and truck at > 5m with 12 nW of power consumptionS. Jeong, et al. "21.6 A 12nW always-on acoustic sensing and object recognition microsystem using frequency-domain feature extraction and SVM classification." Solid-State Circuits Conference (ISSCC), 2017 IEEE International. IEEE, 2017.

Acoustic Signal

Sound of Interest+

Noise

Identify


Hierarchical identify Verify Exploit (HIVE)

Enabling the DoD to perform graph analytics at the edge of the battlefield and not rely on datacenters back in the United

States; providing greater situational awareness in addition to the ability to do

real time sensor fusion and exploitation at the lowest echelons

Next-generation server processor designed to find patterns in streaming data sets by using graph analytics


HIVE: An example of blending commercial and DoD interests

CUDA – compute unified device architectureTPU – tensor processing unitGPU – graphics processing unit

TA 3:Evaluator (evaluation framework 100-1000x improvement)

TA 1: Graph analytics accelerator(ref: TPU, GPU)

TA 2:Graph analytics toolkits (ref: Tensorflow, CUDA)

Graph Software

What should be accelerated?

GraphHardware

How should it be accelerated?

Define graph primitives

Create data format model

Define data flow model

Identify/Develop hardware

accelerators for each building block

Create memorycontroller which optimizes data

movement based on sparse mapping

Develop busarchitectures

to avoid congestion in

data movement

Accelerators Memory Scaling

Cyber security

NorthropGrumman

Georgia TechPacific Northwest

Intel

Qualcomm


Lifelong Learning Machines (L2M)

Pursuing approaches for biologically-inspired artificial intelligence utilizing

flexible models to continue adapting during execution in the field

Continual Learning

Mechanisms

Fundamentally new machine learning mechanisms for machines that learn continuously as they operate


Cortical Processor results


Adaptive Architectures

Results • Found optimal result278x faster than gridsearch method*

• Slightly higheraccuracy than thehand designed(Neverova et.al. 2015)*12 iterations vs ~3300

System modifies architecture via hyper-parameters and finds best

fusion processing paradigm

Determine Optimal Fusion Architecture• 21 classes, 3 modalities (ChaLearn, gesture)

SRI (Chai)

Dense Captioning

Context: learning picture elements and relationships instead of whole

image captioningContext Sensitivity

Requires localization and recurrence

Stanford (Li)

Learn Architecture

Collaborative Machine Intelligence Mitigating Catastrophic Forgetting

Classification error:• Set 1 – Pedestrians and bikers• Set 2 – Skateboarders and cars

Predict Motion using Social LSTM

Average Error vs. Predicted Location

Lifelong Learning

Collaborative Machine Intelligence

Modeled Predictions

Multiple Interacting Neural Networks

Algorithmic Solutions

Each network sees some of others: interacts intelligently

with dynamic worldFirst steps toward solving

catastrophic forgetting

Stanford-UTK (Savarese) Stanford-UTK (Savarese)

Cortical Processor results


Common Heterogeneous Integration and IP Reuse Strategies (CHIPS)

Market IP Proprietary IP

6 –

12 W

eeks

Integrate

CHIPS enables rapid integration of modular circuits at the die level

Developing the design tools and integration standards required to demonstrate modular

integrated circuit (IC) designs that leverage the best of the DoD and commercial designs and

technology


Predecessor is DAHI


300mm diameter Si CMOS wafer (45nm node)

Successful testing identified optimal S/H circuit for ADC

(>65dB SFDR @ 2GHz)Frequency (Hz) 10 9

0 1 2 3 4 5 6 7

Rel

ativ

e Am

plitu

de (d

B)

-90

-80

-70

-60

-50

-40

-30

-20

-10

0FCLK_15 GHz, FCW_771_clk_ttune_128_dem_en_0

DAC with very low digital noise

(-70dBc)

0

20

40

60

80

R2C3

M0

R3C4

M0

R4C3

M0

R5C4

M0

R2C3

M0

R3C4

M0

R4C3

M0

R5C4

M0

R2C3

M0

R3C4

M0

R4C3

M0

R5C4

M0

R2C3

M1

R3C4

M1

R4C3

M1

R5C4

M1

R2C3

M0

R3C4

M0

R4C3

M0

R5C4

M0

R2C3

M0

R3C4

M0

R4C3

M0

R5C4

M0

AR_2 AR_2A AR_1 AR_1A AR_1B

HIC Redundancy: None HIC Redundancy: 2x

HBT

Arra

y -B

eta

at 1

mA

Beta_812_@1mA Beta_813_@1mA Beta_814_@1mA Beta_815_@1mA Beta_862_@1mA Beta_863_@1mA Beta_864_@1mA Beta_865_@1mA Beta_872_@1mA Beta_873_@1mA Beta_874_@1mA Beta_875_@1mA

High foundry integration yields; test

vehicles fully functional

99.94% HIC yield98% HBT post-integration

DAHI integration (Dec 2015): Si (45nm), InP (TF5 HBT), GaN (GaN20 HEMT)

Sources: DARPA, Northrop GrummanDAHI – Diverse Accessible Heterogeneous Integration

CHIPS challenge: make a usable interface standardSource: DARPA

LVDS

32nm_SerDes

65nm_SerDes28nm_SerDes

28nm_SerDesProprietary

PCIe

HBM

WideIO

Si Photonic

1.00E+03

1.00E+04

1.00E+05

1.00E+06

1.00E+07

1.00E+08

1.00E+09

1.00E+10

1.00E+11

1.00E-05 1.00E-04 1.00E-03 1.00E-02 1.00E-01 1.00E+00

BWD

/EPB

Interconnect Length (m)

MonoLithic PCB

What standards will allow CHIPS to bridge the gap?

Interface standards:Too many? Not enough? How to compare?

Too many solutions can hinder wider adoption

𝐺𝐺𝐺𝐺𝐺𝐺𝐺𝐺/𝑚𝑚𝑚𝑚𝐸𝐸𝐸𝐸𝑒𝑒𝑟𝑟𝑔𝑔𝑦𝑦/𝐺𝐺𝑏𝑏𝑏𝑏


CHIPS challenge: make a usable interface standardSource: DARPA

LVDS

32nm_SerDes

65nm_SerDes28nm_SerDes

28nm_SerDesProprietary

PCIe

HBM

WideIO

Si Photonic

1.00E+03

1.00E+04

1.00E+05

1.00E+06

1.00E+07

1.00E+08

1.00E+09

1.00E+10

1.00E+11

1.00E-05 1.00E-04 1.00E-03 1.00E-02 1.00E-01 1.00E+00

BWD

/EPB

Interconnect Length (m)

MonoLithic PCB

Interface standards:Too many? Not enough? How to compare?

𝐺𝐺𝐺𝐺𝐺𝐺𝐺𝐺/𝑚𝑚𝑚𝑚𝐸𝐸𝐸𝐸𝑒𝑒𝑟𝑟𝑔𝑔𝑦𝑦/𝐺𝐺𝑏𝑏𝑏𝑏

CHIPS Convergence to a minimal set of standards is necessary


MTO Electronics Timeline


2016 2017 2018 2019

JUMPUniversity Driven

Page 3 InvestmentsIndustry Driven

• N-ZERO• CRAFT• HIVE• L2M• CHIPS• SSITH

Traditional Programs

8/22/2016JUMP

Approved

4/2017HIVE

Kickoff

4/2016CRAFT Kickoff

1/2017L2M

Approved

11/2015

N-ZEROKickoff

Today

4/2017SSITH

BAA Released

6/2016CHIPS

Approved

Linton SalmonMaterials and Integration




Workshop Summary:

Tom RondeauWade ShenArchitectures




Workshop Summary:

Andreas OlofssonDesigns




Workshop Summary:

Proposals Requested

Proposals Submitted

Partners Selected

Funding Released

OctSepAugJulJunMay Dec Jan Apr

Launch, Learn, & Organize

6/21: Industry Discussion7/11: Defense Base

Summit

Open Competition

9/12: Proposals Requested (Expected)

Complete Contracting

4/20: Start Work

Summer of Listening

7/18: 2-day workshop onMaterials, Architectures,

Designs

V

V

Nov

Completed Happening Now Fall 2017 Spring 2018

7 months

Defense Base Summit

2-dayWorkshop


MTO Electronics Resurgence Initiative Timeline

(HIVE) (CRAFT) (Possible)

Defense and National Needs


Teaming Session

Advantest Cadence IBM Microsemi Qualcomm ST Research

Allvia, Inc. Cold Logic Intel Microsoft Quantum Semiconductor Teledyne

Alphacore Esperanto Technologies Intermolecular MonolithIC 3D QuickLogic Teradeep

Analog Devices Ethaphase Intrinsix Moon RF2BITS Texas Instruments

Applied Materials Fault Tolerant Technology Jariet Nanoshift Sage Design

Automation TSMC

ARM Ferric, Inc. Kryptos Solutions Novati Siemens Vista Ventures

Astrileux Flex Innovation Kyndi Nuvotronics Silicon Storage Technologies Xilinx

Avalanche Technology Google MaXentric NVIDIA Silvaco

Bell Labs HP Mentor Graphics PARC SRI International

BroadPak HRL Micron Photia Synopsys

Commercial Attendees

AFRL Georgia Tech Portland State University of Arkansas

University of Texas at Dallas

Arizona State Harvard Purdue University of Illinois at Chicago

University of Washington

ARL MIT Sandia National Lab

University of Massachusetts USC

Berkeley National Lab

Naval Research Lab Stanford University of

Michigan Virginia Tech

BRIDG NC State UC Berkeley University of Minnesota

Columbia University Northwestern UC Davis University of New

Mexico

Cyclotron Road Notre Dame UC San Diego University of Pennsylvania

DRAPER Oak Ridge National Lab UC Santa Cruz University of

Texas at Dallas

University/Research Attendees

BAE

Boeing

Leidos

Lockheed Martin

Northrop Grumman

Raytheon

Rockwell Collins

Defense Industry Attendees



Teaming Session #111:00 am – 12:30 pm

Fol lowed by:Lunch (12:30PM, Imperial Bal lroom) | Teaming Session #2 (2:00PM, Club Regent) | Workshop Close (4:00PM)




Teaming Session #22:00 pm – 4:00 pm

The workshop wil l adjourn informal ly at 4:00pm. Thank you for attending.


impact of advanced electronics for dod today · 7/19/2017 · 65 nm cmos. 14 nm cmos pixel with...

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