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Undergraduate, Technical 8/17/2012 Internship Presentation Mattics Phi Team: Silicon Applications, PPD Manager: Randal Kuramoto Mentor: Matt Nielson

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Page 1: Intern Presentation (Mattics)

Undergraduate, Technical8/17/2012

Internship PresentationMattics PhiTeam: Silicon Applications, PPDManager: Randal KuramotoMentor: Matt Nielson

Page 2: Intern Presentation (Mattics)

Cal Poly, San Luis Obispo– SLO LIFE

It’s me!

Hail from San Jose, CA

B.S., Electrical Engineering

Page 3: Intern Presentation (Mattics)

Current Goals

Application Note (XAPP)– FPGA configuration using SPI/uP implementation

• All Programmable

• Faster, low cost, easier

• Work with mentor

• Apply for patent

eFuse– Customer found issue with feature, asked to verify

SPI Flash Verification– Documentation project

Page 4: Intern Presentation (Mattics)

Legacy XAPP058 Flow for updating design in system

Out with the old, in with the new!

Released in August 1996

Last revised in March 2009

One of the most downloaded Application Notes

Well established back then, not now

Top in configuration case category

Page 5: Intern Presentation (Mattics)

Legacy XAPP058 Flow for updating design in system

New microprocessor + SPI Flash solution for updating

design in system

Out with the old, in with the new!, Cont.

Page 6: Intern Presentation (Mattics)

New microprocessor + SPI Flash solution for updating

design in system

Out with the old, in with the new!, Cont.

Utilizes current hardware found on most boards

In-System setup that consists of SPI Flash and microprocessor

Simplifies previous solution

Design file in non-volatile memory

In-direct programming

Page 7: Intern Presentation (Mattics)

Out with the old, in with the new!, Cont.

Legacy XAPP058 New Solution

Multi-Stage Implementation Standard setup: Microprocessor and SPI Flash

Huge file size (130 MB) Small file size (11 MB)

Multi-boot/fallback controlled by FPGA/Bitgen mechanism

Microprocessor controls multi-boot and fallback

More signals being used due to multiple signal types

Less signals being used due to integrated signals

Page 8: Intern Presentation (Mattics)

Blowing up eFuses!

Category 1 customer found issue with eFuse verify– Customer’s encryption key did not match eFuse key, iMPACT fail

– iMPACT verify too harsh

Setup and procedure– Spartan 6 and LX150T

– Use Logic Analyzer to verify programming sequence of iMPACT

What exactly is an eFuse?– Number of individual eFuses, 256 primary and redundant

– Stores encryption key

Page 9: Intern Presentation (Mattics)

Blowing up eFuses!

Worked closely with QNG to verify iMPACT and ATE– Discrepancy between iMPACT and ATE verify

– Filed change request (CR) against iMPACT

– Verified that iMPACT was reading the blown fuses correctly

Typical Blown Fuse

Margin Read

Safety Margin

Normal Read

Unblown Fuse

Hig

her

Res

ista

nce

X

Page 10: Intern Presentation (Mattics)

Development for test suite– Developed a suite of tests to ensure parts were compatible on iMPACT

– Baseline for Silicon Applications team, Software Development groups

SPI Flash Verification

Page 11: Intern Presentation (Mattics)

Development for test suite– Developed a suite of tests to ensure parts were compatible on iMPACT

– Baseline for Silicon Applications team, Software Development groups

– Tested compatibility with current FPGAs

– Filed Change Request (CR) against iMPACT

SPI Flash Verification

Page 12: Intern Presentation (Mattics)

What I gave to Xilinx– Patent

– Multiple CRs

– Co-Authored an Application Note

We give and we take

What I received from Xilinx– Real work experience in the semiconductor industry

– A great team to work with

– Networking

Page 13: Intern Presentation (Mattics)

Questions? Concerns?