interrupt handling2ndtest
TRANSCRIPT
Introduction to Embedded Systems
ARM Exception Handling andARM Exception Handling andSoftware Interrupts (SWI)Software Interrupts (SWI)
Introduction to Embedded Systems
Outline of this presentationOutline of this presentation• Normal program flow vs. exceptions
– Exceptions vs. interrupts• Software Interrupts
– What is an SWI?– What happens on an SWI?– Vectoring SWIs– What happens on SWI completion?– What do SWIs do?– A Complete SWI Handler– A C_SWI_Handler (written in C)
• Loading the Software Interrupt Vector Table
Introduction to Embedded Systems
Normal Program Flow Normal Program Flow vs.vs. Exceptions Exceptions • Normally, programs execute sequentially in user mode• Exceptions and interrupts break the sequential flow of a program.• Most exceptions have an associated software exception handler- a
software routine that executes when an exception occurs.• In ARM, Software Interrupt (SWI) is the “system call” exception. • Types of ARM exceptions
– reset when CPU reset pin is asserted – undefined instruction when the processor cannot decode an instruction– software interrupt when CPU executes the SWI instruction – Prefetch abort when the processor attempts to fetch an instruction from
an address without the correct access permissions– data abort when an instruction attempts to access data memory
without the correct access permission – IRQ when CPU's external interrupt request pin is asserted – FIQ when CPU's external fast interrupt request pin is asserted
Introduction to Embedded Systems
TerminologyTerminologyThe terms exception and interrupt are often confused
• Exception – They can happen because of some kind of exceptional condition during execution mode. usually refers to an internal CPU event such as – floating point overflow – MMU fault (e.g., page fault)
• Interrupt - occurs because of external devices outside the CPU core.usually refers to an external I/O event such as
• I/O device request • Reset
It is a special type of exception• SWI – Explicit instruction as a part of code.
Introduction to Embedded Systems
Exceptions and associated modesExceptions and associated modes
Introduction to Embedded Systems
When exception occurs:When exception occurs:• The core automatically
- saves the cpsr to the spsr of the exception mode- saves the pc to the lr of the exception mode- sets the cpsr to the exception mode- set pc to the address of the exceptional handler
Introduction to Embedded Systems
Vector tableVector table
It is a table of addresses that the ARM core branches to when an exception is raised
Introduction to Embedded Systems
Vector TableVector Table• Service routine cannot be put at these addresses• Theses addresses commonly contain branch instructions of one of the
following forms:• B<address> - This branch instruction provides a branch relative from
the pc• LDR pc, [pc, #offset] – This instruction loads the handler address from
memory to pc-This results in slight delay due to extra memory
access.-Any address in the memory can be used for branch
• LDR pc, [pc, #-0xff0] – This instruction is used when a vector interrupt controller is present( VIC PL190)
• MOV pc, #immediate – This copies an immediate value into the pc. The address must be an 8-bit immediate rotated right by an even number of bits
Introduction to Embedded Systems
Exception priority levelsException priority levels
Introduction to Embedded Systems
Entering and exiting an exception handler Entering and exiting an exception handler
Introduction to Embedded Systems
Controlling the interruptsControlling the interrupts
• Enabling an interrupt
• Disabling an interrupt
Introduction to Embedded Systems
Interrupt latencyInterrupt latency• It is the interval of time from an external interrupt request signal being
raised to the first fetch of an instruction of a specific interrupt service routine.
• Interrupt latency depends on a combination of hardware and software.
Introduction to Embedded Systems
Interrupt latencyInterrupt latency
Introduction to Embedded Systems
Link register offsetsLink register offsets
Introduction to Embedded Systems
How the interrupts are designedHow the interrupts are designed
• SWI are normally used to call privileged operating systems
• IRQ is normally assigned to general purpose interrupts
• FIQ is reserved for one single interrupt source that requires fast response time.
Introduction to Embedded Systems
Interrupt handling schemesInterrupt handling schemes• Non nested interrupt handler- it handles and services individual
interrupts sequentially• Nested interrupt handler- handles multiple interrupts without a priority
assignment• Reentrant interrupt handler- handles multiple interrupts that can be
prioritized• Prioritized simple interrupt handler- handles prioritized interrupts• Prioritized standard interrupt handler- handles higher priority interrupts
in a shorter time than lower priority interrupts• Prioritized direct interrupt handler- handles higher-priority interrupts in a
shorter time and goes directly to a specific service routine• Prioritized grouped interrupt handler- is a mechanism for handling
interrupts that are grouped into different priority levels
Introduction to Embedded Systems
Simple non nested interrupt handlerSimple non nested interrupt handler
Introduction to Embedded Systems
Interrupt handlerInterrupt handler
Introduction to Embedded Systems
Nested interrupt handlerNested interrupt handler