lic lab manual

P.S.R. ENGINEERING COLLEGESIVAKASI – 626 140.

DEPARTMENT OF EEE

LAB MANUAL

CLASS : II YEAR EEESEMESTER : IV SEMESTERACADEMIC YEAR : 2009-2010SUBJECT CODE : EE 48SUBJECT : LINEAR AND DIGITAL INTEGRATED CIRCUITS LAB

PREPARED BYR.MAHENDRAN M.E.,T.BALASUBRAMANIAN M.E.,LECTURER/EEE

APPROVED BY

HOD/EEE

R.MAHENDRAN T.BALA SUBRAMANIAN

DEPT OF EEE/PSREC1

INSTRUCTIONS TO THE STUDENTS

1. Candidates should come to the lab with proper Uniform and Good quality Leather

shoes.

2. Punctuality and strict Discipline should be maintained.

3. Study and prepare well before entering into the lab.

4. Complete the observation after completion of the experiment in the lab itself.

5. Be alert till the experiment is completed.

6. Make sure that supply is OFF before touching any terminals.

7. Use proper rating equipments carefully, for which you are duly responsible.

8. Handle the equipments carefully, for which you are duly responsible.

9. Return all the components and make sure that nothing is left on the worktable.

10. In case of any wrong observations you have to switch off the power

supply related with it.11. Don’t use meter terminals as junctions and place them to read

Conveniently.


DEPT OF EEE/PSREC2

SYLLABUS

EC 1314 INTEGRATED CIRCUITS LABORATORY 0 0 3 100

AIM:To study various digital & linear integrated circuits used in simple

system configuration.

LIST OF EXPERIMENTS:

1. Study of Basic Digital IC’s. Verification of truth table for AND, OR, EXOR, NOT, NOR, NAND, JK FF, RS FF, D FF)

2. Implementation of Boolean Functions, Adder/ Subtractor circuits. 3.a). Code converters, Parity generator and parity checking, Excess 3, 2s

Complement, Binary to gray code using suitable IC’s .

b) Encoders and Decoders: Decimal and Implementation of 4-bit shift registers in SISO,SIPO,PISO,PIPO modes using suitable IC’s.

4. Counters: Design and implementation of 4-bit modulo counters as synchronous and asynchronous types using FF IC’s and specific counter IC.

5. Shift Registers: Design and implementation of 4-bit shift registers in SISO, SIPO, PISO, PIPO modes using suitable IC’s.

6. Multiplex/ De-multiplex : Study of 4:1; 8:1 multiplexer and Study of 1:4; 1:8 demultiplexer

7. Timer IC application. Study of NE/SE 555 timer in Astable, Monostable operation.

8. Application of Op-Amp-I Slew rate verifications, inverting and non-inverting amplifier, Adder, comparator, Integrator and Differentiator.

9. Study of Analog to Digital Converter and Digital to Analog Converter:

Verification of A/D conversion using dedicated IC’s.

10. Study of VCO and PLL ICs i. Voltage to frequency characteristics of NE/ SE 566 IC.


DEPT OF EEE/PSREC3

ii. Frequency multiplication using NE/SE 565 PLL IC.

P = 45 Total = 45DETAILED SYLLABUS

1. Study of Basic Digital IC’s.(Verification of truth table for AND, OR, EXOR, NOT, NOR, NAND, JK FF, RS FF, D FF)

Aim To test of ICs by using verification of truth table of basic ICs.

Exercise

1. Breadboard connection of ICs with truth table verification using LED’s.

2. Implementation of Boolean Functions, Adder/ Subtractor circuits. [Minimization using K-map and implementing the same in POS, SOP from Using basic gates]

Aim

Minimization of functions using K-map implementation and combination Circuit.

Exercise

1. Realization of functions using SOP, POS, form.

2. Addition, Subtraction of at least 3 bit binary number using basic gate IC’s. 3a) Code converters, Parity generator and parity checking, Excess 3, 2s Complement, Binary to gray code using suitable IC’s .

Aim Realizing code conversion of numbers of different bar.

Exercise

1 Conversion Binary to Grey, Grey to Binary; 1’s. 2’s complement of numbers addition, subtraction,

2. Parity checking of numbers using Gates and with dedicated IC’s

3b) Encoders and Decoders: Decimal and Implementation of 4-bit shift registers SISO, SIPO, PISO, PIPO modes using suitable IC’s.

Exercise

1. Decimal to binary Conversion using dedicated IC’s.


DEPT OF EEE/PSREC4

2. BCD – 7 Segment display decoder using dedicated decoder IC& display.

4. Counters: Design and implementation of 4-bit modulo counters as synchronous and asynchronous types using FF IC’s and specific counter IC

Aim

Design and implementation of 4 bit modulo counters.

Exercise

1. Using flip-flop for up-down count synchronous count. 2. Realization of counter function using dedicated ICs.

5. Shift Registers

Design and implementation of 4-bit shift registers in SISO, SIPO, PISO, PIPO

modes using suitable IC’s. Aim

Design and implementation of shift register. Exercise

1. Shift Register function realization of the above using dedicated IC’s For SISO, SIPO, PISO, PIPO, modes of atleast 3 bit binary word.

2. Realization of the above using dedicated IC’s.

6. Multiplex/ De-multiplex

Study of 4:1; 8:1 multiplexer and Study of 1:4; 1:8 demultiplexer

Aim

To demonstrate the addressing way of data channel selection for multiplex De-multiplex operation.

Exercise

1. Realization of mux-demux functions using direct IC’s. 2. Realization of mux-demux using dedicated IC’s for 4:1, 8:1, and vice versa.

7. Timer IC application. Study of NE/SE 555 timer in Astable, Monostable operation.

Aim To design a multi vibrator circuit for square wave and pulse

generation.


DEPT OF EEE/PSREC5

Exercise

1. Realization of Astable multivibrator & monostable multivibrator circuit

using Timer IC. 2. Variation of R, C, to vary the frequency, duty cycle for signal generator.

8. Application of Op-Amp-I

Slew rate verifications, inverting and non-inverting amplifier, Adder, comparator, Integrator and Differentiator.

Aim

Design and Realization of Op-Amp application.

Exercise

1. Verification of Op-Amp IC characteristics. 2. Op-Amp IC application for simple arithmetic circuit. 3. Op-Amp IC application for voltage comparator wave generator and

wave shifting circuits.

9. Study of Analog to Digital Converter and Digital to Analog Converter: Verification of A/D conversion using dedicated IC’s.

Aim

Realization of circuit for digital conversions.

Exercise

1. Design of circuit for analog to digital signal conversion using dedicated

IC’s. 2. Realization of circuit using dedicated IC for digital analog conversion.

10. Study of VCO and PLL IC’s

i). Voltage to frequency characteristics of NE/ SE 566 IC. ii). Frequency multiplication using NE/SE 565 PLL IC.

Aim

Demonstration of circuit for communication application Exercise

1. To realize V/F conversion using dedicated IC’s vary the frequency of the generated signal.

2. To realize PLL IC based circuit for frequency multiplier, divider.

LIST OF EXPERIMENTS


DEPT OF EEE/PSREC6

CYCLE I :

1. Inverting and Non – Inverting Amplifier

2. Differentiator and Integrator

3. Astable Multivibrator

4. Monostable Multivibrator

5. Study of basic Digital ICs

6. Implementation of Boolean functions

7. Implementation of Half Adder & Full Adder.

CYCLE II:

1. Implementation of Half Subtractor & Full Subtractor. 2. Code converters.

3. Parity Generator & Checker.

4. Multiplexer / Demultiplexer

5. Asynchronous Decade counter

6. Shift Register.

7. Study of Flip-Flops

Expt. No.1 INVERTING AND NON – INVERTING AMPLIFIER


DEPT OF EEE/PSREC7

1. a. INVERTING AMPLIFIER

AIM:

To design an Inverting Amplifier for the given specifications using Op-Amp IC 741.

APPARATUS REQUIRED:

S.No Name of the Apparatus Range Quantity1. Function Generator 3 MHz 12. CRO 30 MHz 13. Dual RPS 0 – 30 V 14. Op-Amp IC 741 15. Bread Board 16. Resistors As required7. Connecting wires and probes As required

THEORY:

The input signal Vi is applied to the inverting input terminal through R1 and the non-inverting input terminal of the op-amp is grounded. The output voltage Vo is fed back to the inverting input terminal through the R f - R1 network, where Rf is the feedback resistor. The output voltage is given as,

Vo = - ACL Vi

Here the negative sign indicates that the output voltage is 180 0 out of phase with the input signal.

PROCEDURE:

1. Connections are given as per the circuit diagram.2. + Vcc and - Vcc supply is given to the power supply terminal of the Op-Amp

IC.3. By adjusting the amplitude and frequency knobs of the function generator,

appropriate input voltage is applied to the inverting input terminal of the Op-Amp.

4. The output voltage is obtained in the CRO and the input and output voltage waveforms are plotted in a graph sheet.

PIN DIAGRAM:


DEPT OF EEE/PSREC8

CIRCUIT DIAGRAM OF INVERTING AMPLIFIER:

DESIGN:

We know for the gain of inverting Amplifier ACL = RF / R1

Assume R1 ( approx. 10 KΩ ) and find Rf

Hence Vo = - ACL Vi

OBSERVATIONS:

S.No InputOutput

Practical Theoretical

1.Amplitude( No. of div x Volts per div )

2.Time period( No. of div x Time per div )

MODEL GRAPH:R.MAHENDRAN

T.BALA SUBRAMANIANDEPT OF EEE/PSREC

9

RESULT:

The design and testing of the inverting amplifier is done and the input and output waveforms were drawn.

i).output voltage of the inverting amplifier is …………


DEPT OF EEE/PSREC

t

t

10

Vi

+1V

Vo

+V

-V

1. b. NON - INVERTING AMPLIFIER

AIM:

To design a Non-Inverting Amplifier for the given specifications using Op-Amp IC 741.

APPARATUS REQUIRED:

S.No Name of the Apparatus Range Quantity1. Function Generator 3 MHz 12. CRO 30 MHz 13. Dual RPS 0 – 30 V 14. Op-Amp IC 741 15. Bread Board 16. Resistors As required7. Connecting wires and probes As required

THEORY:

The input signal Vi is applied to the non - inverting input terminal of the op-amp. This circuit amplifies the signal without inverting the input signal. It is also called negative feedback system since the output is feedback to the inverting input terminals. The differential voltage Vd at the inverting input terminal of the op-amp is zero ideally and the output voltage is given as,

Vo = ACL Vi

Here the output voltage is in phase with the input signal.

PROCEDURE:



appropriate input voltage is applied to the non - inverting input terminal of the Op-Amp.


PIN DIAGRAM:


DEPT OF EEE/PSREC11

CIRCUIT DIAGRAM OF NON INVERITNG AMPLIFIER:

DESIGN:

We know for a Non-inverting Amplifier ACL = 1 + ( RF / R1)Assume R1 ( approx. 10 KΩ ) and find Rf

Hence Vo = ACL Vi

OBSERVATIONS:

S.No InputOutput

Practical Theoretical



MODEL GRAPH:


DEPT OF EEE/PSREC12

RESULT:

The design and testing of the Non-inverting amplifier is done and the input and output waveforms were drawn. i).output voltage of the non-inverting amplifier is …………


DEPT OF EEE/PSREC13

Expt. No.2 DIFFERENTIATOR AND INTEGRATOR

2. a. DIFFERENTIATOR

AIM:

To design a Differentiator circuit for the given specifications using Op-Amp IC 741.

APPARATUS REQUIRED:

S.No Name of the Apparatus Range Quantity1. Function Generator 3 MHz 12. CRO 30 MHz 13. Dual RPS 0 – 30 V 14. Op-Amp IC 741 15. Bread Board 16. Resistors7. Capacitors8. Connecting wires and probes As required

THEORY:

The differentiator circuit performs the mathematical operation of differentiation; that is, the output waveform is the derivative of the input waveform. The differentiator may be constructed from a basic inverting amplifier if an input resistor R1 is replaced by a capacitor C1 . The expression for the output voltage is given as,

Vo = - Rf C1 ( dVi /dt )

Here the negative sign indicates that the output voltage is 180 0 out of phase with the input signal. A resistor Rcomp = Rf is normally connected to the non-inverting input terminal of the op-amp to compensate for the input bias current. A workable differentiator can be designed by implementing the following steps:

1. Select fa equal to the highest frequency of the input signal to be differentiated. Then, assuming a value of C1 < 1 µF, calculate the value of Rf.

2. Choose fb = 20 fa and calculate the values of R1 and Cf so that R1C1 = Rf Cf.

The differentiator is most commonly used in waveshaping circuits to detect high frequency components in an input signal and also as a rate–of–change detector in FM modulators.

PIN DIAGRAM:


DEPT OF EEE/PSREC14

CIRCUIT DIAGRAM OF DIFFERENTIATOR:

DESIGN :

[ To design a differentiator circuit to differentiate an input signal that varies in frequency from 10 Hz to about 1 KHz. If a sine wave of 1 V peak at 1000Hz is applied to the differentiator , draw its output waveform.]

Given fa = 1 KHz We know the frequency at which the gain is 0 dB, fa = 1 / (2π Rf C1)Let us assume C1 = 0.1 µF ; thenRf = _________Since fb = 20 fa , fb = 20 KHzWe know that the gain limiting frequency fb = 1 / (2π R1 C1)Hence R1 = _________Also since R1C1 = Rf Cf ; Cf = _________

Given Vp = 1 V and f = 1000 Hz, the input voltage is Vi = Vp sin ωtWe know ω = 2πf


DEPT OF EEE/PSREC15

Hence Vo = - Rf C1 ( dVi /dt ) = - 0.94 cos ωt

PROCEDURE:





OBSERVATIONS:

S.No Input Output



MODEL GRAPH:

RESULT:

The design of the Differentiator circuit was done and the input and output waveforms were obtained.

a).amplitude…………b). frequency………….


DEPT OF EEE/PSREC16

2. b. INTEGRATOR

AIM:

To design an Integrator circuit for the given specifications using Op-Amp IC 741.

APPARATUS REQUIRED:

S.No Name of the Apparatus Range Quantity1. Function Generator 3 MHz 12. CRO 30 MHz 13. Dual RPS 0 – 30 V 14. Op-Amp IC 741 15. Bread Board 16. Resistors7. Capacitors8. Connecting wires and probes As required

THEORY:

A circuit in which the output voltage waveform is the integral of the input voltage waveform is the integrator. Such a circuit is obtained by using a basic inverting amplifier configuration if the feedback resistor Rf is replaced by a capacitor Cf . The expression for the output voltage is given as,

Vo = - (1/Rf C1 ) ∫ Vi dt

Here the negative sign indicates that the output voltage is 180 0 out of phase with the input signal. Normally between fa and fb the circuit acts as an integrator. Generally, the value of fa < fb . The input signal will be integrated properly if the Time period T of the signal is larger than or equal to Rf Cf . That is,

T ≥ Rf Cf

The integrator is most commonly used in analog computers and ADC and signal-wave shaping circuits.


DEPT OF EEE/PSREC17

PIN DIAGRAM:

CIRCUIT DIAGRAM OF INTEGRATOR:

DESIGN:

[ To obtain the output of an Integrator circuit with component values R1Cf = 0.1ms , Rf = 10 R1 and Cf = 0.01 µF and also if 1 V peak square wave at 1000Hz is applied as input.]

We know the frequency at which the gain is 0 dB, fb = 1 / (2π R1 Cf)Therefore fb = _____Since fb = 10 fa , and also the gain limiting frequency fa = 1 / (2π Rf Cf)We get , R1 = _______ and hence Rf = __________


DEPT OF EEE/PSREC18

PROCEDURE:





OBSERVATIONS:

S.No Particulars Input Output



MODEL GRAPH:

(A rectangular waveform is applied to the input of an integrator. If R = 10 kW and C = 0.1 mF; sketch vo. Assume zero initial value for vo.)

RESULT:

The design of the Integrator circuit was done and the input and output waveforms were obtained.

a).Input Sine wave ,Output ……………….b).Input triangular,Output………………..


DEPT OF EEE/PSREC

t (ms)

2

-2

01

-1

0.51.5

2.53.5

4.5

vin

vo0

19

Expt. No.3 ASTABLE MULTIVIBRATOR AIM:

To design an Astable multivibrator circuit for the given specifications using 555 Timer IC.

APPARATUS REQUIRED:

S.No Name of the Apparatus Range Quantity1. Function Generator 3 MHz 12. CRO 30 MHz 13. Dual RPS 0 – 30 V 14. Timer IC IC 555 15. Bread Board 16. Resistors7. Capacitors8. Connecting wires and probes As required

THEORY:

An Astable multivibrator, often called a free-running multivibrator, is a rectangular-wave-generating circuit. This circuit do not require an external trigger to change the state of the output. The time during which the output is either high or low is determined by two resistors and a capacitor, which are connected externally to the 555 timer. The time during which the capacitor charges from 1/3 Vcc to 2/3 Vcc is equal to the time the output is high and is given by,

tc = 0.69 (R1 + R2) C

Similarly the time during which the capacitor discharges from 2/3 Vcc to 1/3 Vcc is equal to the time the output is low and is given by,

td = 0.69 (R2) C

Thus the total time period of the output waveform is,

T = tc + td = 0.69 (R1 + 2 R2) C

The term duty cycle is often used in conjunction with the astable multivibrator. The duty cycle is the ratio of the time tc during which the output is high to the total time period T. It is generally expressed in percentage. In equation form,

% duty cycle = [( R1 + R2) / (R1 + 2 R2)] x 100


DEPT OF EEE/PSREC20

PIN DIAGRAM:

CIRCUIT DIAGRAM OF ASTABLE MULTIVIBRATOR


DEPT OF EEE/PSREC21

DESIGN:

[ To design an astable multivibrator with 65% duty cycle at 4 KHz frequency, assume C= 0.01 µF]

Given f= 4 KHz, Therefore, Total time period, T = 1/f = ____________

We know, duty cycle = tc / TTherefore, tc = ------------------------ and td = ____________

We also know for an astable multivibrator td = 0.69 (R2) CTherefore, R2 = _____________

tc = 0.69 (R1 + R2) CTherefore, R1 = _____________

PROCEDURE:

1. Connections are given as per the circuit diagram.2. + 5V supply is given to the + Vcc terminal of the timer IC.3. At pin 3 the output waveform is observed with the help of a CRO4. At pin 6 the capacitor voltage is obtained in the CRO and the V0 and Vc

voltage waveforms are plotted in a graph sheet.

OBSERVATIONS:

S.No Particulars

Amplitude( No. of div x

Volts per div )

Time period( No. of div x

Time per div )

tc td

1.Output Voltage , Vo

2.Capacitor voltage , Vc

MODEL GRAPH:


DEPT OF EEE/PSREC22

RESULT:

The design of the Astable multivibrator circuit was done and the output voltage and capacitor voltage waveforms were obtained.

Expt. No.4 MONOSTABLE MULTIVIBRATOR

AIM:


DEPT OF EEE/PSREC23

To design a monostable multivibrator for the given specifications using 555 Timer IC.

APPARATUS REQUIRED:

S.No Name of the Apparatus Range Quantity1. Function Generator 3 MHz, Analog 12. CRO 30 MHz 13. Dual RPS 0 – 30 V 14. Timer IC IC 555 15. Bread Board 16. Resistors7. Capacitors8. Connecting wires and probes As required

THEORY:

A monostable multivibrator often called a one-shot multivibrator is a pulse generating circuit in which the duration of the pulse is determined by the RC network connected externally to the 555 timer. In a stable or stand-by state the output of the circuit is approximately zero or at logic low level. When an external trigger pulse is applied, the output is forced to go high (approx. Vcc). The time during which the output remains high is given by,

tp = 1.1 R1 C

At the end of the timing interval, the output automatically reverts back to its logic low state. The output stays low until a trigger pulse is applied again. Then the cycle repeats.Thus the monostable state has only one stable state hence the name monostable.

PIN DIAGRAM:

CIRCUIT DIAGRAM OF MONOSTABLE MULTIVIBRATOR:


DEPT OF EEE/PSREC24

DESIGN:

[ To design a monostable multivibrator with tp = 0.616 ms , assume C = 0.01 µF ]

Given tp = 0.616 ms = 1.1 R1 CTherefore, R1 = _____________

PROCEDURE:

1. Connections are given as per the circuit diagram.2. + 5V supply is given to the + Vcc terminal of the timer IC.3. A negative trigger pulse of 5V, 2 KHz is applied to pin 2 of the 555 IC4. At pin 3 the output waveform is observed with the help of a CRO5. At pin 6 the capacitor voltage is obtained in the CRO and the V0 and Vc

voltage waveforms are plotted in a graph sheet.


DEPT OF EEE/PSREC25

OBSERVATIONS:

S.No Particulars

Amplitude( No. of div x

Volts per div )

Time period( No. of div x

Time per div )

ton toff

1. Trigger input

2.Output Voltage , Vo

3.Capacitor voltage , Vc

MODEL GRAPH:

RESULT:

The design of the Monostable multivibrator circuit was done and the input and output waveforms were obtained.

Expt. No.5 STUDY OF BASIC DIGITAL ICS

AIM:


DEPT OF EEE/PSREC26

To verify the truth table of basic digital ICs of AND, OR, NOT, NAND, NOR, EX-OR gates.

APPARATUS REQUIRED:

S.No Name of the Apparatus Range Quantity1. Digital IC trainer kit 12. AND gate IC 7408 13. OR gate IC 7432 14. NOT gate IC 7404 15. NAND gate IC 7400 16. NOR gate IC 7402 17. EX-OR gate IC 7486 18. Connecting wires As required

THEORY:

a. AND gate:

An AND gate is the physical realization of logical multiplication operation. It is an electronic circuit which generates an output signal of ‘1’ only if all the input signals are ‘1’.

b. OR gate:

An OR gate is the physical realization of the logical addition operation. It is an electronic circuit which generates an output signal of ‘1’ if any of the input signal is ‘1’.

c. NOT gate:

A NOT gate is the physical realization of the complementation operation. It is an electronic circuit which generates an output signal which is the reverse of the input signal. A NOT gate is also known as an inverter because it inverts the input.

AND GATE

LOGIC DIAGRAM:


DEPT OF EEE/PSREC27

PIN DIAGRAM OF IC 7408 :

CIRCUIT DIAGRAM:

TRUTH TABLE:

S.NoINPUT OUTPUT

A B Y = A . B1. 0 0 02. 0 1 03. 1 0 04. 1 1 1

OR GATE

LOGIC DIAGRAM:R.MAHENDRAN


28


CIRCUIT DIAGRAM:

TRUTH TABLE:

S.NoINPUT OUTPUT

A B Y = A + B1. 0 0 02. 0 1 13. 1 0 14. 1 1 1

NOT GATE


DEPT OF EEE/PSREC29

LOGIC DIAGRAM:


CIRCUIT DIAGRAM:

TRUTH TABLE:

S.NoINPUT OUTPUT

A Y = A’1. 0 12. 1 0

NAND GATE

LOGIC DIAGRAM:


DEPT OF EEE/PSREC30


CIRCUIT DIARAM:

TRUTH TABLE:

S.NoINPUT OUTPUT

A B Y = (A . B)’1. 0 0 12. 0 1 13. 1 0 14. 1 1 0

NOR GATE

LOGIC DIAGRAM:


DEPT OF EEE/PSREC31


CIRCUIT DIAGRAM:

TRUTH TABLE:

S.NoINPUT OUTPUT

A B Y = (A + B)’1. 0 0 12. 0 1 03. 1 0 04. 1 1 0

EX-OR GATE

LOGIC DIAGRAM


DEPT OF EEE/PSREC32


CIRCUIT DIAGRAM:

TRUTH TABLE:

S.NoINPUT OUTPUT

A B Y = A B1. 0 0 02. 0 1 13. 1 0 14. 1 1 0


DEPT OF EEE/PSREC33

d. NAND gate:

A NAND gate is a complemented AND gate. The output of the NAND gate will be ‘0’ if all the input signals are ‘1’ and will be ‘1’ if any one of the input signal is ‘0’.

e. NOR gate:

A NOR gate is a complemented OR gate. The output of the OR gate will be ‘1’ if all the inputs are ‘0’ and will be ‘0’ if any one of the input signal is ‘1’.

f. EX-OR gate:

An Ex-OR gate performs the following Boolean function,

A B = ( A . B’ ) + ( A’ . B )

It is similar to OR gate but excludes the combination of both A and B being equal to one. The exclusive OR is a function that give an output signal ‘0’ when the two input signals are equal either ‘0’ or ‘1’.

PROCEDURE:

1. Connections are given as per the circuit diagram2. For all the ICs 7th pin is grounded and 14th pin is given +5 V supply.3. Apply the inputs and verify the truth table for all gates.

RESULT:

The truth table of all the basic digital ICs were verified.


DEPT OF EEE/PSREC34

Expt. No.6 IMPLEMENTATION OF BOOLEAN FUNCTIONS

AIM:

To design the logic circuit and verify the truth table of the given Boolean expression,F (A,B,C,D) = Σ (0,1,2,5,8,9,10)

APPARATUS REQUIRED:S.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 12. AND gate IC 74083. OR gate IC 74324. NOT gate IC 74045. NAND gate IC 74006. NOR gate IC 74027. EX-OR gate IC 74868. Connecting wires As required

DESIGN:

Given , F (A,B,C,D) = Σ (0,1,2,5,8,9,10)

The output function F has four input variables hence a four variable Karnaugh Map is used to obtain a simplified expression for the output as shown,

From the K-Map,F = B’ C’ + D’ B’ + A’ C’ DSince we are using only two input logic gates the above expression can be re-written as,F = C’ (B’ + A’ D) + D’ B’Now the logic circuit for the above equation can be drawn.


DEPT OF EEE/PSREC35

CIRCUIT DIAGRAM:

TRUTH TABLE:

S.NoINPUT OUTPUT

A B C DF=D’B’+C’(B’+A’D

)1. 0 0 0 0 12. 0 0 0 1 13. 0 0 1 0 14. 0 0 1 1 05. 0 1 0 0 06. 0 1 0 1 17. 0 1 1 0 08. 0 1 1 1 09. 1 0 0 0 110. 1 0 0 1 111. 1 0 1 0 112. 1 0 1 1 013. 1 1 0 0 014. 1 1 0 1 015. 1 1 1 0 016. 1 1 1 1 0


DEPT OF EEE/PSREC36

PROCEDURE:

1. Connections are given as per the circuit diagram2. For all the ICs 7th pin is grounded and 14th pin is given +5 V supply.3. Apply the inputs and verify the truth table for the given Boolean expression.

RESULT:

The truth table of the given Boolean expression was verified.


DEPT OF EEE/PSREC37

Expt. No. 8 IMPLEMENTATION OF HALF ADDER & FULL ADDER

AIM:

To design and verify the truth table of the Half Adder & Full Adder circuits.

APPARATUS REQUIRED:

S.No Name of the Apparatus Range Quantity1. Digital IC trainer kit 12. AND gate IC 74083. OR gate IC 74324. NOT gate IC 74045. EX-OR gate IC 74866. Connecting wires As required

THEORY:

The most basic arithmetic operation is the addition of two binary digits. There are four possible elementary operations, namely,

0 + 0 = 00 + 1 = 11 + 0 = 1

1 + 1 = 102

The first three operations produce a sum of whose length is one digit, but when the last operation is performed the sum is two digits. The higher significant bit of this result is called a carry and lower significant bit is called the sum.

HALF ADDER:

A combinational circuit which performs the addition of two bits is called half adder. The input variables designate the augend and the addend bit, whereas the output variables produce the sum and carry bits.

FULL ADDER:

A combinational circuit which performs the arithmetic sum of three input bits is called full adder. The three input bits include two significant bits and a previous carry bit. A full adder circuit can be implemented with two half adders and one OR gate.


DEPT OF EEE/PSREC38

HALF ADDER

TRUTH TABLE:

S.NoINPUT OUTPUT

A B S C 1. 0 0 0 02. 0 1 1 03. 1 0 1 04. 1 1 0 1

DESIGN:

From the truth table the expression for sum and carry bits of the output can be obtained as,Sum, S = A BCarry, C = A . B

CIRCUIT DIAGRAM:

FULL ADDER

TRUTH TABLE:

S.NoINPUT OUTPUT

A B C SUM CARRY 1. 0 0 0 0 02. 0 0 1 1 03. 0 1 0 1 04. 0 1 1 0 15. 1 0 0 1 06. 1 0 1 0 17. 1 1 0 0 18. 1 1 1 1 1


DEPT OF EEE/PSREC39

DESIGN:

From the truth table the expression for sum and carry bits of the output can be obtained as,

SUM = A’B’C + A’BC’ + AB’C’ + ABCCARRY = A’BC + AB’C + ABC’ +ABC

Using Karnaugh maps the reduced expression for the output bits can be obtained as,

SUM

SUM = A’B’C + A’BC’ + AB’C’ + ABC = A B C

CARRY

CARRY = AB + AC + BC

CIRCUIT DIAGRAM:


DEPT OF EEE/PSREC40

PROCEDURE:

1. Connections are given as per the circuit diagrams.2. For all the ICs 7th pin is grounded and 14th pin is given +5 V supply.3. Apply the inputs and verify the truth table for the half adder and full adder

circuits.

RESULT:

The design of the half adder and full adder circuits was done and their truth tables were verified.


DEPT OF EEE/PSREC41

Expt. No. 8 IMPLEMENTATION OF HALF SUBTRACTOR &FULL SUBTRACTOR

AIM:

To design and verify the truth table of the Half Subtractor & Full Subtractor circuits.

APPARATUS REQUIRED:

S.No Name of the Apparatus Range Quantity1. Digital IC trainer kit 12. AND gate IC 74083. OR gate IC 74324. NOT gate IC 74045. EX-OR gate IC 74866. Connecting wires As required

THEORY:

The arithmetic operation, subtraction of two binary digits has four possible elementary operations, namely,

0 - 0 = 0 0 - 1 = 1 with 1 borrow

1 - 0 = 11 - 1 = 0

In all operations, each subtrahend bit is subtracted from the minuend bit. In case of the second operation the minuend bit is smaller than the subtrahend bit, hence 1 is borrowed.

HALF SUBTRACTOR:

A combinational circuit which performs the subtraction of two bits is called half subtractor. The input variables designate the minuend and the subtrahend bit, whereas the output variables produce the difference and borrow bits.

FULL SUBTRACTOR:

A combinational circuit which performs the subtraction of three input bits is called full subtractor. The three input bits include two significant bits and a previous borrow bit. A full subtractor circuit can be implemented with two half subtractors and one OR gate.


DEPT OF EEE/PSREC42

HALF SUBTRACTOR

TRUTH TABLE:

S.NoINPUT OUTPUT

A B DIFF BORR 1. 0 0 0 02. 0 1 1 13. 1 0 1 04. 1 1 0 0

DESIGN:

From the truth table the expression for difference and borrow bits of the output can be obtained as,

Difference, DIFF = A BBorrow, BORR = A’ . B

CIRCUIT DIAGRAM:


DEPT OF EEE/PSREC43

FULL SUBTRACTORTRUTH TABLE:

S.NoINPUT OUTPUT

A B C DIFF BORR 1. 0 0 0 0 02. 0 0 1 1 13. 0 1 0 1 14. 0 1 1 0 15. 1 0 0 1 06. 1 0 1 0 07. 1 1 0 0 08. 1 1 1 1 1

DESIGN:

From the truth table the expression for difference and borrow bits of the output can be obtained as,

Difference, DIFF= A’B’C + A’BC’ + AB’C’ + ABCBorrow, BORR = A’BC + AB’C + ABC’ +ABC

Using Karnaugh maps the reduced expression for the output bits can be obtained as,

DIFFERENCE

DIFF = A’B’C + A’BC’ + AB’C’ + ABC = A B C

BORROW

BORR = A’B + A’C + BC


DEPT OF EEE/PSREC44

CIRCUIT DIAGRAM:

PROCEDURE:

1. Connections are given as per the circuit diagrams.2. For all the ICs 7th pin is grounded and 14th pin is given +5 V supply.3. Apply the inputs and verify the truth table for the half subtractor and full

subtractor circuits.

RESULT:

The design of the half subtractor and full subtractor circuits was done and their truth tables were verified.


DEPT OF EEE/PSREC45

Expt. No. 9 CODE CONVERTERS

AIM:

To design and verify the truth table of a three bit binary to gray code converter.

APPARATUS REQUIRED:

S.No Name of the Apparatus Range Quantity1. Digital IC trainer kit 12. EX-OR gate IC 74863. Connecting wires As required

THEORY:

Code converter is a circuit that makes two systems compatible even though each uses different binary codes. There is a wide variety of binary codes used in digital systems. Some of these codes are Binary Coded Decimal, Gray code, Excess- 3 code , ASCII code, etc.

A combinational circuit performs the transformation of a three bit binary to gray code converter by means of logic gates. The input variables are binary bits named as A,B,C with A as the MSB and C as the LSB. The Gray code output bits are termed as X,Y,Zwith X as the MSB and Z as the LSB.

The Gray code is also called as reflective code. The gray coded number corresponding to the decimal number 2n – 1, for any n, differs from gray coded 0 (0000) in one bit position only.

DESIGN:

TRUTH TABLE:

S.NoINPUT - BINARY OUTPUT-GRAYA B C X Y Z

1. 0 0 0 0 0 02. 0 0 1 0 0 13. 0 1 0 0 1 14. 0 1 1 0 1 05. 1 0 0 1 1 06. 1 0 1 1 1 17. 1 1 0 1 0 18. 1 1 1 1 0 0


DEPT OF EEE/PSREC46

From the truth table the expression for the output gray bits are,

X (A, B, C) = Σ (4, 5, 6, 7)Y (A, B, C) = Σ (2, 3, 4, 5)Z (A, B, C) = Σ (1, 2, 5, 6)

Hence obtain the reduced SOP expression using Karnaugh maps as follows,

For X:

X = A

For Y:

Y = A B

For Z:

Z = B C


DEPT OF EEE/PSREC47

CIRCUIT DIAGRAM:

3 BIT BINARY TO GRAY CODE CONVERTER

PROCEDURE:

1. Connections are given as per the circuit diagrams.2. For all the ICs 7th pin is grounded and 14th pin is given +5 V supply.3. Apply the inputs and verify the truth table for the three bit binary to gray

code converter.

RESULT:

The design of the three bit Binary to Gray code converter circuit was done and its truth table was verified.


DEPT OF EEE/PSREC48

Expt. No. 10 PARITY GENERATOR & CHECKER

AIM:

To design and verify the truth table of a three bit Odd Parity generator and checker.

APPARATUS REQUIRED:S.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 12. EX-OR gate IC 74863. NOT gate IC 74044. Connecting wires As required

THEORY:

A parity bit is used for the purpose of detecting errors during transmission of binary information. A parity bit is an extra bit included with a binary message to make the number of 1’s either odd or even. The message including the parity bit is transmitted and then checked at the receiving end for errors. An error is detected if the checked parity does not correspond with the one transmitted. The circuit that generates the parity bit in the transmitter is called a parity generator and the circuit that checks the parity in the receiver is called a parity checker.

In even parity the added parity bit will make the total number of 1’s an even amount and in odd parity the added parity bit will make the total number of 1’s an odd amount.In a three bit odd parity generator the three bits in the message together with the parity bit are transmitted to their destination, where they are applied to the parity checker circuit. The parity checker circuit checks for possible errors in the transmission.

Since the information was transmitted with odd parity the four bits received must have an odd number of 1’s. An error occurs during the transmission if the four bits received have an even number of 1’s, indicating that one bit has changed during transmission. The output of the parity checker is denoted by PEC (parity error check) and it will be equal to 1 if an error occurs, i.e., if the four bits received has an even number of 1’s.


DEPT OF EEE/PSREC49

ODD PARITY GENERATOR

TRUTH TABLE:

S.NoINPUT

( Three bit message)OUTPUT

( Odd Parity bit)

A B C P1. 0 0 0 12. 0 0 1 03. 0 1 0 04. 0 1 1 15. 1 0 0 06. 1 0 1 17. 1 1 0 18. 1 1 1 0

From the truth table the expression for the output parity bit is,

P( A, B, C) = Σ (0, 3, 5, 6)

Also written as,

P = A’B’C’ + A’BC + AB’C + ABC’ = (A B C) ‘

CIRCUIT DIAGRAM:ODD PARITY GENERATOR


DEPT OF EEE/PSREC50

ODD PARITY CHECKERTRUTH TABLE:

S.No

INPUT ( four bit message

Received )

OUTPUT(Parity error

check)A B C P X

1. 0 0 0 0 12. 0 0 0 1 03. 0 0 1 0 04. 0 0 1 1 15. 0 1 0 0 06. 0 1 0 1 17. 0 1 1 0 18. 0 1 1 1 09. 1 0 0 0 010. 1 0 0 1 111. 1 0 1 0 112. 1 0 1 1 013. 1 1 0 0 114. 1 1 0 1 015. 1 1 1 0 016. 1 1 1 1 1

From the truth table the expression for the output parity checker bit is,

X (A, B, C, P) = Σ (0, 3, 5, 6, 9, 10, 12, 15)

The above expression is reduced as,

X = (A B C P) ‘

CIRCUIT DIAGRAM:ODD PARITY CHECKER


DEPT OF EEE/PSREC51

PROCEDURE:

1. Connections are given as per the circuit diagrams.2. For all the ICs 7th pin is grounded and 14th pin is given +5 V supply.3. Apply the inputs and verify the truth table for the Parity generator and

checker.

RESULT:

The design of the three bit odd Parity generator and checker circuits was done and their truth tables were verified.


DEPT OF EEE/PSREC52

Expt. No. 11 MULTIPLEXER & DEMULTIPLEXER

AIM:

To design and verify the truth table of a 4X1 Multiplexer & 1X4 Demultiplexer.

APPARATUS REQUIRED:

S.No Name of the Apparatus Range Quantity1. Digital IC trainer kit 12. OR gate IC 74323. NOT gate IC 74044. AND gate ( three input ) IC 74115. Connecting wires As required

THEORY:

Multiplexer is a digital switch which allows digital information from several sources to be routed onto a single output line. The basic multiplexer has several data input lines and a single output line. The selection of a particular input line is controlled by a set of selection lines. Normally, there are 2n input lines and n selector lines whose bit combinations determine which input is selected. Therefore, multiplexer is ‘many into one’ and it provides the digital equivalent of an analog selector switch.

A Demultiplexer is a circuit that receives information on a single line and transmits this information on one of 2n possible output lines. The selection of specific output line is controlled by the values of n selection lines.

DESIGN:4 X 1 MULTIPLEXER

LOGIC SYMBOL:


DEPT OF EEE/PSREC53

TRUTH TABLE:

S.NoSELECTION

INPUTOUTPUT

S1 S2 Y1. 0 0 I0

2. 0 1 I1

3. 1 0 I2

4. 1 1 I3

PIN DIAGRAM OF IC 7411:

CIRCUIT DIAGRAM:


DEPT OF EEE/PSREC54

1X4 DEMULTIPLEXER

LOGIC SYMBOL:

TRUTH TABLE:


DEPT OF EEE/PSREC55

S.NoINPUT OUTPUT

S1 S2 Din Y0 Y1 Y2 Y31. 0 0 0 0 0 0 02. 0 0 1 1 0 0 03. 0 1 0 0 0 0 04. 0 1 1 0 1 0 05. 1 0 0 0 0 0 06. 1 0 1 0 0 1 07. 1 1 0 0 0 0 08. 1 1 1 0 0 0 1

CIRCUIT DIAGRAM:


DEPT OF EEE/PSREC56

PROCEDURE:

1. Connections are given as per the circuit diagrams.2. For all the ICs 7th pin is grounded and 14th pin is given +5 V supply.3. Apply the inputs and verify the truth table for the multiplexer &

demultiplexer.

RESULT:

The design of the 4x1 Multiplexer and 1x4 Demultiplexer circuits was done and their truth tables were verified.

Expt. No. 12 STUDY OF FLIP FLOPS


DEPT OF EEE/PSREC57

AIM:

To verify the characteristic table of RS, D, JK, and T Flip flops.

APPARATUS REQUIRED:

S.No Name of the Apparatus Range Quantity1. Digital IC trainer kit 12. NOR gate IC 74023. NOT gate IC 74044. AND gate ( three input ) IC 74115. NAND gate IC 74006. Connecting wires As required

THEORY:

A Flip Flop is a sequential device that samples its input signals and changes its output states only at times determined by clocking signal. Flip Flops may vary in the number of inputs they possess and the manner in which the inputs affect the binary states.

RS FLIP FLOP:

The clocked RS flip flop consists of NAND gates and the output changes its state with respect to the input on application of clock pulse. When the clock pulse is high the S and R inputs reach the second level NAND gates in their complementary form. The Flip Flop is reset when the R input high and S input is low. The Flip Flop is set when the S input is high and R input is low. When both the inputs are high the output is in an indeterminate state.

D FLIP FLOP:

To eliminate the undesirable condition of indeterminate state in the SR Flip Flop when both inputs are high at the same time, in the D Flip Flop the inputs are never made equal at the same time. This is obtained by making the two inputs complement of each other.

JK FLIP FLOP:

The indeterminate state in the SR Flip-Flop is defined in the JK Flip Flop. JK inputs behave like S and R inputs to set and reset the Flip Flop. The output Q is ANDed with K input and the clock pulse, similarly the output Q’ is ANDed with J input and the Clock pulse. When the clock pulse is zero both the AND gates are disabled and the Q and Q’ output retain their previous values. When the clock pulse is high, the J and K inputs reach the NOR gates. When both the inputs are high the output toggles continuously. This is called Race around condition and this must be avoided.

T FLIP FLOP:


DEPT OF EEE/PSREC58

This is a modification of JK Flip Flop, obtained by connecting both inputs J and K inputs together. T Flip Flop is also called Toggle Flip Flop.

RS FLIP FLOP

LOGIC SYMBOL:

CIRCUIT DIAGRAM:

CHARACTERISTIC TABLE:

CLOCKPULSE

INPUT PRESENTSTATE (Q)

NEXTSTATE(Q+1)

STATUSS R

1 0 0 0 02 0 0 1 13 0 1 0 04 0 1 1 05 1 0 0 16 1 0 1 17 1 1 0 X8 1 1 1 X

D FLIP FLOP


DEPT OF EEE/PSREC59

LOGIC SYMBOL:

CIRCUIT DIAGRAM:


CLOCKPULSE

INPUTD

PRESENTSTATE (Q)

NEXTSTATE(Q+1)

STATUS

1 0 0 02 0 1 03 1 0 14 1 1 1

JK FLIP FLOPLOGIC SYMBOL:


DEPT OF EEE/PSREC60

CIRCUIT DIAGRAM:

CHARACTERISTIC TABLE:CLOCKPULSE

INPUT PRESENTSTATE (Q)

NEXTSTATE(Q+1)

STATUSJ K

1 0 0 0 02 0 0 1 13 0 1 0 04 0 1 1 05 1 0 0 16 1 0 1 17 1 1 0 18 1 1 1 0

T FLIP FLOP


DEPT OF EEE/PSREC61

LOGIC SYMBOL:

CIRCUIT DIAGRAM:


CLOCKPULSE

INPUTT

PRESENTSTATE (Q)

NEXTSTATE(Q+1)

STATUS

1 0 0 02 0 1 03 1 0 14 1 1 0

PROCEDURE:

1. Connections are given as per the circuit diagrams.2. For all the ICs 7th pin is grounded and 14th pin is given +5 V supply.3. Apply the inputs and observe the status of all the flip flops.

RESULT:

The Characteristic tables of RS, D, JK, T flip flops were verified.

Expt. No. 13 ASYNCHRONOUS DECADE COUNTER


DEPT OF EEE/PSREC62

AIM:

To implement and verify the truth table of an asynchronous decade counter.

APPARATUS REQUIRED:

S.No Name of the Apparatus Range Quantity1. Digital IC trainer kit 12. JK Flip Flop IC 7473 24. NAND gate IC 7400 15. Connecting wires As required

THEORY:

Asynchronous decade counter is also called as ripple counter. In a ripple counter the flip flop output transition serves as a source for triggering other flip flops. In other words the clock pulse inputs of all the flip flops are triggered not by the incoming pulses but rather by the transition that occurs in other flip flops. The term asynchronous refers to the events that do not occur at the same time. With respect to the counter operation, asynchronous means that the flip flop within the counter are not made to change states at exactly the same time, they do not because the clock pulses are not connected directly to the clock input of each flip flop in the counter.


CIRCUIT DIAGRAM:R.MAHENDRAN


63

TRUTH TABLE:

S.NoCLOCKPULSE

OUTPUTD(MSB) C B A(LSB)

1 - 0 0 0 02 1 0 0 0 13 2 0 0 1 04 3 0 0 1 15 4 0 1 0 06 5 0 1 0 17 6 0 1 1 08 7 0 1 1 19 8 1 0 0 010 9 1 0 1 011 10 0 0 0 0

PROCEDURE:

1. Connections are given as per the circuit diagrams.2. Apply the input and verify the truth table of the counter.

RESULT:

The truth table of the Asynchronous decade counter was hence verified.

Expt. No. 14 IMPLEMENTATION OF SHIFT REGISTERSR.MAHENDRAN


64

AIM:

To implement and verify the truth table of a serial in serial out shift register.

APPARATUS REQUIRED:

S.No Name of the Apparatus Range Quantity1. Digital IC trainer kit 12. D Flip Flop IC 7474 23. Connecting wires As required

THEORY:

A register capable of shifting its binary information either to the left or to the right is called a shift register. The logical configuration of a shift register consists of a chain of flip flops connected in cascade with the output of one flip flop connected to the input of the next flip flop. All the flip flops receive a common clock pulse which causes the shift from one stage to the next.

The Q output of a D flip flop is connected to the D input of the flip flop to the left. Each clock pulse shifts the contents of the register one bit position to the right. The serial input determines, what goes into the right most flip flop during the shift. The serial output is taken from the output of the left most flip flop prior to the application of a pulse. Although this register shifts its contents to its left, if we turn the page upside down we find that the register shifts its contents to the right. Thus a unidirectional shift register can function either as a shift right or a shift left register.


CIRCUIT DIAGRAM:R.MAHENDRAN


65

TRUTH TABLE:

For a serial data input of 1101,

S.NO CLOCK PULSE

INPUTS OUTPUTSD1 D2 D3 D4 Q1 Q2 Q3 Q4

1 1 1 X X X 1 X X X2 2 1 1 X X 1 1 X X3 3 0 1 1 X 0 1 1 X4 4 1 0 1 1 1 0 1 15 5 X 1 0 1 X 1 0 16 6 X X 1 0 1 X 1 07 7 X X X 1 0 X X 18 8 X X X X X X X X

PROCEDURE:

1. Connections are given as per the circuit diagrams.2. Apply the input and verify the truth table of the counter.

RESULT:

The truth table of a serial in serial out left shift register was hence verified.


DEPT OF EEE/PSREC66

lic lab manual

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