m16c6s group datasheet - renesas.com

R01DS0201EJ0502 Rev.5.02 page 1 of 203Dec 25, 2012

M16C/6S GroupR01DS0201EJ0502

Rev.5.02Dec 25, 2012SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

OverviewThe M16C/6S group are highly integrated single-chip microcomputers with PLC (Power Line Communica-

tion) modem core and AFE (Analog Front End) in a 64-pin plastic molded LQFP package, which incorpo-

rates IT800 PLC modem technology developed by Yitran Communications Ltd. M16C/60 Series CPU core

enables a high level of code efficiency and high-speed operation. In addition, the implementation of Yitran's

patented DCSK (Differential Code Shift Keying) spread spectrum modulation technique in the IT800 mo-

dem core enables extremely robust communication over the existing electrical wiring, with data rates up to

7.5Kbps. The M16C/6S complies with worldwide regulations (FCC part 15, ARIB and CENELEC bands)

and is suitable for a variety of narrowband applications like smart metering and home networking.

ApplicationsPower Line Communication

Specifications written in this manual are believed to be accurate, but arenot guaranteed to be entirely free of error. Specifications in this manualmay be changed for functional or performance improvements. Please makesure your manual is the latest edition.

------Table of Contents------Overview ......................................................... 1

Memory ......................................................... 10

Central Processing Unit (CPU) ..................... 11

SFR ............................................................... 13

Reset ............................................................. 19

Processor Mode ............................................ 23

Clock Generation Circuit ............................... 27

Protection ...................................................... 46

Interrupts ....................................................... 47

Watchdog Timer ............................................ 66

DMAC ........................................................... 68

Timers ........................................................... 78

Timer A ...................................................... 79

Serial I/O ....................................................... 92

Clock Synchronous serial I/O Mode ........ 101

UART Mode ............................................. 109

Special Mode ........................................... 117

SI/O3 and SI/O4 ...................................... 132

Programmable I/O Ports ............................. 137

Electrical Characteristics ............................. 149

Flash Memory Version ................................ 160

IT800AFE (Analog Front End) .................... 186

Usage Notes ............................................... 191

APPENDIX .................................................. 201

M16C/6S Group Overview


Table 1.1.1. Performance outline of M16C/6S group

Performance OutlineTable 1.1.1 lists performance outline of M16C/6S group.

Item PerformanceCPU Number of basic instructions 91 instructions

Minimum Instruction Execution 65.1 ns (f(BCLK)= 15.36MHZ, VCC= 3.0V to 3.6V)timeOperation Mode Single-chip modeMemory Space 1M ByteMemory Capacity ROM See Tables 1.1.3 and 1.1.4 Product List

RAM 24K BytePeripheral Port Input/Output : 21 pins, Input : 1 pin

Function Multifunction Timer Timer A : 16 bits x 5 channels,Serial I/O 2 channels

Clock synchronous, UART, I2C bus(1),1 channel UART, I2C bus(1),2 channels

Clock synchronous(*)(*) 1 channel is internally connected to IT800

DMAC 2 channelsWatchdog Timer 15 bits x 1 channel (with prescaler)Interrupt 21 internal and 3 external sources, 4 software sources, 7 levelsClock Generation Circuit 2 circuits

Main clock generation circuit with PLL synthesizer (*),On-chip oscillator,(*) This circuit contains a built-in feedback resister.

Electrical Power supply voltage 3.0V to 3.6VCharacteristics Power Consumption 70mA (VCC= VCCA= 3.3V, f(XIN)= 5.12MHz)Flash memory Program/Erase Supply Voltage 3.0V to 3.6V (Topr= 0 to 60°C)Version Program and Erase Endurance 100 timesPower consumption 70mA (VCC= VCCA= 3.3V, f(XIN)= 5.12MHz)Operating Ambient Temperature (2) -20 to 85°C

-40 to 85°C-40 to 105°C

Package 64-pin plastic mold LQFPNotes: 1. I2C Bus is a registered trademark of Koninklijke Philips Electronics N. V. 2. See Tables 1.1.5 and 1.1.6 Product code for version of expanded operating ambient temperature.



IT800 PHY performance outline of M16C/6S group.The IT800 PHY is a PLC optimized Physical Layer (PHY) which consists of IT800 modem core and internal

AFE (Analog Front End). The implementation of Yitran's patented DCSK spread spectrum modulation

technique in the IT800 modem core enables extremely robust communication over the existing electrical

wiring, with data rates up to 7.5Kbps. In addition to the inherent interference immunity provided by the

DCSK modulation, the IT800 PHY utilizes several mechanisms for enhanced communication robustness,

such as forward short block soft decoding error correction algorithm and special synchronization algo-

rithms.

The IT800PHY communicates M16C core with clock synchronous serial I/O, interrupt and input/output

ports in M16C/6S (Note). M16C/6S requires external AFE. Table 1.1.2 lists IT800 PHY performance outline

of M16C/6S group.

Table 1.1.2. IT800 PHY performance outline of M16C/6S group

Item Performance

Features High immunity to signal fading, various noise characteristics,

impedance modulation and phase/frequency distortion

High in-phase and cross-phase reliability

Modulation Technique DCSK (Differential Code Shift Keying)*

*Yitran patented modulation technique

Error Correction/Detection Forward short-block soft decoding error correction mechanism,

CRC-16

Complies with W/W Regulations FCC, ARIB, EN50065-1-CENELEC

Data Rate & FCC & ARIB 120-400 KHz

Frequency Band 7.5Kbps Standard Mode (SM)

5.0Kbps Robust Mode (RM)

1.25Kbps Extremely Robust Mode (ERM)

CENELEC A-Band (Outdoor): 20-80 KHz

B-Band (Indoor): 95-125 KHz

2.5 Kbps Robust Mode (RM)

0.625Kbps Extremely Robust Mode (ERM)

Internal AFE 10bit-D/A converter, preamp,

1bit-A/D converter x 3 channels

Note:Direct operation of IT800 PHY is not recommended. Since the Layer 2 (DLL) handles the channel accessprocedure, using the IT800DLL as such assures coexistence with other IT800 technology based products,regardless of the vendor, protocol and the application. There is NO such coexistence if the device is usedin direct operation of IT800 PHY. Note that the coexistence here is not with other technologies but withother IT800 technology based products. As for details, please refer to the next section and Appendix.

About FirmwareRenesas recommends IT800DLL (Product name: D2DL) as a Data Link Layer (DLL) of M16C/6S group.

The IT800 DLL is a PLC optimized DLL especially for the products based on Yitran's IT800 technology. For

availability of IT800DLL, please contact Renesas technical support representative. For more details about

the IT800DLL advantages, please refer to Appendix.



Block Diagram and PLC application OutlineFigure 1.1.1 is a block diagram of the M16C/6S group and PLC application Outline.

Figure 1.1.1. Block Diagram of Chip and PLC application Outline

10bi

t D/A

Buf

fer

Buf

fer

Com

para

tor

BP

F

SI1

100

to 2

00K

Hz

BP

F

200

to 3

00K

Hz

BP

F

300

to 4

00K

Hz

TX

nRX

DC

LK

DI

DO

CLR

nPH

Y_R

ES

P82

/INT

0nI

NT

nCD

1

nCD

0

EX

TC

LK 1

5.36

MH

z

CLK

_IN

46.

08M

Hz

P40

P42

P95

/CLK

4

P96

/SO

UT

4

P97

/SIN

4

P56

P54

P53

RO

MR

AM

M16

C C

ore

IT80

0 M

odem

Cor

eIn

tern

al A

FE

OPA

MP

AM

P1_

IN

AM

P1_

OU

T

CH

1_IN

N

FB

1

CH

1_IN

P

Com

para

tor

OPA

MP

AM

P2_

IN

AM

P2_

OU

T

CH

2_IN

N

FB

2

CH

2_IN

P

Com

para

tor

OPA

MP

AM

P3_

IN

AM

P3_

OU

T

CH

3_IN

N

FB

3

CH

3_IN

P

VR

EF

PR

E_B

OU

TBU

FF

ER

OPA

MP

VR

EF

PR

E_I

NN

PR

E_I

NP

Pre

ampl

ifier

Vcc

AV

ssA

1bit-

A/D

x 3

IOU

TC

IOU

T

Rex

tLi

neco

uplin

gS

O

PLL

mod

ule

Filt

ers

Line

driv

er

XIN

XO

UT

5.12

MH

z

R0H

R0L

R1H

R1L

R2

R3

A0

A1

FB

SB

US

PIS

PIN

TB

PC

FLG

Mul

tiplie

r

M16

C/6

0 se

ries

16-b

it C

PU

cor

e

Tim

er (

16bi

ts)

Out

put (

Tim

erA

) 5

UA

RT

or

Clo

ck

sync

hron

ous

seria

l I/O

(8bi

ts

3ch

anne

ls)

Clo

ck

sync

hron

ous

seria

l I/O

(8bi

ts

2ch

anne

ls)

Wat

chdo

g tim

er(1

5bits

)

DM

AC

(2ch

anne

ls)

Port P1P

41

P11

P10

TS

TS

TE

ST

_A

TE

ST

_C

Sys

tem

clo

ck

gene

rato

r

10

SI2

SI3

Port P6 Port P7 Port P8 Port P85 Port P9

1 8 5 5 3

Fla

g re

gist

er

Vect

or ta

ble

Pro

gram

Cou

nter

regi

ster

Sta

ck P

oint

er

Blo

ck D

iagr

am o

f Chi

p

Inte

rnal

Per

iphe

rals

Mem

ory

Inne

rPo

r ts



Product ListTables 1.1.3 and 1.1.4 list the M16C/6S group product and Figure 1.1.2 shows the type numbers, memory

sizes and packages.

Table 1.1.3. Product List (1) M16C/6S

Table 1.1.4. Product List (2) M16C/6S D-version

Figure 1.1.2. Type No., Memory Size, and Package

RAM capacityROM capacity Package type RemarksType No.

Current of Dec. 2012

Flash memoryM306S0FAGP PLQP0064KB-A (64P6Q-A)96K bytes 24K bytes

Product Code

U3, U5

RAM capacityROM capacity Package type RemarksType No.

Flash memoryM306S0FADGP PLQP0064KB-A (64P6Q-A)96K bytes 24K bytes

Product Code

U3

Flash memoryM306S0F8DGP PLQP0064KB-A (64P6Q-A)64K bytes 24K bytes U3

Current of Dec. 2012

Package type: GP

Product code See Tables 1.1.5 and 1.1.6 Product code

: Package 64P6Q-A

Version (no) : M16C/6S D : M16C/6S D-version

ROM capacity:

Memory type:

8: 64K bytes A: 96K bytes

F: Flash memory version

Type No. M 3 0 6 S 0 F A D G P – U3

M16C/6S Group

M16C Family

Shows RAM capacity, pin count, etc(The value itself has no specific meaning)



Figure 1.1.3. Marking (Top View)

XXXXXXX

306S0FA U3

YITRAN IT800

Date Code (7 digits) indicates manufacturing management code

Product Name and Product Code

306S0FA indicates M306S0FAGP

U3 indicates product code

U5 has no product code marking

This indicates using Yitran's IT800 technology

(1) M16C/6S

XXXXXXX

M306S0FADGP

YITRAN IT800

Date Code (7 digits) indicates manufacturing management code

Product Name

M306S0FADGP indicates M306S0FADGP U3

This indicates using Yitran's IT800 technology

(2) M16C/6S D-version

Table 1.1.6. Product Code (2) M16C/6S D-version

Microcomputeroperating

temperature

-40°C to 85°C-20°C to 85°C

Temperaturerange

0°C to 60°C

ProductCode

U3

U5

Package

LEAD free

E/W cycles

100

Internal ROM

Table 1.1.5. Product Code (1) M16C/6S

Microcomputeroperating

temperature

-40°C to 105°C

Temperaturerange

0°C to 60°C

ProductCode

U3

Package

LEAD free

E/W cycles

100

Internal ROM



1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33343536373839404142434445464748

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

VC

CA

VS

S

VC

C25

XO

UT

XIN

IFLT

P8 5

P84

/INT

2P

7 6/T

A3O

UT

P8 1

/TA

4IN

P74

/TA

2OU

TP

83/IN

T1

P62

/RX

D0/

SC

L0

PR

E_I

NP

PR

E_I

NN

PR

E_B

OU

T

CNVSS

VSSAVREF

VDCCNAMP1_IN

AMP2_INAMP3_IN

CH3_INP

CH2_INP

CH3_INN

CH2_INN

CH

1_IN

PC

H1_

INN

FB

1

IOU

TC

IOU

TR

EX

TG

ND

/TS

T

NC

3N

C2

NC

1P

1 5/IN

T3

P80

/TA

4OU

T

VC

CA

VC

C

VS

SA

VC

C25

FB3

FB2

AMP3_OUT

AMP1_OUTAMP2_OUT

P63/TXD0/SDA0

P61/CLK0

P91/SIN3

P92/SOUT3P65/CLK1

P70/TXD2/SDA2/TA0OUT(Note)P71/RXD2/SCL2/TA0IN

RESET

VSS

P73/CTS2/RTS2/TA1IN

P64/CTS1/RTS1/CLKS1

P60/CTS0/RTS0P66/RXD1/SCL1

P67/TXD1/SDA1

P90/CLK3

TS

M16C/6SYITRAN IT800

Pin ConfigurationFigures 1.1.4 show the pin configurations (top view).

Package: PLQP0064KB-A (64P6Q-A)

Figure 1.1.4. Pin Configuration (Top View)

PIN CONFIGURATION (top view)

Note: P70 is N channel open-drain output pins.



Table 1.1.7 Pin Description (1)

NOTES:1. In case of Direction Register “1”, any signal is not output from M16C to assigned signal of IT800 .

Refer to Programmable I/O Ports pages.2. Ask the oscillator maker the oscillation characteristic.

VCC, VSS

CNVSS

XIN

XOUT

VCCA

P15

Signal name

Power supply input

CNVSS

Reset input

Clock input

Clock output

Analog powersupply input

I/O port P1

Apply 3.0V to 3.6V to the VCC pin.Apply 0V to the VSS pin.

Function

This is a pin for changing flash memory mode. Usually, connect to VSS.

“L” on this input resets the microcomputer.I/O pins for the main clock generation circuit. Connect a ceramic resonator or crystal oscillator between XIN and XOUT (3). To use the external clock, input the clock from XIN and leave XOUT open.This pin is a power supply input of analog circuit. Connect to VCC.

VCC25 Power supply It is the 2.5V power supply pin which is carrying out internal generating.Connect VCC25 two pins each other and add stabilization capacity.

This is an 1-bit I/O port equivalent to P6. By choosing by the program, it functions as an input pin of INT interrupt.

Pin name

Input

Input

Input

Output

Input/output

I/O type

VSSA Analog powersupply input

This pin is a power supply input of analog circuit. Connect to VSS.

GND/TST Input for test This is input pin for test. Connect to VSS.

P70, P71, P73, P74,P76

I/O port P7 It is an I/O port with a function equivalent to P6 (however, P70 N channel open-drain output). By choosing by the program, it functions as an I/O pin of timers A0 to A3. Moreover, P70 to P73 function also as an I/O pin of UART2.

Input/output

P80, P81, P83, P84, P85

I/O port P8 P80, P81, P83, and P84 are I/O ports with a function equivalent to P6. By choosing by the program, P80 to P81 function as an I/O pin of timer A4, and P83 to P84 functions as an input pin of INT interruption.

Input/output

Input port P85

P85 cannot be used as general input pin. Pull-up resistance cannot set up this pin. This pin must be pulled-up externally to Vcc, and be fixed to “H”.

Input

keep Input

P60 to P67 I/O port P6 This is the 8-bit I/O port of CMOS. It has a direction register for choosing I/O, and is made for every pin in an input port or an output port. An input port can choose the existence of pull-up resistance in a 4-bit unit by the program. It functions as an I/O pin of what is chosen by the program which are therefore UART0 and UART1.

It is an I/O port with a function equivalent to P6. It functions as an I/O pin of SILO3 by choosing by the program.

Input/output

P9

TS

0 to P92 I/O port P9

Inner port P10

Input/output

Port for IT800 Testing. Please set Direction Register PD1_0 “0” for keeping Input.P10

keep InputInner port P11 Port for AFE Testing. Please set Direction Register PD1_1 “0” for keeping Input.P11

P40 Output to IT800

Inner port P40

I/O Port for communication between M16C Core and IT800 Modem. Please set Direction Register PD4_0 “1” to Output a signal to IT800. The output signal is connected to TXnRX of IT800 inside of chip.

P41 Input from IT800

Inner port P41

I/O Port for communication between M16C Core and IT800 Modem (Note.1). Please set Direction Register PD4_1 “0” to Input a signal from IT800. The TS signal isinput from IT800 inside of chip.

P42 Output to IT800

Inner port P42

I/O Port for communication between M16C Core and IT800 Modem. Please set Direction Register PD4_2 “1” to Output a signal to IT800. The output signal is connected to CLR of IT800 inside of chip.


Inner port P53

I/O Port for communication between M16C Core and IT800 Modem (Note.1). Please set Direction Register PD5_3 “0” to Input a signal from IT800. The nCD0 signal is input from IT800 inside of chip.


Inner port P54

I/O Port for communication between M16C Core and IT800 Modem (Note.1). Please set Direction Register PD5_4 “0” to Input a signal from IT800. The nCD1 signal is input from IT800 inside of chip.

P56 Output to IT800

Inner port P56

I/O Port for communication between M16C Core and IT800 Modem. Please set Direction Register PD5_6 “1” to Output a signal to IT800. The output signal is connected to nPHY_RES of IT800 inside of chip.


Inner port P82

I/O Port for communication between M16C Core and IT800 Modem (Note.1). nINT signal of IT800 is connected to this port inside of chip for carrying out Interrupt function by software.

P95 Output to IT800

Inner port P95

I/O Port for communication between M16C Core and IT800 Modem. This port is connected to DCLK signal of IT800 inside of chip as SILO4 CLK4 functional Output port by choosing by the program.

P96 Output to IT800

Inner port P96

I/O Port for communication between M16C Core and IT800 Modem. This port is connected to DI signal of IT800 inside of chip as SILO4 SOUT4 functional Output port by choosing by the program.


Inner port P97

I/O Port for communication between M16C Core and IT800 Modem. This port is connected to DI signal of IT800 inside of chip as SILO4 SOUT4 functional Input port by choosing by the program.

This is the pin with which IT800 controls ON/OFF of an output to the external transmission AMP at the time of power line communication.

Output port TS

Output

RESET

Input



Table 1.1.8 Pin Description (2) (Analog pin)

PRE-BOUT

Pin name I/O type

Output

PRE-INN

PRE-INP

VREF

VDCCN

AMP1-IN

AMP1-OUT

AMP2-IN

AMP2-OUT

AMP3-IN

AMP3-OUT

CHI-INP

CHI-INN

FB1

CH2-INP

CH2-INN

FB2

CH3-INP

CH3-INN

FB3

IOUTC

IOUT

REXT

IFLT

Input

Input

Function

This is a pre-amp buffer output.

This is a pre-amp differential signal input.

This is a pre-amp differential signal input.

This is the reference voltage input of amplifier common to channels 1, 2, and 3.

This is a pin for a test. Usually, please carry out a pull-up.

This is a channel 1 amplifier input.

This is a channel 1 amplifier output.





This is a channel 1 comparator differential input.


This is a channel 1 comparator feedback output.







This is the differential current output of DAC.

This is the differential current output of DAC.

This is for external reference resistor of DAC.

This is the pin for low path filters of PLL.

Input

Input

Input

Output

Input

Output

Input

Output

Input

Input

Output

Input

Input

Output

Input

Input

Output

Output

Output

Input

Input

M16C/6S Group Memory


MemoryFigure 1.2.1 is a memory map of the M16C/6S group. The address space extends the 1M bytes from

address 0000016 to FFFFF16.

The internal ROM is allocated in a lower address direction beginning with address FFFFF16. For example,

a 96-Kbyte internal ROM is allocated to the addresses from E800016 to FFFFF16.

The fixed interrupt vector table is allocated to the addresses from FFFDC16 to FFFFF16. Therefore, store

the start address of each interrupt routine here.

The internal RAM is allocated in an upper address direction beginning with address 0040016. For example,

a 24-Kbytes internal RAM is allocated to the addresses from 0040016 to 063FF16. In addition to storing

data, the internal RAM also stores the stack used when calling subroutines and when interrupts are gener-

ated.

The SRF is allocated to the addresses from 0000016 to 003FF16. Peripheral function control registers are

located here. Of the SFR, any area which has no functions allocated is reserved for future use and cannot

be used by users.

The special page vector table is allocated to the addresses from FFE0016 to FFFDB16. This vector is used

by the JMPS or JSRS instruction. For details, refer to the “M16C/60, M16C/20, and M16C/Tiny Series

Software Manual.”

Figure 1.2.1. Memory Map

0000016

XXXXX16

Internal ROM

SFR

Internal RAM

Can not Use

FFE0016

FFFDC16

FFFFF16

Undefined instruction

OverflowBRK instructionAddress match

Single stepWatchdog timer

Reset

Special pagevector table

DBCReserved

Address XXXXX16Size Address YYYYY16Size

E80001696K bytes

F00001664K bytes

0040016

YYYYY16

FFFFF16

063FF1624K bytes

Internal RAM Internal ROM

Note 1: Shown here is a memory map for the case where the PM13 bit in the PM1 register is “1”.

M16C/6S Group Central Processing Unit (CPU)


Central Processing Unit (CPU)Figure 1.3.1 shows the CPU registers. The CPU has 13 registers. Of these, R0, R1, R2, R3, A0, A1 and FB

comprise a register bank. There are two register banks.

Figure 1.3.1. Central Processing Unit Register

(1) Data Registers (R0, R1, R2 and R3)The R0 register consists of 16 bits, and is used mainly for transfers and arithmetic/logic operations. R1 to

R3 are the same as R0.

The R0 register can be separated between high (R0H) and low (R0L) for use as two 8-bit data registers.

R1H and R1L are the same as R0H and R0L. Conversely, R2 and R0 can be combined for use as a 32-

bit data register (R2R0). R3R1 is the same as R2R0.

(2) Address Registers (A0 and A1)

The register A0 consists of 16 bits, and is used for address register indirect addressing and address register

relative addressing. They also are used for transfers and logic/logic operations. A1 is the same as A0.

In some instructions, registers A1 and A0 can be combined for use as a 32-bit address register (A1A0).

Data registers (Note)

Address registers (Note)

Frame base registers (Note)

Program counter

Interrupt table register

User stack pointer

Interrupt stack pointer

Static base register

Flag register

Note: These registers comprise a register bank. There are two register banks.

R0H(R0's high bits)b15 b8 b7 b0

R3

INTBH

USP

ISP

SB

CDZSBOIUIPL

R0L(R0's low bits)

R1H(R1's high bits)R1L(R1's low bits)

R2b31

R3

R2

A1

A0

FB

b19

INTBLb15 b0

PCb19 b0

b15 b0

FLGb15 b0

b15 b0 b7 b8

Reserved area

Carry flag

Debug flag

Zero flag

Sign flag

Register bank select flag

Overflow flag

Interrupt enable flag

Stack pointer select flag

Reserved area

Processor interrupt priority level

The upper 4 bits of INTB are INTBH and the lower 16 bits of INTB are INTBL.

M16C/6S Group Central Processing Unit (CPU)


(3) Frame Base Register (FB)FB is configured with 16 bits, and is used for FB relative addressing.

(4) Interrupt Table Register (INTB)

INTB is configured with 20 bits, indicating the start address of an interrupt vector table.

(5) Program Counter (PC)

PC is configured with 20 bits, indicating the address of an instruction to be executed.

(6) User Stack Pointer (USP) and Interrupt Stack Pointer (ISP)

Stack pointer (SP) comes in two types: USP and ISP, each configured with 16 bits.

Your desired type of stack pointer (USP or ISP) can be selected by the U flag of FLG.

(7) Static Base Register (SB)SB is configured with 16 bits, and is used for SB relative addressing.

(8) Flag Register (FLG)

FLG consists of 11 bits, indicating the CPU status.

• Carry Flag (C Flag)

This flag retains a carry, borrow, or shift-out bit that has occurred in the arithmetic/logic unit.

• Debug Flag (D Flag)

The D flag is used exclusively for debugging purpose. During normal use, it must be set to “0”.

• Zero Flag (Z Flag)

This flag is set to “1” when an arithmetic operation resulted in 0; otherwise, it is “0”.

• Sign Flag (S Flag)

This flag is set to “1” when an arithmetic operation resulted in a negative value; otherwise, it is “0”.

• Register Bank Select Flag (B Flag)

Register bank 0 is selected when this flag is “0” ; register bank 1 is selected when this flag is “1”.

• Overflow Flag (O Flag)

This flag is set to “1” when the operation resulted in an overflow; otherwise, it is “0”.

• Interrupt Enable Flag (I Flag)

This flag enables a maskable interrupt.

Maskable interrupts are disabled when the I flag is “0”, and are enabled when the I flag is “1”. The I

flag is cleared to “0” when the interrupt request is accepted.

• Stack Pointer Select Flag (U Flag)

ISP is selected when the U flag is “0”; USP is selected when the U flag is “1”.

The U flag is cleared to “0” when a hardware interrupt request is accepted or an INT instruction for

software interrupt Nos. 0 to 31 is executed.

• Processor Interrupt Priority Level (IPL)

IPL is configured with three bits, for specification of up to eight processor interrupt priority levels from

level 0 to level 7.

If a requested interrupt has priority greater than IPL, the interrupt is enabled.

• Reserved Area

When write to this bit, write "0". When read, its content is indeterminate.

M16C/6S Group SFR


SFR

DMA0 control register DM0CON 00000?002

DMA0 transfer counter TCR0 ??16 ??16

DMA1 control register DM1CON 00000?002

DMA1 source pointer SAR1 ??16 ??16 X?16

DMA1 transfer counter TCR1 ??16 ??16

DMA1 destination pointer DAR1 ??16 ??16 X?16

Watchdog timer start register WDTS ??16 Watchdog timer control register WDC 00??????2

Processor mode register 0 (Note 2) PM0

System clock control register 0 CM0 010010002 System clock control register 1 CM1 001000002

Address match interrupt enable register AIER XXXXXX002 Protect register PRCR XX0000002

Processor mode register 1 PM1 00XX10X02

DMA0 destination pointer DAR0 ??16 ??16 X?16

Note 1: The blank areas are reserved and cannot be used by users.Note 2: The PM00 and PM01 bits do not change at software reset, watchdog timer reset and oscillation stop detection reset.Note 3: The CM20, CM21, and CM27 bits do not change at oscillation stop detection reset.X : Nothing is mapped to this bit? : Undefined

Oscillation stop detection register (Note 3) CM2 0000X0002

Processor mode register 2 PM2 XXX000002

000016

000116

000216

000316

000416

000516

000616

000716

000816

000916

000A16

000B16

000C16

000D16

000E16

000F16

001016

001116

001216

001316

001416

001516

001616

001716

001816

001916

001A16

001B16

001C16

001D16

001E16

001F16

002016

002116

002216

002316

002416

002516

002616

002716

002816

002916

002A16

002B16

002C16

002D16

002E16

002F16

003016

003116

003216

003316

003416

003516

003616

003716

003816

003916

003A16

003B16

003C16

003D16

003E16

003F16

Address Register Symbol After reset

Address match interrupt register 0 RMAD0 0016 0016 X016


DMA0 source pointer SAR0 ??16 ??16 X?16

XXXX0X002 (CNVSS pin is “L”)

M16C/6S Group SFR


Timer A1 interrupt control register TA1IC XXXX?0002

UART0 transmit interrupt control register S0TIC XXXX?0002



UART0 receive interrupt control register S0RIC XXXX?0002 UART1 transmit interrupt control register S1TIC XXXX?0002UART1 receive interrupt control register S1RIC XXXX?0002

DMA1 interrupt control register DM1IC XXXX?0002DMA0 interrupt control register DM0IC XXXX?0002

UART2 Bus collision detection interrupt control register BCNIC XXXX?0002

UART2 transmit interrupt control register S2TIC XXXX?0002UART2 receive interrupt control register S2RIC XXXX?0002

INT1 interrupt control register INT1IC XX00?0002






UART1 BUS collision detection interrupt control register U1BCNIC XXXX?0002 UART0 BUS collision detection interrupt control register U0BCNIC XXXX?0002 SI/O4 interrupt control register (S4IC) S4IC XX00?0002

SI/O3 interrupt control register S3IC XX00?0002

Note :The blank areas are reserved and cannot be used by users.

X : Nothing is mapped to this bit? : Undefined

004016

004116

004216

004316

004416

004516

004616

004716

004816

004916

004A16

004B16

004C16

004D16

004E16

004F16

005016

005116

005216

005316

005416

005516

005616

005716

005816

005916

005A16

005B16

005C16

005D16

005E16

005F16

006016

006116

006216

006316

006416

006516

006616

006716

006816

006916

006A16

006B16

006C16

006D16

006E16

006F16

007016

007116

007216

007316

007416

007516

007616

007716

007816

007916

007A16

007B16

007C16

007D16

007E16

007F16


M16C/6S Group SFR


008016

008116

008216

008316

008416

008516

008616

01B016

01B116

01B216

01B316

01B416

01B516

01B616

01B716

01B816

01B916

01BA16

01BB16

01BC16

01BD16

01BE16

01BF16

025016

025116

025216

025316

025416

025516

025616

025716

025816

025916

025A16

025B16

025C16

025D16

025E16

025F16

033016

033116

033216

033316

033416

033516

033616

033716

033816

033916

033A16

033B16

033C16

033D16

033E16

033F16

Note 1: The blank areas are reserved and cannot be used by users.


Peripheral clock select register PCLKR 000000112

Flash memory control register 0 FMR0 ??0000012

Flash memory control register 1 FMR1 0?00??0?2



Address match interrupt enable register 2 AIER2 XXXXXX002


~~ ~~

~~ ~~

~~ ~~

M16C/6S Group SFR


Address Register Symbol After reset034016

034116

034216

034316

034416

034516

034616

034716

034816

034916

034A16

034B16

034C16

034D16

034E16

034F16

035016

035116

035216

035316

035416

035516

035616

035716

035816

035916

035A16

035B16

035C16

035D16

035E16

035F16

036016

036116

036216

036316

036416

036516

036616

036716

036816

036916

036A16

036B16

036C16

036D16

036E16

036F16

037016

037116

037216

037316

037416

037516

037616

037716

037816

037916

037A16

037B16

037C16

037D16

037E16

037F16

Interrupt cause select register IFSR 0016 SI/O3 transmit/receive register S3TRR ??16

SI/O4 transmit/receive register S4TRR ??16

SI/O3 control register S3C 010000002 SI/O3 bit rate generator S3BRG ??16

SI/O4 bit rate generator S4BRG ??16

SI/O4 control register S4C 010000002

UART2 special mode register U2SMR X00000002

UART2 receive buffer register U2RB ????????2 ?????XX?2

UART2 transmit buffer register U2TB ????????2 XXXXXXX?2UART2 transmit/receive control register 0 U2C0 000010002

UART2 transmit/receive mode register U2MR 0016

UART2 transmit/receive control register 1 U2C1 000000102

UART2 bit rate generator U2BRG ??16

UART2 special mode register 2 U2SMR2 X00000002

Note : The blank areas are reserved and cannot be used by users.X : Nothing is mapped to this bit? : Undefined

UART2 special mode register 3 U2SMR3 000X0X0X2

Interrupt cause select register 2 IFSR2A 00XXXXXX2



UART0 special mode register 3 U0SMR3 000X0X0X2UART0 special mode register 4 U0SMR4 0016



UART1 special mode register 3 U1SMR3 000X0X0X2

UART1 special mode register 4 U1SMR4 0016

UART2 special mode register 4 U2SMR4 0016

M16C/6S Group SFR


038016

038116

038216

038316

038416

038516

038616

038716

038816

038916

038A16

038B16

038C16

038D16

038E16

038F16

039016

039116

039216

039316

039416

039516

039616

039716

039816

039916

039A16

039B16

039C16

039D16

039E16

039F16

03A016

03A116

03A216

03A316

03A416

03A516

03A616

03A716

03A816

03A916

03AA16

03AB16

03AC16

03AD16

03AE16

03AF16

03B016

03B116

03B216

03B316

03B416

03B516

03B616

03B716

03B816

03B916

03BA16

03BB16

03BC16

03BD16

03BE16

03BF16

Timer A0 register TA0 ??16 ??16Timer A1 register TA1 ??16 ??16Timer A2 register TA2 ??16 ??16

Count start flag TABSR 0016

One-shot start flag ONSF 0016

Timer A0 mode register TA0MR 0016Timer A1 mode register TA1MR 0016Timer A2 mode register TA2MR 0016

Up-down flag UDF 0016

Timer A3 register TA3 ??16 ??16Timer A4 register TA4 ??16 ??16

Timer A3 mode register TA3MR 0016Timer A4 mode register TA4MR 0016

Trigger select register TRGSR 0016

UART0 transmit/receive mode register U0MR 0016

UART0 transmit buffer register U0TB ????????2 XXXXXXX?2

UART0 receive buffer register U0RB ????????2 ?????XX?2UART1 transmit/receive mode register U1MR 0016

UART1 transmit buffer register U1TB ????????2 XXXXXXX?2

UART1 receive buffer register U1RB ????????2 ?????XX?2


UART0 transmit/receive control register 0 U0C0 000010002UART0 transmit/receive control register 1 U0C1 000000102


UART1 transmit/receive control register 0 U1C0 000010002UART1 transmit/receive control register 1 U1C1 000000102

DMA1 request cause select register DM1SL 0016

DMA0 request cause select register DM0SL 0016

UART transmit/receive control register 2 UCON X00000002

Note : The blank areas are reserved and cannot be used by users.X : Nothing is mapped to this bit? : Undefined


M16C/6S Group SFR


03C016

03C116

03C216

03C316

03C416

03C516

03C616

03C716

03C816

03C916

03CA16

03CB16

03CC16

03CD16

03CE16

03CF16

03D016

03D116

03D216

03D316

03D416

03D516

03D616

03D716

03D816

03D916

03DA16

03DB16

03DC16

03DD16

03DE16

03DF16

03E016

03E116

03E216

03E316

03E416

03E516

03E616

03E716

03E816

03E916

03EA16

03EB16

03EC16

03ED16

03EE16

03EF16

03F016

03F116

03F216

03F316

03F416

03F516

03F616

03F716

03F816

03F916

03FA16

03FB16

03FC16

03FD16

03FE16

03FF16

Note 1: The blank areas are reserved and cannot be used by users.


Port P1 register P1 ??16

Port P1 direction register PD1 0016

Port P4 register P4 ??16

Port P4 direction register PD4 0016Port P5 register P5 ??16




Port P8 direction register PD8 00X000002Port P9 register P9 ??16

Port P9 direction register PD9 0016

Pull-up control register 0 PUR0 0016Pull-up control register 1 PUR1 000000002

Pull-up control register 2 PUR2 0016

Port control register PCR 0016

Register Symbol After resetAddress

M16C/6S Group Reset


ResetThere are four types of resets: a hardware reset, a software reset, an watchdog timer reset, and an oscilla-

tion stop detection reset.

Hardware Reset____________ ____________

A reset is applied using the RESET pin. When an “L” signal is applied to the RESET pin while the

power supply voltage is within the recommended operating condition, the pins are initialized (see

Table 1.5.1). The oscillation circuit is initialized and the main clock starts oscillating. When the input____________

level at the RESET pin is released from “L” to “H”, the CPU and SFR are initialized, and the program

is executed starting from the address indicated by the reset vector. The internal RAM is not initialized.____________

If the RESET pin is pulled “L” while writing to the internal RAM, the internal RAM becomes indetermi-

nate.

Figure 1.5.1 shows the example reset circuit. Figure 1.5.2 shows the reset sequence. Table 1.5.1____________

shows the statuses of the other pins while the RESET pin is “L”. Figure 1.5.3 shows the CPU register

status after reset. Refer to “SFR” for SFR status after reset.

1. When the power supply is stable____________

(1) Apply an “L” signal to the RESET pin.

(2) Supply a clock for 20 cycles or more to the XIN pin.____________

(3) Apply an “H” signal to the RESET pin.

2. Power on____________

(1) Apply an “L” signal to the RESET pin.

(2) Let the power supply voltage increase until it meets the recommended operating condition.

(3) Wait td(P-R) or more until the internal power supply stabilizes.

(4) Supply a clock for 20 cycles or more to the XIN pin.____________


M16C/6S Group Reset


Software ResetWhen the PM03 bit in the PM0 register is set to “1” (microcomputer reset), the microcomputer has its pins,

CPU, and SFR initialized. Then the program is executed starting from the address indicated by the reset

vector.

Select the main clock for the CPU clock source, and set the PM03 bit to “1” with main clock oscillation

satisfactorily stable.

At software reset, some SFR’s are not initialized. Refer to “SFR”. Also, since the PM01 to PM00 bits in the

PM0 register are not initialized, the processor mode remains unchanged.

Figure 1.5.1. Example Reset Circuit

R

E

S

E

T VC

C

R

E

S

E

T

VC

C

0 V

0 V

M

o

r

e

t

h

a

n

2

0

c

y

c

l

e

s

o

f

XI

N

+

t

d

(

P

-

R

)

a

r

e

n

e

e

d

e

d

.

E

q

u

a

l

t

o

o

r

l

e

s

s

t

h

a

n

0

.

2

VC

C

E

q

u

a

l

t

o

o

r

l

e

s

s

t

h

a

n

0

.

2

VC

C

Re

c

o

m

m

e

n

d

e

d

o

p

e

r

a

t

i

n

gv

o

l

t

a

g

e

Watchdog Timer ResetWhere the PM12 bit in the PM1 register is “1” (reset when watchdog timer underflows), the microcom-

puter initializes its pins, CPU and SFR if the watchdog timer underflows. Then the program is executed

starting from the address indicated by the reset vector.

At watchdog timer reset, some SFR’s are not initialized. Refer to “SFR”. Also, since the PM01 to PM00

bits in the PM0 register are not initialized, the processor mode remains unchanged.

Oscillation Stop Detection ResetWhere the CM27 bit in the CM2 register is “0” (reset at oscillation stop detection), the microcomputer

initializes its pins, CPU and SFR, coming to a halt if it detects main clock oscillation circuit stop. Refer to

the section “oscillation stop, re-oscillation detection function”.

At oscillation stop detection reset, some SFR’s are not initialized. Refer to the section “SFR”. Also, since

the PM01 to PM00 bits in the PM0 register are not initialized, the processor mode remains unchanged.

M16C/6S Group Reset


Figure 1.5.2. Reset Sequence

td(P-R) More than20 cyclesare needed

BCLK

Internal address

Single chip mode

XIN

RESET

Content of reset vector

BCLK 28cycles

FFFFE16

FFFFC16

VCC1

M16C/6S Group Reset


____________

Table 1.5.1. Pin Status When RESET Pin Level is “L”

Status

CNVSS = VSSPin name

P15,P60 to P67,P70, P71, P73,P74, P76,P80, P81, P83, P84, P85,P90 to P92,TS

Input port

Figure 1.5.3. CPU Register Status After Reset

b15 b0

Data register(R0)

Address register(A0)

Frame base register(FB)

Program counter(PC)

Interrupt table register(INTB)

User stack pointer(USP)

Interrupt stack pointer(ISP)

Static base register(SB)

Flag register(FLG)

000016

000016

000016

CDZSBOIUIPL

000016

000016

000016

000016

000016

b19 b0

Content of addresses FFFFE16 to FFFFC16

b15 b0

b15 b0

b15 b0 b7 b8

0000016

Data register(R1)

Data register(R2)

Data register(R3)

Address register(A1)

000016

000016

000016

M16C/6S Group Processor Mode


Table 1.6.2. PM01 to PM00 Bits Set Values and Processor Modes

Figure 1.6.4 show the memory map in single chip mode.

Processor Mode(1) Setting Processor Modes

Processor mode is available only: single-chip mode.

Processor mode is set by using the CNVSS pin and the PM01 to PM00 bits in the PM0 register.

Table 1.6.1 shows the processor mode after hardware reset. Table 1.6.2 shows the PM01 to PM00 bits

set values and processor modes. For setting Single-chip mode. CNVss should be kept Vss level. And

PM01 to PM00 of PM0 register should be set "00."

Table 1.6.1. Processor Mode After Hardware Reset

CNVSS pin input level Processor modeVSS Single-chip modeVCC Flash Memory Mode

PM01 to PM00 bits Processor modes

Single-chip mode

Must not be set

002

012

102

112



P15

TR

RESET

THOLDTsetup

(2) Setting PLC ModePLC mode is simply set by putting P15 High level during RESET.

Figure 1.6.1. PLC mode by P15 simply setting

min typ max

40us TR

5us

5us

Tset up

THOLD

Table 1.6.3. RESET and P15 Input



Figure 1.6.3. PM1 Register

Figure 1.6.2. PM0 Register

Processor mode register 0 (Note 1)

Symbol Address After reset (Note 2)PM0 000416 XXXX0X002 (CNVSS pin = “L”)

Bit name FunctionBit symbol RW

b7 b6 b5 b4 b3 b2 b1 b0

0 0: Single-chip mode0 1: Must not be set1 0: Must not be set1 1: Must not be set

b1 b0

PM03

PM01

(b2)

PM00 Processor mode bit(Note 2)

Nothing is assigned. When write, set to “0”. When read, its content is indeterminate.

Software reset bit Setting this bit to “1” resets the microcomputer. When read, its content is “0”.

RW

RW

RW

Note 1: Write to this register after setting the PRC1 bit in the PRCR register to "1" (write enable).Note 2: The PM01 to PM00 bits do not change at software reset, watchdog timer reset and oscillation stop

detection reset.

(b7-b4)Nothing is assigned. When write, set to “0”. When read, their contents are indeterminate.


Symbol Address After resetPM1 000516 00XX10X02


b7 b6 b5 b4 b3 b2 b1 b0

RW

Note 1: Write to this register after setting the PRC1 bit in the PRCR register to “1” (write enable).Note 2: PM12 bit is set to “1” by writing a “1” in a program. (Writing a “0” has no effect.) Note 3: When PM17 bit is set to “1” (with wait state), one wait state is inserted when accessing the internal RAM,

internal ROM, or an external area.

PM17 Wait bit (Note 3) 0 : No wait state 1 : With wait state (1 wait)

Internal reserved area expansion bit

PM13

Should be set to “0”.

Should be set to “1”.

0 : Watchdog timer interrupt 1 : Watchdog timer reset (Note 2)

Watchdog timer function select bit

PM12 RW

RW

RW

(b6)Reserved bit RW

0 01

(b2)Nothing is assigned. When write, set to “0”. When read, its content is indeterminate.

(b5-b4)Nothing is assigned. When write, set to “0”. When read, its content is indeterminate.

Should be set to “0”. (b0) Reserved bit



Single-chip mode

SFR

Internal RAM

Can not use

Internal ROM

0000016

0040016

XXXXX16

YYYYY16

FFFFF16

Note 1: Since internal RAM which can be used becomes 15 K bytes when PM13 is “0”, please be sure to set PM13 to “1”.

PM13=1 (Note1)

24K bytes 063FF16

Internal RAM Internal ROM

96K bytes E800016

64K bytes F000016

Capacity Capacity Address YYYYY16Address XXXXX16

Figure 1.6.4. Memory Map in Single Chip Mode

M16C/6S Group Clock Generation Circuit


• CPU clock source• Peripheral function

clock source

Use of clock

Main clock oscillation circuitItem

Clock frequency 5.12 MHz

• Crystal oscillator (Note 1)Usable oscillator

XIN, XOUTPins to connect oscillator

NoOscillation stop,restart function

OscillatingOscillator status after reset

Externally derived clock can be inputOther

On-chip Oscillator

• CPU clock source• Peripheral function clock source

About 1 MHz

Presence

Stopped

Note. Operating frequency must be 5.12 MHz, overall accuracy must be less than 150 ppm.

Clock Generation CircuitThe clock generation circuit contains two oscillator circuits as follows:

(1) Main clock oscillation circuit

(2) On-chip Oscillator (oscillation stop detect function)

Table 1.7.1 lists the clock generation circuit specifications. Figure 1.7.1 shows the clock generation circuit.

Figures 1.7.2 to 1.7.5 show the clock-related registers.

Table 1.7.1. Clock Generation Circuit Specifications



Figure 1.7.1. Clock Generation Circuit

Pulse generation circuit for clock edge detection and charge, discharge control

Charge, dischargecircuit

Resetgenerating circuit

Oscillation stop, re-oscillationdetection interruptgenerating circuit

Mainclock

Oscillation stopdetection reset

CM27 0

1

CM21 switch signal

Oscillation stop, re-oscillationdetection signal

Oscillation stop, re-oscillation detection circuit(Note)

Note. Even if XIN input stops, PLL does not stop. Oscillation stop, re-oscillation detect circuit does not function.

CM02, CM04, CM05, CM06, CM07: CM0 register bitsCM10, CM11, CM16, CM17: CM1 register bitsPCLK0, PCLK1: PCLK register bitsCM21, CM27 : CM2 register bits

CM02

CM10=1(stop mode) QS

R

WAIT instruction

QS

R

Interrupt request level judgment output

RESET

Software reset

CPU clock

CM07=0Divider

a d

1/2 1/2 1/2 1/2

CM06=0CM17–CM16=002

CM06=0CM17–CM16=012

CM06=0CM17–CM16=102

CM06=1

CM06=0CM17–CM16=112

d

a

Details of divider

f8

f32

cb

b

1/2

c

f32SIO

f8SIO

fAD

f1

e

e

1/2 1/4 1/8 1/161/32

PCLK0=1

CM21=1

CM21=0

On-chip oscillator

On-chip oscillatorclock

BCLK

PCLK0=0f2

f1SIOPCLK1=1

PCLK1=0f2SIO

Main clock

CM21

Oscillation stop, re-oscillation detection circuit

XOUTXIN

5.12MHz

Normal operation mode(15.36MHz)IT800 CLK_IN

1/3

Standard serial I/O mode(5.12MHz)

PLL46.08MHz



System clock control register 0 (Notes 1 and 4)

Symbol Address After reset CM0 000616 010010002

Bit name FunctionBit symbol

b7 b6 b5 b4 b3 b2 b1 b0

CM02

CM06

WAIT peripheral function clock stop bit (Note 3)

0 : Do not stop peripheral function clock in wait mode1 : Stop peripheral function clock in wait mode

Main clock division select bit 0 (Notes 5, 13)

0 : CM16 and CM17 valid1 : Division by 8 mode

Note 1: Write to this register after setting the PRC0 bit of PRCR register to “1” (write enable).Note 2: When entering stop mode from high or middle speed mode, On-chip Oscillator mode or On-chip Oscillator low power mode, the CM06 bit is set to “1” (divide-by-8 mode).

Note 3: When the PM21 bit of PM2 register is set to “1” (clock modification disable), writing to the CM02 bits has no effect.

Note 4: To use the main clock as the clock source for the CPU clock, follow the procedure below. (1) Wait until td(M-L) elapses or the main clock oscillation stabilizes, whichever is longer. (2) Set the CM21 to “0”. Note 5: During On-chip Oscillator low power dissipation mode, the divide-by-n value can be selected using the CM06 and CM17 to

CM16 bits. To return to high or middle speed mode, however, set the CM06 bit to “1”, before selecting the desired mode.

RW

RW

RW

RW

RW



(b7)

(b5)

Should be set to “0”. Reserved bit

Should be set to “0”. Reserved bit

0 0

Figure 1.7.2. CM0 Register



System clock control register 1 (Note 1)

Symbol Address After reset CM1 000716 001000002

Bit name

FunctionBit symbol

b7 b6 b5 b4 b3 b2 b1 b0

CM10 All clock stop control bit(Notes 3, 4)

0 : Clock on1 : All clocks off (stop mode)

Note 1: Write to this register after setting the PRC0 bit of PRCR register to “1” (write enable).Note 2: Effective when the CM06 bit is “0” (CM16 and CM17 bits enable).Note 3: When the CM20 bit of CM2 register is set to “1” (oscillation stop, re-oscillation detection function enabled), do not set the

CM10 bit to “1”.Note 4: When the PM21 bit of PM2 register is set to “1” (clock modification disable), writing to the CM10 bits has no effect. When the PM22 bit of PM2 register is set to “1” (watchdog timer count source is On-chip Oscillator clock), writing to the CM10 bit has no effect.

RW

CM16

CM17

Reserved bit Must set to “0”

Main clock division select bit 1 (Note 2)

0 0 : No division mode0 1 : Division by 2 mode1 0 : Division by 4 mode1 1 : Division by 16 mode

b7 b6

0 001 0

RW

RW

RW

RW

RW

(b4-b1)

Reserved bit Must set to “1”(b5)




b7 b6 b5 b4 b3 b2 b1 b0

RW

CM20

CM21

Oscillation stop detection register (Note 1)

Symbol Address After reset CM2 000C16 0X0000002(Note 10)


System clock select bit 2 (Notes 2, 3, 6, 10)

0: Oscillation stop, re-oscillation detection function disabled1: Oscillation stop, re-oscillation detection function enabled

0: Main clock (On-chip Oscillator turned off)1: On-chip Oscillator clock (On-chip Oscillator oscillating)

Oscillation stop, re-oscillation detection bit(Notes 7, 8, 9, 10)

Note 1: Write to this register after setting the PRC0 bit of PRCR register to “1” (write enable).Note 2: When the CM20 bit is “1” (oscillation stop, re-oscillation detection function enabled), the CM27 bit is “1” (oscillation stop, re-oscillation detection interrupt), and the CPU clock source is the main clock, the CM21 bit is set to “1” (On-chip Oscillator clock) if the main clock stop is detected.Note 3: If the CM20 bit is “1” and the CM23 bit is “1” (main clock turned off), do not set the CM21 bit to “0”. Note 4: This bit becomes “1” at main clock stop detection and main clock re-oscillation detection. When this bit

changes from “0” to “1”, there arise oscillation stop, re-oscillation detection interrupt. Use this register to discriminate the causes for oscillation stop, re-oscillation detection interrupt and watchdog timer interrupt in the interrupt processing program. By writing “0” in the program, this bit becomes “0”. (Even when “1” is written in the program, no change is identified for the bit. Also, this bit is not set to “0” where there occur oscillation stop, re-oscillation detection interrupt.) When the CM22 bit is “1”, no oscillation stop, re-oscillation detection interrupt occur even if oscillation stop or re-oscillation is detected.

Note 5: Read the CM23 bit in an oscillation stop, re-oscillation detection interrupt handling routine to determine the main clock status.

Note 6: Effective when the CM07 bit of CM0 register is “0”.Note 7: When the PM21 bit of PM2 register is “1” (clock modification disabled), writing to the CM20 bit has no

effect.Note 8: Set the CM20 bit to “0” (disable) before entering stop mode. After exiting stop mode, set the CM20 bit

back to “1” (enable).Note 9: Set the CM20 bit to “0” (disable) before setting the CM05 bit of CM0 register.Note 10: The CM20, CM21 and CM27 bits do not change at oscillation stop detection reset.

CM22

CM23

Oscillation stop, re-oscillation detection flag

0: Main clock stop, re-oscillation not detected1: Main clock stop, re-oscillation detected

0: Main clock oscillating1: Main clock turned off

XIN monitor flag

(Note 4)

CM27 0: Oscillation stop detection reset 1: Oscillation stop, re-oscillation detection interrupt

Nothing is assigned. When write, set to “0”. When read, its content is indeterminate.

Operation select bit(when an oscillation stop, re-oscillation is detected)(Note 10)

RW

RW

RW

RW

RO

(b6)

(Note 5)

Reserved bit(b5-b4) Must set to “0” RW

0 0




Figure 1.7.5. PCLKR Register and PM2 Register

FunctionBit symbol Bit name

Peripheral clock select register (Note)Symbol Address When reset PCLKR 025E16 000000112

RW

b7 b6 b5 b4 b3 b2 b1 b0

PCLK0 Timers A, B clock select bit (Clock source for the timers A, B, and the dead time timer)

0 : f21 : f1

0 0 0


Note: Write to this register after setting the PRC0 bit of PRCR register to “1” (write enable).

0 0 0

PCLK1 SI/O clock select bit (Clock source for UART0 to UART2, SI/O3, SI/O4)

0 : f2SIO1 : f1SIO

RW

RW

RW(b7-b2)

FunctionBit symbol Bit name


Symbol Address After reset PM2 001E16 XXX000002

RW

b7 b6 b5 b4 b3 b2 b1 b0

0 0


Nothing is assigned. When write, set to “0”. When read, its content is interdeterminate.


Note 1: Write to this register after setting the PRC1 bit of PRCR register to “1” (write enable).Note 2: Once this bit is set to “1”, it cannot be cleared to “0” in a program.Note 3: Setting the PM21 bit to “1” results in the following conditions: • The BCLK is not halted by executing the WAIT instruction. • Writing to the following bits has no effect.

CM02 bit of CM0 register CM05 bit of CM0 register (main clock is not halted)CM07 bit of CM0 registerCM10 bit of CM1 register (stop mode is not entered)CM11 bit of CM1 registerCM20 bit of CM2 register (oscillation stop, re-oscillation detection function settings do not change)

Note 4: Setting the PM22 bit to “1” results in the following conditions: • The On-chip Oscillator starts oscillating, and the On-chip Oscillator clock becomes the watchdog timer count source. • The CM10 bit of CM1 register is disabled against write. (Writing a “1” has no effect, nor is stop mode entered.) • The watchdog timer does not stop when in wait mode or hold state.

RW

RW

PM21

(b7-b5)

System clock protectivebit

0 : Clock is protected by PRCR register1 : Clock modification disabled

PM22 WDT count source protective bit

(Note 2, Note 3)

(Note 2, Note 4)

0 : CPU clock is used for the watchdog timer count source1 : On-chip Oscillator clock is used for the watchdog timer count source

RW

(b4-b3)

(b0)



Microcomputer(Built-in feedback resistor)

XIN XOUT

Externally derived clock

5.12 MHz

Open

Vcc

Vss

Microcomputer(Built-in feedback resistor)

XIN XOUT

Rd

CIN COUT

(Note 1)

(Note 2)

Note 1: Insert a damping resistor if required. The resistance will vary depending on the oscillator and the oscillation drive

Note 2: Operating frequency must be 5.12 MHz, overall accuracy must be less than 150 ppm.

capacity setting. Use the value recommended by the maker of the oscillator.Also, if the oscillator manufacturer's data sheet specifies that a feedback resistor be added external to the chip,

insert a feedback resistor between XIN and XOUT following the instruction.

Figure 1.7.6. Examples of Main Clock Connection Circuit

The following describes the clocks generated by the clock generation circuit.

(1) Main Clock

Main clock is supplied by IT800 with a tripled clock of XIN (main clock oscillator).

This clock is used as the clock source for the CPU and peripheral function clocks. The main clock oscilla-

tor circuit is configured by connecting a resonator between the XIN and XOUT pins. The main clock oscil-

lator circuit contains a feedback resistor. The main clock oscillator circuit may also be configured by

feeding an externally generated clock to the XIN pin. Figure 1.7.6 shows the examples of main clock

connection circuit.

After reset, the main clock divided by 8 is selected for the CPU clock.

Even if XIN input stops, main clock oscillator does not stop.

During stop mode, all clocks of internal M16C core including the main clock are turned off. Refer to

“power control”.



(3) On-chip Oscillator ClockThis clock, approximately 1 MHz, is supplied by a On-chip Oscillator. This clock is used as the clock

source for the CPU and peripheral function clocks. In addition, if the PM22 bit of PM2 register is “1” (On-

chip Oscillator clock for the watchdog timer count source), this clock is used as the count source for the

watchdog timer.

After reset, the On-chip Oscillator clock is turned off. It is turned on by setting the CM21 bit of CM2

register to “1” (On-chip Oscillator clock), and is used as the clock source for the CPU and peripheral

function clocks, in place of the main clock.



CPU Clock and Peripheral Function Clock

Two type clocks: CPU clock to operate the CPU and peripheral function clocks to operate the peripheral

functions.

(1) CPU Clock and BCLKThese are operating clocks for the CPU and watchdog timer.

The clock source for the CPU clock can be chosen to be the main clock, or On-chip Oscillator clock.

If the main clock or On-chip Oscillator clock is selected as the clock source for the CPU clock, the se-

lected clock source can be divided by 1 (undivided), 2, 4, 8 or 16 to produce the CPU clock. Use the CM06

bit in CM0 register and the CM17 to CM16 bits in CM1 register to select the divide-by-n value.

After reset, the main clock divided by 8 provides the CPU clock.

Note that when entering stop mode from high or middle speed mode or On-chip Oscillator mode, the

CM06 bit of CM0 register is set to “1” (divide-by-8 mode).

(2) Peripheral Function Clock(f1, f2, f8, f32, f1SIO, f2SIO, f8SIO, f32SIO)These are operating clocks for the peripheral functions.

Of these, fi (i = 1, 2, 8, 32) and fiSIO are derived from the main clock, or On-chip Oscillator clock by dividing

them by i. The clock fi is used for timers A, and fiSIO is used for serial I/O.

When the WAIT instruction is executed after setting the CM02 bit of CM0 register to “1” (peripheral

function clock turned off during wait mode), or when the microcomputer is in low power dissipation mode,

the fi, and fiSIO clocks are turned off.



Power ControlThere are three power control modes. For convenience’ sake, all modes other than wait and stop modes

are referred to as normal operation mode here.

(1) Normal Operation Mode

Normal operation mode is further classified into three modes.

In normal operation mode, because the CPU clock and the peripheral function clocks both are on, the

CPU and the peripheral functions are operating. Power control is exercised by controlling the CPU clock

frequency. The higher the CPU clock frequency, the greater the processing capability. The lower the CPU

clock frequency, the smaller the power consumption in the chip. If the unnecessary oscillator circuits are

turned off, the power consumption is further reduced.

Before the clock sources for the CPU clock can be switched over, the new clock source to which switched

must be oscillating stably. If the new clock source is the main clock, allow a sufficient wait time in a

program until it becomes oscillating stably.

Where the CPU clock source is changed from the On-chip Oscillator to the main clock, change the opera-

tion mode to the medium speed mode (divided by 8 mode) after the clock was divided by 8 (the CM06 bit

of CM0 register was set to “1”) in the On-chip Oscillator mode.

• High-speed Mode

The main clock divided by 1 provides the CPU clock.

• Medium-speed Mode

The main clock divided by 2, 4, 8 or 16 provides the CPU clock.

• On-chip Oscillator Mode

The On-chip Oscillator clock divided by 1 (undivided), 2, 4, 8 or 16 provides the CPU clock. The On-

chip Oscillator clock is also the clock source for the peripheral function clocks.



Table 1.7.2. Setting Clock Related Bit and Modes

Modes CM2 register

CM21CM1 registerCM17, CM16

CM0 registerCM06

High-speed mode 0 002 0Medium-speed mode

0 012 00 102 0

divided by 2

0 10 112 0

On-chip oscillator mode

divided by 4divided by 8divided by 16

1 012 01 102 01 11 112 0

1 002 0divided by 2divided by 4divided by 8divided by 16

divided by 1

(2) Wait ModeIn wait mode, the CPU clock is turned off, so are the CPU (because operated by the CPU clock) and the

watchdog timer. However, if the PM22 bit of PM2 register is “1” (On-chip Oscillator clock for the watchdog

timer count source), the watchdog timer remains active. Because the main clock, and On-chip Oscillator

clock are on, the peripheral functions using these clocks keep operating.

• Peripheral Function Clock Stop Function

If the CM02 bit is “1” (peripheral function clocks turned off during wait mode), the f1, f2, f8, f32, f1SIO,

f8SIO, and f32SIO clocks are turned off when in wait mode, with the power consumption reduced that

much.

• Entering Wait Mode

The microcomputer is placed into wait mode by executing the WAIT instruction.

• Pin Status During Wait Mode

Table 1.7.3 lists pin status during wait mode

• Exiting Wait Mode

The microcomputer is moved out of wait mode by a hardware reset or peripheral function interrupt.

If the microcomputer is to be moved out of exit wait mode by a hardware reset, set the peripheral

function interrupt priority ILVL2 to ILVL0 bits to “0002” (interrupts disabled) before executing the WAIT

instruction.

The peripheral function interrupts are affected by the CM02 bit. If CM02 bit is “0” (peripheral function

clocks not turned off during wait mode), all peripheral function interrupts can be used to exit wait

mode. If CM02 bit is “1” (peripheral function clocks turned off during wait mode), the peripheral func-

tions using the peripheral function clocks stop operating, so that only the peripheral functions clocked

by external signals can be used to exit wait mode.

Table 1.7.4 lists the interrupts to exit wait mode.



Table 1.7.3. Pin Status During Wait Mode

Pin Status

I/O ports Retains status before wait mode

Interrupt CM02=0 CM02=1

Serial I/O interrupt Can be used when operating with internal or external clock

Can be used when operating with external clock

Timer A interrupt Can be used in all modes Can be used in event counter mode

INT interrupt Can be used Can be used

Table 1.7.4. Interrupts to Exit Wait Mode

If the microcomputer is to be moved out of wait mode by a peripheral function interrupt, set up the

following before executing the WAIT instruction.

1. In the ILVL2 to ILVL0 bits of interrupt control register, set the interrupt priority level of the periph

eral function interrupt to be used to exit wait mode.

Also, for all of the peripheral function interrupts not used to exit wait mode, set the ILVL2 to ILVL0

bits to “0002” (interrupt disable).

2. Set the I flag to “1”.

3. Enable the peripheral function whose interrupt is to be used to exit wait mode.

In this case, when an interrupt request is generated and the CPU clock is thereby turned on, an

interrupt routine is executed.

The CPU clock turned on when exiting wait mode by a peripheral function interrupt is the same CPU

clock that was on when the WAIT instruction was executed.



(3) Stop Mode

In stop mode, all the M16C core's internal oscillator circuits are turned off, so are the CPU clock and theperipheral function clocks. Therefore, the CPU and the peripheral functions clocked by these clocks stopoperating.However, the peripheral functions clocked by external signals keep operating. The following interruptscan be used to exit stop mode.

______

• INT interrupt• Timer A, interrupt (when counting external pulses in event counter mode)• Serial I/O interrupt (when external clock is selected)

• Entering Stop ModeThe microcomputer is placed into stop mode by setting the CM10 bit of CM1 register to “1” (all clocksturned off). At the same time, the CM06 bit of CM0 register is set to “1” (divide-by-8 mode).Before entering stop mode, set the CM20 bit to “0” (oscillation stop, re-oscillation detection functiondisable).

• Pin Status in Stop ModeTable 1.7.5 lists pin status during stop mode

• Exiting Stop ModeThe microcomputer is moved out of stop mode by a hardware reset or peripheral function interrupt.If the microcomputer is to be moved out of stop mode by a hardware reset, set the peripheral functioninterrupt priority ILVL2 to ILVL0 bits to “0002” (interrupts disable) before setting the CM10 bit to “1”.If the microcomputer is to be moved out of stop mode by a peripheral function interrupt, set up thefollowing before setting the CM10 bit to “1”.

1. In the ILVL2 to ILVL0 bits of interrupt control register, set the interrupt priority level of the periph-eral function interrupt to be used to exit stop mode.Also, for all of the peripheral function interrupts not used to exit stop mode, set the ILVL2 to ILVL0bits to “0002”.

2. Set the I flag to “1”.3. Enable the peripheral function whose interrupt is to be used to exit stop mode.

In this case, when an interrupt request is generated and the CPU clock is thereby turned on, aninterrupt service routine is executed.

Which CPU clock will be used after exiting stop mode by a peripheral function is determined by theCPU clock that was on when the microcomputer was placed into stop mode as follows:If the CPU clock before entering stop mode was derived from the main clock: main clock divide-by-8If the CPU clock before entering stop mode was derived from the On-chip Oscillator clock: On-chipOscillator clock divide-by-8



Table 1.7.5. Pin Status in Stop Mode

Pin Status

I/O ports Retains status before stop mode



Figure 1.7.7. State Transition to Stop Mode and Wait Mode

Reset

Medium-speed mode(divided-by-8 mode)

High-speed, medium-speed mode

Stop mode Wait mode Interrupt

CM10=1

Interrupt

Normal mode

CM10=1

Stop mode

All oscillators stopped

InterruptWait mode

WAIT instruction(Note 1)

Interrupt

CPU operation stopped

Note 1: When the PM21 bit = 0 (system clock protective function unused).Note 2: The On-chip Oscillator clock divided by 8 provides the CPU clock.Note 3: Write to the CM0 register and CM1 register simultaneously by accessing in word units while CM21=0 (On-chip Oscillator turned off).

On-chip Oscillator mode Wait mode Interrupt

CM10=1

Interrupt(Note 2)

Stop mode



Figure 1.7.7 shows the state transition from normal operation mode to stop mode and wait mode.



Figure 1.7.8. State Transition in Normal Mode

CM07=0

CM17=0

CM06=0

CM16=0

CM07=0

CM17=0

CM06=0

CM16=1

CM07=0

CM17=1

CM06=0

CM16=0

CM07=0

CM06=1

CM07=0

CM17=1

CM06=0

CM16=1

High-speed modeOn-chip Oscillator mode

On-chip Oscillator clock oscillation

CPU clockCM21=0(Note 4)

(Note 2)

(Note 3)

CM21=1

Main clock oscillation

f(Ring)f(Ring)/2f(Ring)/4f(Ring)/8f(Ring)/16

Middle-speed mode (divide by 2)




CPU clock: f(XIN) CPU clock: f(XIN)/2 CPU clock: f(XIN)/4 CPU clock: f(XIN)/8 CPU clock: f(XIN)/16

Notes: 1: Avoid making a transition when the CM20 bit in the CM2 register is set to “1” (oscillation stop, re-oscillation detection function enabled). Set the CM20 bit to “0” (oscillation stop, re-oscillation detection function disabled) before transiting. 2: Change CM17 and CM16 bits in the CM1 register before changing CM06 bit in the CM0 register. 3: Transit in accordance with arrow. 4: Set the CM06 to “1” (division by 8 mode) before changing back the operation mode from on-chip oscillator mode to high- or middle-speed mode.



Table 1.7.6. Allowed Transition and Setting

High-speed mode, middle-speed mode

On-chip Oscillator mode

Stop mode

Wait modeCur

rent

sta

te

State after transition

See Table A

(10)3

(1)

(2)

(3)

(4)

(5)

(6)

(7)

(8)

(9)

(10)

Setting Operation

CM06 = 0,CPU clock no division modeCM17 = 0 , CM16 = 0

CM06 = 0, CPU clock division by 2 modeCM17 = 0 , CM16 = 1


CM06 = 1 CPU clock division by 8 mode


CM21 = 0 Main clock

CM21 = 1 On-chip Oscillator clock selected

CM10 = 1 Transition to stop mode

wait Transition to wait mode

Hardware interrupt Exit stop mode or wait mode

(6)2

(7)

--

--

(8)1 (9)

(8)1 (9)

(1)

(1)

(1)

(1)

(2)

(2)

(2)

(2)

(3)

(3)

(3)

(3) (5)

(5)

(5)

(5)

(4)

(4)

(4)

(4)

State after transition

(10)3

(10)(10)

Table 1. State Transition with Main Clock Division Ration in High- or Middle-speed Mode and On-chip Oscillator Mode. Table B. Setting and Operation

Notes:1. Avoid making a transition when the CM21 bit is set to “1” (oscillation stop, re-oscillation detection function enabled). Set the CM21 bit to “0” (oscillation stop, re-oscillation detection function disabled) before transiting.2. Set the CM06 bit to “1” (division by 8 mode) before transiting from On-chip Oscillator mode to high- or middle-speed mode.3. When exiting stop mode, the CM06 bit is set to “1” (division by 8 mode).

--: Cannot transit

High-speed mode, middle-speed mode

On-chip Oscillatormode Stop mode Wait mode

See Table A

No division

Divided by 2

Dividedby 4

Divided by 8

Divided by 16

Cur

rent

st

ate

No division

Divided by 4

Divided by 8

Divided by 16

Divided by 2



System Clock Protective FunctionWhen the main clock is selected for the CPU clock source, this function disables the clock against modifica-

tions in order to prevent the CPU clock from becoming halted by run-away.

If the PM21 bit of PM2 register is set to “1” (clock modification disabled), the following bits are protected

against writes:

• CM02 bit in CM0 register

• CM10, CM11 bits in CM1 register

• CM20 bit in CM2 register

Before the system clock protective function can be used, the following register settings must be made:

(1) Set the PRC1 bit of PRCR register to “1” (enable writes to PM2 register).

(2) Set the PM21 bit of PM2 register to “1” (disable clock modification).

(3) Set the PRC1 bit of PRCR register to “0” (disable writes to PM2 register).

Do not execute the WAIT instruction when the PM21 bit is “1”.



Oscillation Stop and Re-oscillation Detect FunctionThe oscillation stop and re-oscillation detect function is such that main clock oscillation circuit stop and re-

oscillation are detected. At oscillation stop, re-oscillation detection, reset or oscillation stop, re-oscillation

detection interrupt are generated. Which is to be generated can be selected using the CM27 bit of CM2

register. Main clock oscillator of M16C/6S does not stop even if Xin input stops. Oscillation stop re-oscilla-

tion detect circuit does not function.

M16C/6S Group Protection


ProtectionIn the event that a program runs out of control, this function protects the important registers so that they will

not be rewritten easily. Figure 1.8.1 shows the PRCR register. The following lists the registers protected by

the PRCR register.

• Registers protected by PRC0 bit: CM0, CM1, CM2, and PCLKR registers

• Registers protected by PRC1 bit: PM0, PM1, PM2 registers

• Registers protected by PRC2 bit: PD9, S3C and S4C registers

Set the PRC2 bit to “1” (write enabled) and then write to any address, and the PRC2 bit will be cleared to “0”

(write protected). The registers protected by the PRC2 bit should be changed in the next instruction after

setting the PRC2 bit to “1”. Make sure no interrupts or DMA transfers will occur between the instruction in

which the PRC2 bit is set to “1” and the next instruction. The PRC0 and PRC1 bits are not automatically

cleared to “0” by writing to any address. They can only be cleared in a program.

Figure 1.8.1. PRCR Register

Protect register

Symbol Address After reset PRCR 000A16 XX0000002

Bit nameBit symbol

b7 b6 b5 b4 b3 b2 b1 b0

0 : Write protected1 : Write enabled

PRC1

PRC0

PRC2

Function RW

Note: The PRC2 bit is set to “0” by writing to any address after setting it to “1”. Other bits are not set to “0” by writing to any address, and must therefore be set in a program.

0 0

RW

RW

RW


Reserved bit Must set to “0” RW

Protect bit 0

Protect bit 1

Protect bit 2

Enable write to CM0, CM1, CM2, PLC0 and PCLKR registers


Enable write to PM0, PM1, PM2, TB2SC, INVC0 and INVC1 registers


Enable write to PD9, S3C and S4C registers

(b5-b3)

(b7-b6)

0

M16C/6S Group Interrupts


• Maskable Interrupt: An interrupt which can be enabled (disabled) by the interrupt enable flag (I flag) or

whose interrupt priority can be changed by priority level.

• Non-maskable Interrupt: An interrupt which cannot be enabled (disabled) by the interrupt enable flag

(I flag) or whose interrupt priority cannot be changed by priority level.

Figure 1.9.1. Interrupts

Interrupt

Software

(Non-maskable interrupt)

Hardware

Special

(Non-maskable interrupt)

Peripheral function (Note 1)

(Maskable interrupt)

Undefined instruction (UND instruction)

Overflow (INTO instruction)

BRK instruction

INT instruction

________

DBC (Note 2)

Watchdog timer

Single step (Note 2)

Address match

Note 1: Peripheral function interrupts are generated by the microcomputer's internal functions.

Note 2: Do not normally use this interrupt because it is provided exclusively for use by development

support tools.

Interrupts

Type of InterruptsFigure 1.9.1 shows types of interrupts.



Software InterruptsA software interrupt occurs when executing certain instructions. Software interrupts are non-maskable

interrupts.

• Undefined Instruction Interrupt

An undefined instruction interrupt occurs when executing the UND instruction.

• Overflow Interrupt

An overflow interrupt occurs when executing the INTO instruction with the O flag set to “1” (the opera-

tion resulted in an overflow). The following are instructions whose O flag changes by arithmetic:

ABS, ADC, ADCF, ADD, CMP, DIV, DIVU, DIVX, NEG, RMPA, SBB, SHA, SUB

• BRK Interrupt

A BRK interrupt occurs when executing the BRK instruction.

• INT Instruction Interrupt

An INT instruction interrupt occurs when executing the INT instruction. Software interrupt Nos. 0 to 63

can be specified for the INT instruction. Because software interrupt Nos. 4 to 31 are assigned to

peripheral function interrupts, the same interrupt routine as for peripheral function interrupts can be

executed by executing the INT instruction.

In software interrupt Nos. 0 to 31, the U flag is saved to the stack during instruction execution and is

cleared to “0” (ISP selected) before executing an interrupt sequence. The U flag is restored from the

stack when returning from the interrupt routine. In software interrupt Nos. 32 to 63, the U flag does not

change state during instruction execution, and the SP then selected is used.



Hardware InterruptsHardware interrupts are classified into two types — special interrupts and peripheral function interrupts.

(1) Special Interrupts

Special interrupts are non-maskable interrupts.________

• DBC Interrupt

Do not normally use this interrupt because it is provided exclusively for use by development support

tools.

• Watchdog Timer Interrupt

Generated by the watchdog timer. Once a watchdog timer interrupt is generated, be sure to initialize

the watchdog timer. For details about the watchdog timer, refer to the section "watchdog timer".

• Oscillation Stop and Re-oscillation Detection Interrupt

Generated by the oscillation stop and re-oscillation detection function. For details about the oscilla-

tion stop detection function, refer to the section "clock generating circuit".

• Single-step Interrupt

Do not normally use this interrupt because it is provided exclusively for use by development support

tools.

• Address Match Interrupt

An address match interrupt is generated immediately before executing the instruction at the address

indicated by the RMAD0 to RMAD3 register that corresponds to one of the AIER register’s AIER0 or

AIER1 bit or the AIER2 register’s AIER20 or AIER21 bit which is "1" (address match interrupt en-

abled). For details about the address match interrupt, refer to the section "address match interrupt".

(2) Peripheral Function Interrupts

Peripheral function interrupts are maskable interrupts and generated by the microcomputer's internal

functions. The interrupt sources for peripheral function interrupts are listed in Table 1.9.1. For details

about the peripheral functions, refer to the description of each peripheral function in this manual.



Interrupt source Vector table addresses Remarks Reference

Address (L) to address (H)

Undefined instruction FFFDC16 to FFFDF16 Interrupt on UND instruction M16C/60, M16C/20

Overflow FFFE016 to FFFE316 Interrupt on INTO instruction series software

BRK instruction FFFE416 to FFFE716 manual

Address match FFFE816 to FFFEB16 Address match interrupt

Single step (Note) FFFEC16 to FFFEF16

Watchdog timer FFFF016 to FFFF316 Watchdog timerOscillation stop and

re-oscillation detection Clock generating circuit________

DBC (Note) FFFF416 to FFFF716

FFFF816 to FFFFB16

Reset FFFFC16 to FFFFF16 Reset

Note: Do not normally use this interrupt because it is provided exclusively for use by development sup-

port tools.

Figure 1.9.2. Interrupt Vector

Mid address

Low address

0 0 0 0 High address

0 0 0 0 0 0 0 0

Vector address (L)

LSBMSB

Vector address (H)

Interrupts and Interrupt VectorOne interrupt vector consists of 4 bytes. Set the start address of each interrupt routine in the respective

interrupt vectors. When an interrupt request is accepted, the CPU branches to the address set in the

corresponding interrupt vector. Figure 1.9.2 shows the interrupt vector.

• Fixed Vector Tables

The fixed vector tables are allocated to the addresses from FFFDC16 to FFFFF16. Table 1.9.1 lists the

fixed vector tables. In the flash memory version of microcomputer, the vector addresses (H) of fixed

vectors are used by the ID code check function. For details, refer to the section "flash memory rewrite

disabling function".

Table 1.9.1. Fixed Vector Tables

If the contents of addressFFFE716 is FF16, program ex-ecution starts from the addressshown by the vector in therelocatable vector table.

(Reserved)



Table 1.9.2. Relocatable Vector Tables

Software interrupt number

Reference

Note 1: Address relative to address in INTB.Note 2: Set the IFSR register's IFSR6 and IFSR7 bits “0”.Note 3: During I2C mode, NACK and ACK interrupts comprise the interrupt source. Note 4: Set the IFSR2A register’s IFSR26 and IFSR27 bits “1”.Note 5: These interrupts cannot be disabled using the I flag.

Vector address (Note 1)Address (L) to address (H)

0

11

12

13

14

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

63

to

10

15

16

5

6

7

8

4

9

1 to 3

Interrupt source

BRK instruction

INT3

SI/O3, INT4

SI/O4, INT5

Timer B4, UART1 bus collision detect

(Note 2)

(Note 2)

DMA0

DMA1

UART0 transmit, NACK0

UART0 receive, ACK0

UART1 transmit, NACK1

UART1 receive, ACK1

Timer A0

Timer A1

Timer A2

Timer A3

Timer A4

INT0

INT1

INT2

Software interrupt

UART 2 bus collision detection

UART2 transmit, NACK2 (Note 3)

UART2 receive, ACK2 (Note 3)

(Note 4)

Timer B3, UART0 bus collision detect(Note 4)

M16C/60, M16C/20 series software manual

INT interrupt

TimerSerial I/O

Serial I/OINT interrupt

Serial I/O

DMAC

Serial I/O

Timer

INT interrupt

M16C/60, M16C/20 series software manual

(Note 5)

(Reserved)

(Reserved)

(Reserved)

(Reserved)

(Reserved)

(Reserved)

(Reserved)

+0 to +3 (000016 to 000316)

+44 to +47 (002C16 to 002F16)

+48 to +51 (003016 to 003316)

+52 to +55 (003416 to 003716)

+56 to +59 (003816 to 003B16)

+68 to +71 (004416 to 004716)

+72 to +75 (004816 to 004B16)

+76 to +79 (004C16 to 004F16)

+80 to +83 (005016 to 005316)

+84 to +87 (005416 to 005716)

+88 to +91 (005816 to 005B16)

+92 to +95 (005C16 to 005F16)

+96 to +99 (006016 to 006316)

+100 to +103 (006416 to 006716)

+104 to +107 (006816 to 006B16)

+108 to +111 (006C 16 to 006F16)

+112 to +115 (0070 16 to 007316)

+116 to +119 (0074 16 to 007716)

+120 to +123 (007816 to 007B16)

+124 to +127 (007C16 to 007F16)

+128 to +131 (008016 to 008316)

+252 to +255 (00FC16 to 00FF16)

+40 to +43 (002816 to 002B16)

+60 to +63 (003C16 to 003F16)

+64 to +67 (004016 to 004316)

+20 to +23 (001416 to 001716)

+24 to +27 (001816 to 001B16)

+28 to +31 (001C16 to 001F16)

+32 to +35 (002016 to 002316)

+16 to +19 (001016 to 001316)

+36 to +39 (002416 to 002716)

to

(Note 3)

(Note 3)

(Note 3)

(Note 3)

(Note 5)

• Relocatable Vector Tables

The 256 bytes beginning with the start address set in the INTB register comprise a reloacatable vector

table area. Table 1.9.2 lists the relocatable vector tables. Setting an even address in the INTB register

results in the interrupt sequence being executed faster than in the case of odd addresses.



Interrupt ControlThe following describes how to enable/disable the maskable interrupts, and how to set the priority in which

order they are accepted. What is explained here does not apply to nonmaskable interrupts.

Use the FLG register’s I flag, IPL, and each interrupt control register’s ILVL2 to ILVL0 bits to enable/disable

the maskable interrupts. Whether an interrupt is requested is indicated by the IR bit in each interrupt control

register.

Figure 1.9.3 shows the interrupt control registers.



Figure 1.9.3. Interrupt Control Registers

Symbol Address After resetINT3IC 004416 XX00X0002S4IC 004816 XX00X0002S3IC 004916 XX00X0002INT0IC to INT2IC 005D16 to 005F16 XX00X0002


b7 b6 b5 b4 b3 b2 b1 b0

ILVL0

IR

POL

No functions are assigned.When writing to these bits, write “0”. The values in these bits when read are indeterminate.

Interrupt priority level select bit

Interrupt request bit

Polarity select bit

Reserved bit

0: Interrupt not requested1: Interrupt requested

0 : Selects falling edge (Notes 3, 4)1 : Selects rising edge

Must always be set to “0”

ILVL1

ILVL2

Note 1: This bit can only be reset by writing "0" (Do not write "1"). Note 2: To rewrite the interrupt control register, do so at a point that does not generate the interrupt request for that register. For details, see the precautions for interrupts.Note 3: If the IFSR register’s IFSRi bit (i = 0 to 5) is "1" (both edges), set the INTiIC register’s POL bit to "0 "(falling edge). Note 4: Set the S3IC or S4IC register’s POL bit to "0" (falling edge) when the IFSR register’s IFSR6 bit = 0 (SI/O3 selected) or IFSR7 bit = 0 (SI/O4 selected), respectively.

(Note 1)

Interrupt control register (Note 2)

b7 b6 b5 b4 b3 b2 b1 b0


Symbol Address After reset

BCNIC 004A16 XXXXX0002U0BCNIC (Note 3) 004716 XXXXX0002U1BCNIC (Note 3) 004616 XXXXX0002

DM0IC, DM1IC 004B16, 004C16 XXXXX0002S0TIC to S2TIC 005116, 005316, 004F16 XXXXX0002S0RIC to S2RIC 005216, 005416, 005016 XXXXX0002TA0IC to TA4IC 005516 to 005916 XXXXX0002

ILVL0

IR

Interrupt priority level select bit

Interrupt request bit 0 : Interrupt not requested1 : Interrupt requested

ILVL1

ILVL2

No functions are assigned.When writing to these bits, write “0”. The values in these bits when read are indeterminate.

(Note 1)

Note 1: This bit can only be reset by writing "0" (Do not write "1"). Note 2: To rewrite the interrupt control registers, do so at a point that does not generate the interrupt request for that register. For details, see the precautions for interrupts. Note 3: Use the IFSR2A register to select.

0 0 0 : Level 0 (interrupt disabled)0 0 1 : Level 1 0 1 0 : Level 2 0 1 1 : Level 3 1 0 0 : Level 4 1 0 1 : Level 5 1 1 0 : Level 6 1 1 1 : Level 7

b2 b1 b0

0 0 0 : Level 0 (interrupt disabled)0 0 1 : Level 1 0 1 0 : Level 2 0 1 1 : Level 3 1 0 0 : Level 4 1 0 1 : Level 5 1 1 0 : Level 6 1 1 1 : Level 7

b2 b1 b0

0

RW

RW

RW

RW

(b7-b4)

RW

RW

RW

RW

RW

RW

RW

RW(b7-b6)



I FlagThe I flag enables or disables the maskable interrupt. Setting the I flag to “1” (= enabled) enables the

maskable interrupt. Setting the I flag to “0” (= disabled) disables all maskable interrupts.

IR Bit

The IR bit is set to “1” (= interrupt requested) when an interrupt request is generated. Then, when the

interrupt request is accepted and the CPU branches to the corresponding interrupt vector, the IR bit is

cleared to “0” (= interrupt not requested).

The IR bit can be cleared to “0” in a program. Note that do not write “1” to this bit.

Table 1.9.4. Interrupt Priority Levels Enabled by IPL

Table 1.9.3. Settings of Interrupt Priority Levels

ILVL2 to ILVL0 bitsInterrupt priority

levelPriorityorder

0002

0012

0102

0112

1002

1012

1102

1112

Level 0 (interrupt disabled)

Level 1

Level 2

Level 3

Level 4

Level 5

Level 6

Level 7

Low

High

Enabled interrupt priority levels

Interrupt levels 1 and above are enabled







All maskable interrupts are disabled

IPL

0002

0012

0102

0112

1002

1012

1102

1112

ILVL2 to ILVL0 Bits and IPLInterrupt priority levels can be set using the ILVL2 to ILVL0 bits.

Table 1.9.3 shows the settings of interrupt priority levels and Table 1.9.4 shows the interrupt priority levels

enabled by the IPL.

The following are conditions under which an interrupt is accepted:

· I flag = “1”

· IR bit = “1”

· interrupt priority level > IPL

The I flag, IR bit, ILVL2 to ILVL0 bits and IPL are independent of each other. In no case do they affect one

another.



Interrupt SequenceAn interrupt sequence — what are performed over a period from the instant an interrupt is accepted to the

instant the interrupt routine is executed — is described here.

If an interrupt occurs during execution of an instruction, the processor determines its priority when the

execution of the instruction is completed, and transfers control to the interrupt sequence from the next

cycle. If an interrupt occurs during execution of either the SMOVB, SMOVF, SSTR or RMPA instruction,

the processor temporarily suspends the instruction being executed, and transfers control to the interrupt

sequence.

The CPU behavior during the interrupt sequence is described below. Figure 1.9.4 shows time required for

executing the interrupt sequence.

(1) The CPU gets interrupt information (interrupt number and interrupt request priority level) by reading the

address 0000016. Then it clears the IR bit for the corresponding interrupt to “0” (interrupt not re-

quested).

(2) The FLG register immediately before entering the interrupt sequence is saved to the CPU’s internal

temporary register(Note 1).

(3) The I, D and U flags in the FLG register become as follows:

The I flag is cleared to “0” (interrupts disabled).

The D flag is cleared to “0” (single-step interrupt disabled).

The U flag is cleared to “0” (ISP selected).

However, the U flag does not change state if an INT instruction for software interrupt Nos. 32 to 63 is

executed.

(4) The CPU’s internal temporary register (Note 1) is saved to the stack.

(5) The PC is saved to the stack.

(6) The interrupt priority level of the accepted interrupt is set in the IPL.

(7) The start address of the relevant interrupt routine set in the interrupt vector is stored in the PC.

After the interrupt sequence is completed, the processor resumes executing instructions from the start

address of the interrupt routine.

Note: This register cannot be used by user.

Indeterminate

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18

Indeterminate SP-2 contents

SP-4 contents

vec contents

vec+2 contents

Interrupt information

Address 000016 Indeterminate SP-2 SP-4 vec vec+2 PC

CPU clock

Address bus

Data bus

WR

RD

The indeterminate state depends on the instruction queue buffer. A read cycle occurs when the instruction queue buffer is ready to accept instructions.

Figure 1.9.4. Time Required for Executing Interrupt Sequence



Interrupt sources

7

Level that is set to IPL

Watchdog timer_________

Software, address match, DBC, single-step Not changed

Variation of IPL when Interrupt Request is AcceptedWhen a maskable interrupt request is accepted, the interrupt priority level of the accepted interrupt is set

in the IPL.

When a software interrupt or special interrupt request is accepted, one of the interrupt priority levels listed

in Table 1.9.5 is set in the IPL. Shown in Table 1.9.5 are the IPL values of software and special interrupts

when they are accepted.

Table 1.9.5. IPL Level That is Set to IPL When A Software or Special Interrupt Is Accepted

Instruction Interrupt sequence Instruction in interrupt routine

Time

Interrupt response time

(a) (b)

Interrupt request acknowledgedInterrupt request generated

(a) A time from when an interrupt request is generated till when the instruction then executing is completed. The length of this time varies with the instruction being executed. The DIVX instruction requires the longest time, which is equal to 30 cycles (without wait state, the divisor being a register).

(b) A time during which the interrupt sequence is executed. For details, see the table

below. Note, however, that the values in this table must be increased 2 cycles for the DBC interrupt and 1 cycle for the address match and single-step interrupts.

Interrupt vector address

Even

Even

Odd

Odd

SP value

Even

Odd

Even

Odd

16-Bit bus, without wait

18 cycles

19 cycles

19 cycles

20 cycles

8-Bit bus, without wait

20 cycles

20 cycles

20 cycles

20 cycles

Figure 1.9.5. Interrupt response time

Interrupt Response TimeFigure 1.9.5 shows the interrupt response time. The interrupt response or interrupt acknowledge time

denotes a time from when an interrupt request is generated till when the first instruction in the interrupt

routine is executed. Specifically, it consists of a time from when an interrupt request is generated till when

the instruction then executing is completed ((a) in Figure 1.9.5) and a time during which the interrupt

sequence is executed ((b) in Figure 1.9.5).



Saving RegistersIn the interrupt sequence, the FLG register and PC are saved to the stack.

At this time, the 4 high-order bits of the PC and the 4 high-order (IPL) and 8 low-order bits of the FLG

register, 16 bits in total, are saved to the stack first. Next, the 16 low-order bits of the PC are saved. Figure

1.9.6 shows the stack status before and after an interrupt request is accepted.

The other necessary registers must be saved in a program at the beginning of the interrupt routine. Use

the PUSHM instruction, and all registers except SP can be saved with a single instruction.

Address

Content of previous stack

Stack

[SP]SPvalue beforeinterrupt occurs

m

m – 1

m – 2

m – 3

m – 4

Stack status before interrupt requestis acknowledged

Stack status after interrupt requestis acknowledged

Content of previous stackm + 1

MSB L SB

m

m – 1

m – 2

m – 3

m – 4

Address

FLGL

Content of previous stack

Stack

FLGH PCH

[SP]New SP value

Content of previous stackm + 1

MSB L SB

PCL

PCM

PCH : 4 high-order bits of PCPCM : 8 middle-order bits of PCPCL : 8 low-order bits of PC

FLGH : 4 high-order bits of FLGFLGL : 8 low-order bits of FLG

Figure 1.9.6. Stack Status Before and After Acceptance of Interrupt Request



Figure 1.9.7. Operation of Saving Register

(2) SP contains odd number

[SP] (Odd)

[SP] – 1 (Even)

[SP] – 2(Odd)

[SP] – 3 (Even)

[SP] – 4(Odd)

[SP] – 5 (Even)

Address Sequence in which order registers are saved

(2)

(1)

Finished saving registers in four operations.

(3)

(4)

(1) SP contains even number

[SP] (Even)

[SP] – 1(Odd)

[SP] – 2 (Even)

[SP] – 3(Odd)

[SP] – 4 (Even)

[SP] – 5 (Odd)

Note: [SP] denotes the initial value of the SP when interrupt request is acknowledged.After registers are saved, the SP content is [SP] minus 4.

Address

PCM

Stack

FLGL

PCL

Sequence in which order registers are saved

(2) Saved simultaneously, all 16 bits

(1) Saved simultaneously, all 16 bits

Finished saving registers in two operations.

PCM

Stack

FLGL

PCL

Saved, 8 bits at a time

FLGH PCH

FLGH PCH

PCH : 4 high-order bits of PCPCM : 8 middle-order bits of PCPCL : 8 low-order bits of PC

FLGH : 4 high-order bits of FLGFLGL : 8 low-order bits of FLG

The operation of saving registers carried out in the interrupt sequence is dependent on whether the

SP(Note), at the time of acceptance of an interrupt request, is even or odd. If the stack pointer (Note) is

even, the FLG register and the PC are saved, 16 bits at a time. If odd, they are saved in two steps, 8 bits

at a time. Figure 1.9.7 shows the operation of the saving registers.

Note: When any INT instruction in software numbers 32 to 63 has been executed, this is the SP indicated

by the U flag. Otherwise, it is the ISP.



Interrupt PriorityIf two or more interrupt requests are generated while executing one instruction, the interrupt request that

has the highest priority is accepted.

For maskable interrupts (peripheral functions), any desired priority level can be selected using the ILVL2 to

ILVL0 bits. However, if two or more maskable interrupts have the same priority level, their interrupt priority

is resolved by hardware, with the highest priority interrupt accepted.

The watchdog timer and other special interrupts have their priority levels set in hardware. Figure 1.9.8

shows the priorities of hardware interrupts.

Software interrupts are not affected by the interrupt priority. If an instruction is executed, control branches

invariably to the interrupt routine.

Returning from an Interrupt RoutineThe FLG register and PC in the state in which they were immediately before entering the interrupt se-

quence are restored from the stack by executing the REIT instruction at the end of the interrupt routine.

Thereafter the CPU returns to the program which was being executed before accepting the interrupt re-

quest.

Return the other registers saved by a program within the interrupt routine using the POPM or similar in-

struction before executing the REIT instruction.

Interrupt Priority Resolution CircuitThe interrupt priority resolution circuit is used to select the interrupt with the highest priority among those

requested.

Figure 1.9.9 shows the circuit that judges the interrupt priority level.

Figure 1.9.8. Hardware Interrupt Priority

________

Reset > DBC > WDT > Peripheral function > Single step > Address match



Figure 1.9.9. Interrupts Priority Select Circuit

Timer A3

Timer A1

Timer A4

Timer A2

UART1 reception, ACK1



DMA1

UART 2 bus collision

Timer A0

UART1 transmission, NACK1



DMA0

IPL

I flag

INT1

INT2

INT0

Watchdog timer

DBC

Interrupt request

accepted

Level 0 (initial value)Priority level of each interrupt

High

Low

Priority of peripheral function interrupts(if priority levels are same)

UART1 bus collision

INT3

UART0 bus collision

SI/O4

SI/O3

Address match

Interrupt request level resolution outputTo clock generation circuit (Figure 1.7.1)

Oscillation stop and re-oscillation detection

Power supply down detection



______

INT Interrupt_______

INTi interrupt (i=0 to 3) is triggered by the edges of external inputs. The edge polarity is selected using the

IFSR register's IFSRi bit.

Figure 1.9.10 shows the IFSR and IFSR2A registers.

Figure 1.9.10. IFSR Register and IFSR2A Register

Interrupt request cause select register 2


Symbol Address After reset IFSR2A 035E16 00XXXXXX2

b7 b6 b5 b4 b3 b2 b1 b0

0 : reserved1 : UART0 bus collision detection

0 : reserved1 : UART1 bus collision detection

IFSR26

IFSR27

Interrupt request cause select bit


RW

RW

(b5-b0)Nothing is assigned. When write, set to “0”. When read, their contents are indeterminate.

Interrupt request cause select register


Symbol Address After reset IFSR 035F16 0016

IFSR0

b7 b6 b5 b4 b3 b2 b1 b0

INT0 interrupt polarity switching bit

0 : SI/O31 : reserved

0 : SI/O41 : reserved

0 : One edge1 : Both edges









IFSR1

IFSR2

IFSR3

IFSR6

IFSR7

RW

RW

RW

RW

RW

RW

(Note 1)

(Note 1)

(Note 1)

(Note 1)

(Note 3)(Note 2)

(Note 2)

Note 1: When setting this bit to “1” (= both edges), make sure the INT0IC to INT3IC register’s POL bit is set to “0” (= falling edge).Note 2: Set this bit to “0” (= SI/O3, SI/O4)Note 3: When setting this bit to “0” (= SI/O3, SI/O4), make sure the S3IC and S4IC registers’ POL bit is set to “0” (= falling edge).

0 0

Nothing is assigned. When write, set to “0”. When read, its content is interdeterminate. (b5-b4)



Address Match InterruptAn address match interrupt is generated immediately before executing the instruction at the address indi-

cated by the RMADi register (i=0 to 3). Set the start address of any instruction in the RMADi register. Use

the AIER register’s AIER0 and AIER1 bits and the AIER2 register’s AIER20 and AIER21 bits to enable or

disable the interrupt. Note that the address match interrupt is unaffected by the I flag and IPL. For address

match interrupts, the value of the PC that is saved to the stack area varies depending on the instruction

being executed (refer to Saving Registers).

(The value of the PC that is saved to the stack area is not the correct return address.) Therefore, follow

one of the methods described below to return from the address match interrupt.

• Rewrite the content of the stack and then use the REIT instruction to return.

• Restore the stack to its previous state before the interrupt request was accepted by using the POP or

similar other instruction and then use a jump instruction to return.

Table 1.9.6 shows the value of the PC that is saved to the stack area when an address match interrupt

request is accepted.

Figure 1.9.11 shows the AIER, AIER2, and RMAD0 to RMAD3 registers.

Table 1.9.6. Value of the PC that is saved to the stack area when an address match interrupt

request is accepted

Table 1.9.7. Relationship Between Address Match Interrupt Sources and Associated Registers

Address match interrupt sources Address match interrupt enable bit Address match interrupt register

Address match interrupt 0 AIER0 RMAD0




• 16-bit op-code instruction• Instruction shown below among 8-bit operation code instructions ADD.B:S #IMM8,dest SUB.B:S #IMM8,dest AND.B:S #IMM8,dest OR.B:S #IMM8,dest MOV.B:S #IMM8,dest STZ.B:S #IMM8,dest STNZ.B:S #IMM8,dest STZX.B:S #IMM81,#IMM82,dest CMP.B:S #IMM8,dest PUSHM src POPM dest JMPS #IMM8 JSRS #IMM8 MOV.B:S #IMM,dest (However, dest=A0 or A1)

Instructions other than the above

Instruction at the Address Indicated by the RMADi RegisterValue of the PC that is saved to the stack area

The address indicated by the RMADi register +2

The address indicated by the RMADi register +1

Value of the PC that is saved to the stack area : Refer to Saving Registers.



Figure 1.9.11. AIER Register, AIER2 Register and RMAD0 to RMAD3 Registers

Bit nameBit symbol

Symbol Address After reset AIER 000916 XXXXXX002

Address match interrupt enable register

Function RWAddress match interrupt 0 enable bit

0 : Interrupt disabled1 : Interrupt enabled

AIER0

Address match interrupt 1 enable bit

AIER1

Symbol Address After reset RMAD0 001216 to 001016 X0000016RMAD1 001616 to 001416 X0000016RMAD2 01BA16 to 01B816 X0000016RMAD3 01BE16 to 01BC16 X0000016

b7 b6 b5 b4 b3 b2 b1 b0

Address setting register for address match interrupt

Function Setting range

Address match interrupt register i (i = 0 to 3)

0000016 to FFFFF16


b0 b7 b0b3(b19) (b16)

b7 b0(b15) (b8)

b7(b23)

Bit nameBit symbol

Symbol Address After reset AIER2 01BB16 XXXXXX002

Address match interrupt enable register 2

Function RWAddress match interrupt 2 enable bit


AIER20

Address match interrupt 3 enable bit

AIER21

b7 b6 b5 b4 b3 b2 b1 b0


RW

RW

(b7-b2)

RW

RW

(b7-b2)

RW

RW

Nothing is assigned.When write, set to “0”. When read, their contents are indeterminate.





Precautions for Interrupts

(1) Reading Address 0000016

• Do not read the address 0000016 in a program. When a maskable interrupt request is accepted, the

CPU reads interrupt information (interrupt number and interrupt request priority level) from the address

0000016 during the interrupt sequence. At this time, the IR bit for the accepted interrupt is cleared to “0”.

If the address 0000016 is read in a program, the IR bit for the interrupt which has the highest priority

among the enabled interrupts is cleared to “0”. This causes a problem that the interrupt is canceled, or

an unexpected interrupt is generated.

(2) SP Setting• Set any value in the SP before accepting an interrupt. The SP is cleared to ‘000016’ after reset. There-

fore, if an interrupt is accepted before setting any value in the SP, the program may go out of control._____

(3) INT Interrupt________

• Either an “L” level or an “H” level of at least 250 ns width is necessary for the signal input to the INT0________

through INT3 pins regardless of the CPU clock.________ ________

• When the polarity of the INT0 to INT3 pins is changed, the IR bit is sometimes set to “1” (=interrupt

requested). After changing the polarity, set the IR bit to “0” (=interrupt not requested). Figure 1.9.12______

shows the procedure for changing the INT interrupt generate factor.

(4) Watchdog Timer Interrupt

• Initialize the watchdog timer after the watchdog timer interrupt occurs.

______

Figure 1.9.12. Switching Procedure for INT Interrupt Request

Set the ILVL2 to ILVL0 bits to '0002' (= level 0)(Disable INT interrupt)

Set the POL bit

Set the ILVL2 to ILVL0 bits to '0012' (=level 1) to '1112' (=level 7)

(Enable the accepting of INT interrupt request)

Set the I flag to “0” (=disable interrupt)

Set the I flag to “1” (= enable interrupt)

Note: Execute the setting above individually. Do not execute two or more settings at once (by one instruction).

Set the IR bit to “0” (=interrupt not requested)



(5) Modifying Interrupt Control Register• Each interrupt control register can only be modified while no interrupt requests corresponding to that

register are generated. If interrupt requests managed by any interrupt control register are likely to occur,

disable the interrupts before modifying the register. A sample program is shown below.

To modify any interrupt control register after disabling interrupts, be careful with the instructions used.

Modifying other than the IR bit

If an interrupt request corresponding to that register is generated while executing the instruction, the IR

bit may not be set to “1” (= interrupt requested), with the result that the interrupt request is ignored. If this

presents a problem, use the following instructions to modify the register.

Instructions to use: AND, OR, BCLR, BSET

Modifying the IR bit

Even when the IR bit is cleared to “0” (= interrupt not requested), it may not actually be cleared to “0”

depending on the instruction used. Therefore, use the MOV instruction to clear the IR bit.

M16C/6S Group Watchdog Timer


Watchdog TimerThe watchdog timer is the function of detecting when the program is out of control. Therefore, we recom-

mend using the watchdog timer to improve reliability of a system. The watchdog timer contains a 15-bit

counter which counts down the clock derived by dividing the CPU clock using the prescaler. Whether to

generate a watchdog timer interrupt request or apply a watchdog timer reset as an operation to be per-

formed when the watchdog timer underflows after reaching the terminal count can be selected using the

PM12 bit of PM1 register. The PM12 bit can only be set to “1” (reset). Once this bit is set to “1”, it cannot be

set to “0” (watchdog timer interrupt) in a program.

The pin, CPU and SFR initialized where the monitor timer underflows when the PM12 bit is “1” are the same

as in software reset.

When the main clock is selected for CPU clock, the divide-by-N value for the prescaler can be chosen to be

16 or 128. The period of watchdog timer can be calculated as given below. The period of watchdog timer is,

however, subject to an error due to the prescaler.

For example, when CPU clock = 16 MHz and the divide-by-N value for the prescaler= 16, the watchdog

timer period is approx. 32.8 ms.

The watchdog timer is initialized by writing to the WDTS register. The prescaler is initialized after reset.

Note that the watchdog timer and the prescaler both are inactive after reset, so that the watchdog timer is

activated to start counting by writing to the WDTS register.

In stop mode and wait mode, the watchdog timer and prescaler are stopped. Counting is resumed from the

held value when the modes or state are released.

Figure 1.10.1 shows the block diagram of the watchdog timer. Figure 1.10.2 shows the watchdog timer-

related registers.

• Count source protective mode

In this mode, a On-chip Oscillator clock is used for the watchdog timer count source. The watchdog timer

can be kept being clocked even when CPU clock stops as a result of run-away.

Before this mode can be used, the following register settings are required:

(1) Set the PRC1 bit of PRCR register to “1” (enable writes to PM1 and PM2 registers).

(2) Set the PM12 bit of PM1 register to “1” (reset when the watchdog timer underflows).

(3) Set the PM22 bit of PM2 register to “1” (On-chip Oscillator clock used for the watchdog timer count source).

(4) Set the PRC1 bit of PRCR register to “0” (disable writes to PM1 and PM2 registers).

(5) Write to the WDTS register (watchdog timer starts counting).

With main clock chosen for CPU clock

Prescaler dividing (16 or 128) X Watchdog timer count (32768)

CPU clockWatchdog timer period =

M16C/6S Group Watchdog Timer


Figure 1.10.2. WDC Register and WDTS Register

CPUclock

Write to WDTS register

PM12 = 0

Watchdog timer

Set to “7FFF16”

1/128

1/16

CM07 = 0WDC7 = 1

CM07 = 0WDC7 = 0

CM07 = 1

HOLD

1/2

Prescaler

PM12 = 1

Watchdog timer interrupt request

Reset

PM22 = 0

PM22 = 1

On-chip Oscillator clock

Internal RESET signal(“L” active)

CM07: Bit in CM0 register WDC7: Bit in WDC registerPM12: Bit in PM1 registerPM22: Bit in PM2 register

Figure 1.10.1. Watchdog Timer Block Diagram

Setting the PM22 bit to “1” results in the following conditions

• The On-chip Oscillator starts oscillating, and the On-chip Oscillator clock becomes the watchdog timer

count source.

• The CM10 bit of CM1 register is disabled against write. (Writing a “1” has no effect, nor is stop mode

entered.)

• The watchdog timer does not stop when in wait mode.

Watchdog timer period =Watchdog timer count (32768)

on-chip oscillator clock

Watchdog timer control register

Symbol Address After reset WDC 000F16 00XXXXXX2

FunctionBit symbol RW

b7 b6 b5 b4 b3 b2 b1 b0

High-order bit of watchdog timer

WDC7

Bit name

Prescaler select bit 0 : Divided by 161 : Divided by 128


0 0

RO

RW

RW

(b4-b0)

(b6-b5)

Watchdog timer start register (Note)

Symbol Address After reset WDTS 000E16 Indeterminate

WO

b7 b0

Function

The watchdog timer is initialized and starts counting after a write instruction to this register. The watchdog timer value is always initialized to “7FFF16”regardless of whatever value is written.

RW

Note : Write to the WDTS register after the watchdog timer interrupt occurs.

M16C/6S Group DMAC


DMACThe DMAC (Direct Memory Access Controller) allows data to be transferred without the CPU intervention.Two DMAC channels are included. Each time a DMA request occurs, the DMAC transfers one (8 or 16-bit)data from the source address to the destination address. The DMAC uses the same data bus as used bythe CPU. Because the DMAC has higher priority of bus control than the CPU and because it makes use ofa cycle steal method, it can transfer one word (16 bits) or one byte (8 bits) of data within a very short timeafter a DMA request is generated. Figure 1.11.1 shows the block diagram of the DMAC. Table 1.11.1shows the DMAC specifications. Figures 1.11.2 to 1.11.4 show the DMAC-related registers.

Figure 1.11.1. DMAC Block Diagram

Data bus low-order bits

DMA latch high-order bits DMA latch low-order bits

DMA0 source pointer SAR0(20)

DMA0 destination pointer DAR0 (20)

DMA0 forward address pointer (20) (Note)

Data bus high-order bits

Address bus

DMA1 destination pointer DAR1 (20)

DMA1 source pointer SAR1 (20)

DMA1 forward address pointer (20) (Note)

DMA0 transfer counter reload register TCR0 (16)

DMA0 transfer counter TCR0 (16)

DMA1 transfer counter reload register TCR1 (16)

DMA1 transfer counter TCR1 (16)

(addresses 002916, 002816)

(addresses 003916, 003816)

(addresses 002216 to 002016)

(addresses 002616 to 002416)

(addresses 003216 to 003016)

(addresses 003616 to 003416)

Note: Pointer is incremented by a DMA request.

A DMA request is generated by a write to the DMiSL register (i = 0–1)’s DSR bit, as well as by an interrupt

request which is generated by any function specified by the DMiSL register’s DMS and DSEL3–DSEL0 bits.

However, unlike in the case of interrupt requests, DMA requests are not affected by the I flag and the

interrupt control register, so that even when interrupt requests are disabled and no interrupt request can be

accepted, DMA requests are always accepted. Furthermore, because the DMAC does not affect interrupts,

the interrupt control register’s IR bit does not change state due to a DMA transfer.

A data transfer is initiated each time a DMA request is generated when the DMiCON register’s DMAE bit =

“1” (DMA enabled). However, if the cycle in which a DMA request is generated is faster than the DMA

transfer cycle, the number of transfer requests generated and the number of times data is transferred may

not match. For details, refer to “DMA Requests”.

M16C/6S Group DMAC


Item SpecificationNo. of channels 2 (cycle steal method)Transfer memory space • From any address in the 1M bytes space to a fixed address

• From a fixed address to any address in the 1M bytes space• From a fixed address to a fixed address

Maximum No. of bytes transferred 128K bytes (with 16-bit transfers) or 64K bytes (with 8-bit transfers)

DMA request factors________ ________

Falling edge of INT0 or INT1 (Note 1, Note 2)

________ ________

Both edge of INT0 or INT1Timer A0 to timer A4 interrupt requestsUART0 transfer, UART0 reception interrupt requestsUART1 transfer, UART1 reception interrupt requestsUART2 transfer, UART2 reception interrupt requestsSI/O3, SI/O4 interrupt requestsSoftware triggers

Channel priority DMA0 > DMA1 (DMA0 takes precedence)Transfer unit 8 bits or 16 bitsTransfer address direction forward or fixed (The source and destination addresses cannot both be

in the forward direction.)Transfer mode •Single transfer Transfer is completed when the DMAi transfer counter (i = 0–1)

underflows after reaching the terminal count.•Repeat transfer When the DMAi transfer counter underflows, it is reloaded with the value

of the DMAi transfer counter reload register and a DMA transfer is continued with it.

DMA interrupt request generation timing When the DMAi transfer counter underflowedDMA startup Data transfer is initiated each time a DMA request is generated when the

DMAiCON register’s DMAE bit = “1” (enabled).

DMA shutdown •Single transfer •When the DMAE bit is set to “0” (disabled)•After the DMAi transfer counter underflows

•Repeat transfer When the DMAE bit is set to “0” (disabled)When a data transfer is started after setting the DMAE bit to “1” (enabled), the forward address pointer is reloaded with the value of theSARi or the DARi pointer whichever is specified to be in the forwarddirection and the DMAi transfer counter is reloaded with the value of theDMAi transfer counter reload register.

Table 1.11.1. DMAC Specifications

Notes:

1. DMA transfer is not effective to any interrupt. DMA transfer is affected neither by the I flag nor by the

interrupt control register.

2. The selectable causes of DMA requests differ with each channel.

3. Make sure that no DMAC-related registers (addresses 002016–003F16) are accessed by the DMAC.

Reload timing for forward ad-

dress pointer and transfer

counter

M16C/6S Group DMAC


DMA0 request cause select register

Symbol Address After reset DM0SL 03B816 0016

FunctionBit symbol

b7 b6 b5 b4 b3 b2 b1 b0

DMA request cause select bit

DSEL0

RW

DSEL1

DSEL2

DSEL3

Nothing is assigned. When write, set to “0”. When read, its content is “0”.

Software DMA request bit

A DMA request is generated by setting this bit to “1” when the DMS bit is “0” (basic cause) and the DSEL3 to DSEL0 bits are “00012” (software trigger).The value of this bit when read is “0” .

DSR

DSEL3 to DSEL0 DMS=0(basic cause of request) DMS=1(extended cause of request)0 0 0 02 Falling edge of INT0 pin – 0 0 0 12 Software trigger – 0 0 1 02 Timer A0 –0 0 1 12 Timer A1 –0 1 0 02 Timer A2 –0 1 0 12 Timer A3 –0 1 1 02 Timer A4 Two edges of INT0 pin 0 1 1 12 1 0 0 02 1 0 0 12 1 0 1 02 UART0 transmit –

– – –

1 0 1 12 UART0 receive –1 1 0 02 UART2 transmit – 1 1 0 12 UART2 receive –1 1 1 02 –

– – –

–1 1 1 12 UART1 transmit –

Bit name

DMA request cause expansion select bitDMS 0: Basic cause of request

1: Extended cause of request

RW

RW

RW

RW

RW

RW

(b5-b4)

Refer to note

Note: The causes of DMA0 requests can be selected by a combination of DMS bit and DSEL3 to DSEL0 bits in the manner described below.

Figure 1.11.2. DM0SL Register

M16C/6S Group DMAC


DMAi control register(i=0,1)

Symbol Address After reset DM0CON 002C16 00000X002DM1CON 003C16 00000X002


Transfer unit bit select bit

b7 b6 b5 b4 b3 b2 b1 b0

0 : 16 bits1 : 8 bits

DMBIT

DMASL

DMAS

DMAE

Repeat transfer mode select bit

0 : Single transfer1 : Repeat transfer

DMA request bit 0 : DMA not requested1 : DMA requested

0 : Disabled1 : Enabled

0 : Fixed1 : Forward

DMA enable bit

Source address direction select bit (Note 2)

Destination address direction select bit (Note 2)

0 : Fixed1 : Forward

DSD

DAD


Note 1: The DMAS bit can be set to “0” by writing “0” in a program (This bit remains unchanged even if “1” is written).Note 2: At least one of the DAD and DSD bits must be “0” (address direction fixed).

(Note 1)

DMA1 request cause select register

Symbol Address After reset DM1SL 03BA16 0016

FunctionBit symbol

b7 b6 b5 b4 b3 b2 b1 b0

DMA request cause select bit

DSEL0

RW

DSEL1DSEL2

DSEL3

Software DMA request bit

DSR

DSEL3 to DSEL0 DMS=0(basic cause of request) DMS=1(extended cause of request)0 0 0 02 Falling edge of INT1 pin – 0 0 0 12 Software trigger –0 0 1 02 Timer A0 –0 0 1 12 Timer A1 –0 1 0 02 Timer A2 –0 1 0 12 Timer A3 SI/O3 0 1 1 02 Timer A4 SI/O4 0 1 1 12 Two edges of INT1 1 0 0 02 – 1 0 0 12 – 1 0 1 02 UART0 transmit – 1 0 1 12 UART0 receive/ACK0 – 1 1 0 02 UART2 transmit – 1 1 0 12 UART2 receive/ACK2 – 1 1 1 02 –

– –

–

– 1 1 1 12 UART1 receive/ACK1 –

Bit name

DMA request cause expansion select bit

DMS

RW

RW

RW

RW

RW

RW

(b5-b4)

RW

RW

RW

RW

RW

RW

RW

(b7-b6)

Note: The causes of DMA1 requests can be selected by a combination of DMS bit and DSEL3 to DSEL0 bits in the manner described below.


A DMA request is generated by setting this bit to “1” when the DMS bit is “0” (basic cause) and the DSEL3 to DSEL0 bits are “00012” (software trigger).The value of this bit when read is “0” .

0: Basic cause of request1: Extended cause of request

Refer to note

Figure 1.11.3. DM1SL Register, DM0CON Register, and DM1CON Registers

M16C/6S Group DMAC


b7 b0 b7 b0(b8)(b15)

Function

Set the transfer count minus 1. The written value is stored in the DMAi transfer counter reload register, and when the DMAE bit of DMiCON register is set to “1” (DMA enabled) or the DMAi transfer counter underflows when the DMASL bit of DMiCON register is “1” (repeat transfer), the value of the DMAi transfer counter reload register is transferred to the DMAi transfer counter.When read, the DMAi transfer counter is read.

Symbol Address After reset TCR0 002916, 002816 Indeterminate TCR1 003916, 003816 Indeterminate

DMAi transfer counter (i = 0, 1)

Setting range

000016 to FFFF16

b7(b23)

b3 b0 b7 b0 b7 b0(b8)(b16)(b15)(b19)

Function RW

Set the source address of transfer

Symbol Address After reset SAR0 002216 to 002016 Indeterminate SAR1 003216 to 003016 Indeterminate

DMAi source pointer (i = 0, 1) (Note)

Setting range

0000016 to FFFFF16

Nothing is assigned. When write, set “0”. When read, these contents are “0”.

Symbol Address After reset DAR0 002616 to 002416 Indeterminate DAR1 003616 to 003416 Indeterminate

b3 b0 b7 b0 b7 b0(b8)(b15)(b16)(b19)

Function

Set the destination address of transfer

DMAi destination pointer (i = 0, 1)(Note)

Setting range

0000016 to FFFFF16

b7(b23)

RW

RW

RW

RW

RW

Note: If the DSD bit of DMiCON register is “0” (fixed), this register can only be written to when the DMAE bit of DMiCON register is “0” (DMA disabled). If the DSD bit is “1” (forward direction), this register can be written to at any time. If the DSD bit is “1” and the DMAE bit is “1” (DMA enabled), the DMAi forward address pointer can be read from this register. Otherwise, the value written to it can be read.

Nothing is assigned. When write, set “0”. When read, these contents are “0”.

Note: If the DAD bit of DMiCON register is “0” (fixed), this register can only be written to when the DMAE bit of DMiCON register is “0”(DMA disabled). If the DAD bit is “1” (forward direction), this register can be written to at any time. If the DAD bit is “1” and the DMAE bit is “1” (DMA enabled), the DMAi forward address pointer can be read from this register. Otherwise, the value written to it can be read.

Figure 1.11.4. SAR0, SAR1, DAR0, DAR1, TCR0, and TCR1 Registers

M16C/6S Group DMAC


1. Transfer CyclesThe transfer cycle consists of a memory or SFR read (source read) bus cycle and a write (destination

write) bus cycle. The number of read and write bus cycles is affected by the source and destination________

addresses of transfer. Furthermore, the bus cycle itself is extended by a software wait or RDY signal.

(a) Effect of Source and Destination Addresses

If the transfer unit and data bus both are 16 bits and the source address of transfer begins with an odd

address, the source read cycle consists of one more bus cycle than when the source address of

transfer begins with an even address.

Similarly, if the transfer unit and data bus both are 16 bits and the destination address of transfer

begins with an odd address, the destination write cycle consists of one more bus cycle than when the

destination address of transfer begins with an even address.

(b) Effect of Software Wait

For memory or SFR accesses in which one or more software wait states are inserted, the number of

bus cycles required for that access increases by an amount equal to software wait states.

Figure 1.11.5 shows the example of the cycles for a source read. For convenience, the destination write

cycle is shown as one cycle and the source read cycles for the different conditions are shown. In reality,

the destination write cycle is subject to the same conditions as the source read cycle, with the transfer

cycle changing accordingly. When calculating transfer cycles, take into consideration each condition for

the source read and the destination write cycle, respectively. For example, when data is transferred in 16

bit units using an 8-bit bus ((2) in Figure 1.11.5), two source read bus cycles and two destination write bus

cycles are required.

M16C/6S Group DMAC


BCLK

Address bus

RD signal

WR signal

Data bus

CPU use

CPU use CPU use

CPU useSource

Source

Destination

Destination

Dummy cycle

Dummy cycle

(1) When the transfer unit is 8 or 16 bits and the source of transfer is an even address

BCLK

Address bus

RD signal

WR signal

Data bus

CPU use

CPU use CPU use

CPU useSource

Source

Destination

Destination

Dummy cycle

Dummy cycle

(3) When the source read cycle under condition (1) has one wait state inserted

BCLK

Address bus

RD signal

WR signal

Data bus

CPU use

CPU use CPU use

CPU useSource

Source

Destination

Destination

Dummy cycle

Dummy cycle

Source + 1

Source + 1

(2) When the transfer unit is 16 bits and the source address of transfer is an odd address

BCLK

Address bus

RD signal

WR signal

Data bus

CPU use

CPU use CPU use

CPU useSource

Source

Destination

Destination

Dummy cycle

Dummy cycle

Source + 1

Source + 1

(4) When the source read cycle under condition (2) has one wait state inserted

Note: The same timing changes occur with the respective conditions at the destination as at the source.

Figure 1.11.5. Transfer Cycles for Source Read

M16C/6S Group DMAC


Transfer unit Access address No. of read No. of write

cycles cycles

8-bit transfers Even 1 1

(DMBIT= “1”) Odd 1 1

16-bit transfers Even 1 1

(DMBIT= “0”) Odd 2 2

Table 1.11.2. DMA Transfer Cycles

Table 1.11.3. Coefficient j, kInternal ROM, RAM SFR

No wait With wait

1

1

2

2

3

3

j

k

Notes: 1. Depends on the set value of CSE register 2. Depends on the set value of PM20 bit in P

2

2

1-wait2 2-wait2

2. DMA Transfer CyclesAny combination of even or odd transfer read and write addresses is possible. Table 1.11.2 shows the

number of DMA transfer cycles. Table 1.11.3 shows the Coefficient j, k.

The number of DMAC transfer cycles can be calculated as follows:

No. of transfer cycles per transfer unit = No. of read cycles x j + No. of write cycles x k

M16C/6S Group DMAC


3. DMA EnableWhen a data transfer starts after setting the DMAE bit in DMiCON register (i = 0, 1) to “1” (enabled), the

DMAC operates as follows:

(1) Reload the forward address pointer with the SARi register value when the DSD bit in DMiCON register

is “1” (forward) or the DARi register value when the DAD bit of DMiCON register is “1” (forward).

(2) Reload the DMAi transfer counter with the DMAi transfer counter reload register value.

If the DMAE bit is set to “1” again while it remains set, the DMAC performs the above operation. However,

if a DMA request may occur simultaneously when the DMAE bit is being written, follow the steps below.

Step 1: Write “1” to the DMAE bit and DMAS bit in DMiCON register simultaneously.

Step 2: Make sure that the DMAi is in an initial state as described above (1) and (2) in a program.

If the DMAi is not in an initial state, the above steps should be repeated.

4. DMA RequestThe DMAC can generate a DMA request as triggered by the cause of request that is selected with the

DMS and DSEL3 to DSEL0 bits of DMiSL register (i = 0, 1) on either channel. Table 1.11.4 shows the

timing at which the DMAS bit changes state.

Whenever a DMA request is generated, the DMAS bit is set to “1” (DMA requested) regardless of whether

or not the DMAE bit is set. If the DMAE bit was set to “1” (enabled) when this occurred, the DMAS bit is

set to “0” (DMA not requested) immediately before a data transfer starts. This bit cannot be set to “1” in

a program (it can only be set to “0”).

The DMAS bit may be set to “1” when the DMS or the DSEL3 to DSEL0 bits change state. Therefore,

always be sure to set the DMAS bit to “0” after changing the DMS or the DSEL3 to DSEL0 bits.

Because if the DMAE bit is “1”, a data transfer starts immediately after a DMA request is generated, the

DMAS bit in almost all cases is “0” when read in a program. Read the DMAE bit to determine whether the

DMAC is enabled.

Table 1.11.4. Timing at Which the DMAS Bit Changes State

DMA factor

Software trigger

Peripheral function

Timing at which the bit is set to “1” Timing at which the bit is set to “0” DMAS bit of the DMiCON register

When the DSR bit of DMiCON register is set to “1”

When the interrupt control register for the peripheral function that is selected by the DSEL3 to DSEL0 and DMS bits of DMiCON register has its IR bit set to “1”

• Immediately before a data transfer starts• When set by writing “0” in a program

M16C/6S Group DMAC


5. Channel Priority and DMA Transfer TimingIf both DMA0 and DMA1 are enabled and DMA transfer request signals from DMA0 and DMA1 are

detected active in the same sampling period (one period from a falling edge to the next falling edge of

BCLK), the DMAS bit on each channel is set to “1” (DMA requested) at the same time. In this case, the

DMA requests are arbitrated according to the channel priority, DMA0 > DMA1. The following describes

DMAC operation when DMA0 and DMA1 requests are detected active in the same sampling period.

Figure 1.11.6 shows an example of DMA transfer effected by external factors.

In Figure 1.11.6, because DMA0 and DMA1 requests occurred at the same time, DMA0 which has higher

channel priority is accepted first and a DMA transfer on it starts. When DMA0 finishes one transfer unit, it

relinquishes control of the bus to the CPU, and when the CPU finishes one bus access, DMA1 starts a

transfer next and after completion of one transfer unit, returns control of the bus to the CPU.

Note that because there is only one DMAS bit on each channel, the number of times DMA is requested

cannot be counted. Therefore, even if multiple DMA requests occurred before gaining control of the bus

as in the case of DMA1 in Figure 1.11.6, the DMAS bit is set to “0” when control of the bus is gained and

after completion of one transfer unit, control of the bus is returned to the CPU.

BCLK

DMA0

DMA1

DMA0request bit

DMA1request bit

CPU

INT0

INT1

Obtainment of the bus right

An example where DMA requests for external causes are detected active at the same

Figure 1.11.6. DMA Transfer by External Factors

M16C/6S Group Timers


TimersFive 16-bit timers, each capable of operating independently of the others. The count source for each timer

acts as a clock, to control such timer operations as counting, reloading, etc. Figures 1.12.1 show block

diagrams of timer A.

Figure 1.12.1. Timer A Configuration

1/8

1/4

f1 or f2

f8

f32

• Main clock• On-chip oscillator clock

NOTES : 1. Be aware that TA0IN shares the pin with RXD2.

1/2

f1

f2 PCLK0 bit = 0

PCLK0 bit = 1

00: Timer mode10: One-shot timer mode11: PWM mode

01: Event counter modeTA0IN

TA1IN

TA2IN

TA3IN

TA4IN

Timer A0

Timer A1

Timer A2

Timer A3

Timer A4

Timer A0 interrupt

Timer A1 interrupt

Timer A2 interrupt

Timer A3 interrupt

Timer A4 interrupt

Noise filter

Noise filter

Noise filter

Noise filter

Noise filter

00011011

TCK1 to TCK0

00: Timer mode10: One-shot tiemr mode11: PWM mode




01: Event counter mode




TCK1 to TCK0

TCK1 to TCK0

TCK1 to TCK0

TCK1 to TCK0

TMOD1 to TMOD0

TMOD1 to TMOD0

TMOD1 to TMOD0

TA0TGH to TA0TGL

00011011

00011011

00011011

00011011

00

11

10

00

11

10

00

11

10

00

11

10

00

11

10

TCK1 to TCK0, TMOD1 to TMOD0 : Bits in TAiMR register (i=0 to 4)TAiGH to TAiGL: Bits in ONSF register and TRGSR register

TA1TGH to TA1TGL

TA2TGH to TA2TGL

TA3TGH to TA3TGL

TA4TGH to TA4TGL

TMOD1 to TMOD0

TMOD1 to TMOD0

f8 f32 fC32f1 or f2

M16C/6S Group Timer A


Timer AFigure 1.12.2 shows a block diagram of the timer A. Figures 1.12.3 to 1.12.5 show registers related to the

timer A.

The timer A supports the following four modes. Except in event counter mode, timers A0 to A4 all have the

same function. Use the TMOD1 to TMOD0 bits of TAiMR register (i = 0 to 4) to select the desired mode.

• Timer mode: The timer counts an internal count source.

• Event counter mode: The timer counts pulses from an external device or overflows and underflows of

other timers.

• One-shot timer mode: The timer outputs a pulse only once before it reaches the minimum count

“000016.”

• Pulse width modulation (PWM) mode: The timer outputs pulses in a given width successively.

Figure 1.12.3. TA0MR to TA4MR Registers

TAi Addresses TAj TAkTimer A0 0387h - 0386h Timer A4 Timer A1Timer A1 0389h - 0388h Timer A0 Timer A2Timer A2 038Bh - 038Ah Timer A1 Timer A3Timer A3 038Dh - 038Ch Timer A2 Timer A4Timer A4 038Fh - 038Eh Timer A3 Timer A0

f1 or f2

f8

f32

TAiS

Increment / decrement

Select Count Source

• Timer(gate function):TMOD1 to TMOD0=00, MR2=1

• Timer :TMOD1 to TMOD0=00, MR2=0• One-Shot Timer :TMOD1 to TMOD0=10• Pulse Width Modulation:TMOD1 to TMOD0=11

TAiIN

• Event counter:TMOD1 to TMOD0=01

Select clock

TAj Overflow (1)

Pulse Output

Toggle Flip FlopTAiOUT

Always decrement except in event counter mode

8 low-order bits

Reload Register

Counter

Low-Order Bits of Data Bus

TAiUD

Decrement

TAk Overflow (1)

Polarity Selector

00

01

10

TCK1 to TCK0

00

10

11

TAiTGH to TAiTGL

11

01

0100

0

1

MR2

TMOD1 to TMOD0

NOTES:1. Overflow or underflow

TCK1 to TCK0, TMOD1 to TMOC0, MR2 to MR1 : Bits in TAiMR registerTAiTGH to TAiTGL : Bits in ONSF register if i=0 or bits in TRGSR register if i=1 to 4TAiS : Bits in the TABSR registerTAiUD : Bits in the UDF register

TMOD1 to TMOD0,MR2

i=0 to 4j=i-1, except j=4 if i=0 k=i+1, except k=0 if i=4

8 high-order bits

To external trigger circuit

High-Order Bits of Data Bus

Timer Ai mode register (i=0 to 4) Symbol Address After reset TA0MR to TA4MR 039616 to 039A16 0016


b7 b6 b5 b4 b3 b2 b1 b0

0 0 : Timer mode 0 1 : Event counter mode 1 0 : One-shot timer mode 1 1 : Pulse width modulation (PWM) mode

b1 b0

TCK1

MR3

MR2

MR1

TMOD1

MR0

TMOD0

TCK0

Function varies with each operation mode

Count source select bit

Operation mode select bit RW

RW

RW

RW

RW

RW

RW

RWFunction varies with each operation mode

Figure 1.12.2. Timer A Block Diagram



Figure 1.12.4. TA0 to TA4 Registers, TABSR Register, and UDF Register

Symbol Address After reset TA0 038716, 038616 Indeterminate TA1 038916, 038816 Indeterminate TA2 038B16, 038A16 Indeterminate TA3 038D16, 038C16 Indeterminate TA4 038F16, 038E16 Indeterminate

b7 b0 b7 b0(b15) (b8)

Timer Ai register (i= 0 to 4) (Note 1)

RW

Divide the count source by n + 1 where n = set value

Function Setting range

Divide the count source by FFFF16 – n + 1 where n = set value when counting up or by n + 1 when counting down

Divide the count source by n where n = set value and cause the timer to stop

Modify the pulse width as follows:PWM period: (216 – 1) / fjHigh level PWM pulse width: n / fj where n = set value, fj = count source frequency

000016 to FFFE16 (Note 3, 4)

Note 1: The register must be accessed in 16 bit units.Note 2: If the TAi register is set to ‘000016,’ the counter does not work and timer Ai interrupt

requests are not generated either. Furthermore, if “pulse output” is selected, no pulses are output from the TAiOUT pin.

Note 3: If the TAi register is set to ‘000016,’ the pulse width modulator does not work, the output level on the TAiOUT pin remains low, and timer Ai interrupt requests are not generated either. The same applies when the 8 high-order bits of the timer TAi register are set to ‘0016’ while operating as an 8-bit pulse width modulator.

Note 4: Use the MOV instruction to write to the TAi register.Note 5: The timer counts pulses from an external device or overflows or underflows in other timers.

0016 to FE16(High-order address)

0016 to FF16(Low-order address)

Timer A4 up/down flag





Timer A2 two-phase pulse signal processing select bit



Symbol Address After reset UDF 038416 0016

TA4P

TA3P

TA2P

Up/down flag (Note 1)


b7 b6 b5 b4 b3 b2 b1 b0

TA4UD

TA3UD

TA2UD

TA1UD

TA0UD 0 : Down count 1 : Up count

Enabled by setting the TAiMR register’s MR2 bit to “0”(= switching source in UDF register) during event counter mode.

0 : two-phase pulse signal processing disabled1 : two-phase pulse signal processing enabled

Symbol Address After reset TABSR 038016 0016

Count start flag


b7 b6 b5 b4 b3 b2 b1 b0

Timer A4 count start flag




Timer A0 count start flag 0 : Stops counting1 : Starts counting

TA4S

TA3S

TA2S

TA1S

TA0S

Note 1: Use MOV instruction to write to this register. Note 2: Make sure the port direction bits for the TA2IN to TA4IN and TA2OUT to TA4OUT pins are set

to “0” (input mode).Note 3: When not using the two-phase pulse signal processing function, set the corresponding bit

to “0” (TA2P and TA3P must be set “0”).

RW

RW

WO

WO

WO

RW

RW

RW

RW

RW

RW

RW

RW

RW

RW

RW

WO

WO

WO

Timer modeEvent counter mode

One-shot timer mode

Pulse width modulation mode(16-bit PWM)

Pulse width modulation mode(8-bit PWM)

000016 to FFFF16

000016 to FFFF16

000016 to FFFF16 (Notes 2, 4)

Mode

Modify the pulse width as follows:PWM period: (28 – 1) x (m + 1)/ fjHigh level PWM pulse width: (m + 1)n / fj where n = high-order address set value, m = low-order address set value, fj = count source frequency

(Note 3, 4)

(Notes 2, 3)

(Note 5)




TA1TGL

Symbol Address After reset TRGSR 038316 0016

Timer A1 event/trigger select bit 0 0 : Input on TA1IN is selected (Note 1)

1 0 : TA0 overflow is selected 1 1 : TA2 overflow is selected

Trigger select register


b7 b6 b5 b4 b3 b2 b1 b0



0 0 : Input on TA4IN is selected (Note 1) 1 0 : TA3 overflow is selected 1 1 : TA0 overflow is selected

Timer A2 event/trigger select bit



TA1TGH

TA2TGL

TA2TGH

TA3TGL

TA3TGH

TA4TGL

TA4TGH

b1 b0

b3 b2

b5 b4

b7 b6

Note 1: Make sure the port direction bits for the TA1IN to TA4IN pins are set to “0” (= input mode).Note 2: Overflow or underflowNote 3: Do not set cases which are not discribed.

TA1OS

TA2OS

TA0OS

One-shot start flagSymbol Address After reset ONSF 038216 0016

Timer A0 one-shot start flag





TA3OS

TA4OS


b7 b6 b5 b4 b3 b2 b1 b0

TA0TGL

TA0TGH

0 0 : Input on TA0IN is selected0 1 : TB2 overflow is selected1 0 : TA4 overflow is selected1 1 : TA1 overflow is selected

Timer A0 event/triggerselect bit

b7 b6

RW

The timer starts counting by setting this bit to “1” while the TMOD1 to TMOD0 bits of TAiMR register (i = 0 to 4) = ‘102’ (= one-shot timer mode) and the MR2 bit of TAiMR register = “0” (=TAiOS bit enabled). When read, its content is “0”.

RW

RW

RW

RW

RW

RW

RW

RW

RW

RW

RW

RW

RW

RW

RW

RW

RW

(Note 2) (Note 2)

(Note 2) (Note 2)

(Note 2) (Note 2)

(Note 2) (Note 2)

(Note 2) (Note 2) (Note 2)

Note 1: Make sure the PD7_1 bit of PD7 register is set to “0” (= input mode).Note 2: Overflow or underflow

(Note 1)

Should be set to “0”. (b6)

Reserved bit

0

(Note 3)

(Note 3)

(Note 3)

(Note 3)

Figure 1.12.5. ONSF Register, TRGSR Register, and CPSRF Register



Item Specification

Count source f1, f2, f8, f32

Count operation • Down-count

• When the timer underflows, it reloads the reload register contents and continues counting

Divide ratio 1/(n+1) n: set value of TAiMR register (i= 0 to 4) 000016 to FFFF16

Count start condition Set TAiS bit of TABSR register to “1” (= start counting)

Count stop condition Set TAiS bit to “0” (= stop counting)

Interrupt request generation timing Timer underflow

TAiIN pin function I/O port or gate input i≠2, 3

TAiOUT pin function I/O port or pulse output

Read from timer Count value can be read by reading TAi register

Write to timer • When not counting and until the 1st count source is input after counting start

Value written to TAi register is written to both reload register and counter

• When counting (after 1st count source input)

Value written to TAi register is written to only reload register

(Transferred to counter when reloaded next)

Select function • Gate function

Counting can be started and stopped by an input signal to TAiIN pin

• Pulse output function

Whenever the timer underflows, the output polarity of TAiOUT pin is inverted.

When not counting, the pin outputs a low.

1. Timer ModeIn timer mode, the timer counts a count source generated internally (see Table 1.12.1). Figure 1.12.6

shows TAiMR register in timer mode.

Table 1.12.1. Specifications in Timer Mode

Note 1: TA0OUT pin is N-channel open drain output.Note 2: The port direction bit for the TAi

There are not TA2IN and TA3IN.

IN pin must be set to “0” (= input mode).

Timer Ai mode register (i=0 to 4)

Symbol Address After reset TA0MR to TA4MR 039616 to 039A16 0016


b7 b6 b5 b4 b3 b2 b1 b0

Operation mode select bit 0 0 : Timer mode

b1 b0

TMOD1

TMOD0

MR0 Pulse output function select bit

0 : Pulse is not output (TAiOUT pin is a normal port pin)1 : Pulse is output (Note 1) (TAiOUT pin is a pulse output pin)

Gate function select bit0 0 : Gate function not available0 1 : (TAiIN pin functions as I/O port)1 0 : Counts while input on the TAi IN pin is low (Note 2)1 1 : Counts while input on the TAi IN pin is high (Note 2)

b4 b3

MR2

MR1

MR3 Must be set to “0” in timer mode

0 0 : f1 or f2 0 1 : f8 1 0 : f1 1 : Do not set

32

b7 b6

TCK1

TCK0 Count source select bit

0 00

RW

RW

RW

RW

RW

RW

RW

RW

Figure 1.12.6. Timer Ai Mode Register in Timer Mode



Item SpecificationCount source • External signals input to TAiIN pin (i=0 to 4) (effective edge can be selected

in program)timer Aj (j=i-1, except j=4 if i=0) overflows or underflows,timer Ak (k=i+1, except k=0 if i=4) overflows or underflows

Count operation • Up-count or down-count can be selected by external signal or program• When the timer overflows or underflows, it reloads the reload register con-

tents and continues counting. When operating in free-running mode, thetimer continues counting without reloading.

Divided ratio 1/ (FFFF16 - n + 1) for up-count1/ (n + 1) for down-count n : set value of TAi register 000016 to FFFF16


Count stop condition Set TAiS bit to “0” (= stop counting)Interrupt request generation timing Timer overflow or underflowTAiIN pin function I/O port or count source input i≠2, 3TAiOUT pin function I/O port, pulse output, or up/down-count select inputRead from timer Count value can be read by reading TAi registerWrite to timer • When not counting and until the 1st count source is input after counting start

Value written to TAi register is written to both reload register and counter


Value written to TAi register is written to only reload register

(Transferred to counter when reloaded next)Select function • Free-run count function

Even when the timer overflows or underflows, the reload register content isnot reloaded to it

• Pulse output functionWhenever the timer underflows or underflows, the output polarity of TAiOUT

pin is inverted . When not counting, the pin outputs a low.

2. Event Counter ModeIn event counter mode, the timer counts pulses from an external device or overflows and underflows ofother timers. Timer A4 can count two-phase external signals. Table 1.12.2 lists specifications in eventcounter mode (when not processing two-phase pulse signal). Table 1.12.3 lists specifications in eventcounter mode (when processing two-phase pulse signal with the timer A4). Figure 1.12.7 shows TAiMRregister in event counter mode (when not processing two-phase pulse signal). Figure 1.12.8 showsTA4MR registers in event counter mode (when processing two-phase pulse signal with the timer A4).

Table 1.12.2. Specifications in Event Counter Mode (when not processing two-phase pulse signal)



Note 1: During event counter mode, the count source can be selected using the ONSF and TRGSR registers.

Note 2: TA0OUT pin is N-channel open drain output.Note 3: Effective when the TAiGH and TAiGL bits of ONSF or TRGSR register are ‘002’ (TAiIN pin input). Note 4: Count down when input on TAiOUT pin is low or count up when input on that pin is high. The port

direction bit for TAiOUT pin must be set to “0” (= input mode).


WR

b7 b6 b5 b4 b3 b2 b1 b0

Operation mode select bit0 1 : Event counter mode (Note 1)b1 b0 TMOD0

MR0 Pulse output functionselect bit

0 : Pulse is not output (TAiOUT pin functions as I/O port)1 : Pulse is output (Note 2) (TAiOUT pin functions as pulse output pin)

Count polarity select bit (Note 3)

MR2

MR1

MR3 Must be set to “0” in event counter mode

TCK0 Count operation type select bit

0 10

0 : Counts external signal's falling edge1 : Counts external signal's rising edge

Up/down switching cause select bit

0 : UDF register1 : Input signal to TAiOUT pin (Note 4)

0 : Reload type1 : Free-run type

Bit symbol Bit name Function RW

TCK1 Can be “0” or “1” when not using two-phase pulse signal processing

TMOD1

Timer Ai mode register (i=0 to 4)(When not using two-phase pulse signal processing)

RWRW

RW

RW

RW

RW

RW

RW

Figure 1.12.7. TAiMR Register in Event Counter Mode (when not using two-phase pulse signalprocessing)



Item Specification

Count source • Two-phase pulse signals input to TAiIN or TAiOUT pins (i = 4)

Count operation • Up-count or down-count can be selected by two-phase pulse signal• When the timer overflows or underflows, it reloads the reload register con-

tents and continues counting. When operating in free-running mode, thetimer continues counting without reloading.

Divide ratio 1/ (FFFF16 - n + 1) for up-count

1/ (n + 1) for down-count n : set value of TAi register 000016 to FFFF16


Count stop condition Set TAiS bit to “0” (= stop counting)

Interrupt request generation timing Timer overflow or underflow

TAiIN pin function Two-phase pulse input

TAiOUT pin function Two-phase pulse input

Read from timer Count value can be read by reading timer A4 register

Write to timer • When not counting and until the 1st count source is input after counting startValue written to TAi register is written to both reload register and counter


Value written to TAi register is written to reload register

(Transferred to counter when reloaded next)Select function • Multiply-by-4 processing operation (timer A4)

If the phase relationship is such that TAkIN(k=4) pin goes “H” when the inputsignal on TAkOUT pin is “H”, the timer counts up rising and falling edges onTAkOUT and TAkIN pins. If the phase relationship is such that TAkIN pingoes “L” when the input signal on TAkOUT pin is “H”, the timer counts downrising and falling edges on TAkOUT and TAkIN pins.

Table 1.12.3 shows the Specifications in event counter mode (when processing two-phase pulse signal

with timer A4), and Figure 1.12.8 shows the TA4MR registers in event counter mode (when using two-

phase pulse signal processing with timer A4).

Table 1.12.3. Specifications in Event Counter Mode (when processing two-phase pulse signal with timer A4)

TAkOUT

TAkIN

(k=3,4)

Count up all edges

Count up all edges

Count down all edges

Count down all edges



NOTES: 1. No matter how this bit is set, timer A4 always operates in x4 processing mode.2. If two-phase pulse signal processing is desired, following register settings are required:

• Set the TAiP bit in the UDF register to “1” (two-phase pulse signal processing function enabled).• Set the TAiTGH and TAiTGL bits in the TRGSR register to “00b” (TAiIN pin input).• Set the port direction bits for TAiIN and TAiOUT to “0” (input mode).

Timer Ai Mode Register (i=4) (When Using Two-Phase Pulse Signal Processing)

Symbol Address After ResetTA4MR 039Ah 00h

b6 b5 b4 b3 b2 b1 b0

Operation Mode Select Bit0 1 : Event counter modeb1 b0

TMOD1

TMOD0

MR0 To use two-phase pulse signal processing, set this bit to “0”.

MR2

MR1

MR3

TCK1

TCK0

0 10

Bit Name Function RW

Count Operation Type Select Bit

Two-Phase Pulse Signal Processing Operation Select Bit (1, 2)

0 : Reload type1 : Free-run type

0 : Normal processing operation1 : Multiply-by-4 processing operation

001

RWRW

RW

RW

RW

RW

RW

RW

To use two-phase pulse signal processing, set this bit to “0”.



b7

Bit Symbol

Figure 1.12.8. TA4MR Registers in Event Counter Mode (when using two-phase pulse signalprocessing with timer A4)



3. One-shot Timer ModeIn one-shot timer mode, the timer is activated only once by one trigger. (See Table 1.12.4.) When thetrigger occurs, the timer starts up and continues operating for a given period. Figure 1.12.9 shows theTAiMR register in one-shot timer mode.

Table 1.12.4. Specifications in One-shot Timer Mode

Item Specification

Count source f1, f2, f8, f32

Count operation • Down-count

• When the counter reaches 000016, it stops counting after reloading a new value

• If a trigger occurs when counting, the timer reloads a new count and restarts counting

Divide ratio 1/n n : set value of TAi register 000016 to FFFF16

However, the counter does not work if the divide-by-n value is set to 000016.Count start condition TAiS bit of TABSR register = “1” (start counting) and one of the following trig-

gers occurs.• External trigger input from the TAiIN pin• timer Aj (j=i-1, except j=4 if i=0) overflow or underflow,

timer Ak (k=i+1, except k=0 if i=4) overflow or underflow

• The TAiOS bit of ONSF register is set to “1” (= timer starts)

Count stop condition • When the counter is reloaded after reaching “000016”

• TAiS bit is set to “0” (= stop counting)

Interrupt request generation timing When the counter reaches “000016”

TAiIN pin function I/O port or trigger input

TAiOUT pin function I/O port or pulse output

Read from timer An indeterminate value is read by reading TAi registerWrite to timer • When not counting and until the 1st count source is input after counting start

Value written to TAi register is written to both reload register and counter• When counting (after 1st count source input)

Value written to TAi register is written to only reload register(Transferred to counter when reloaded next)

Select function • Pulse output functionThe timer outputs a low when not counting and a high when counting.



Bit name

Timer Ai mode register (i=0 to 4)


Function Bit symbol

b7 b6 b5 b4 b3 b2 b1 b0

Operation mode select bit1 0 : One-shot timer modeb1 b0

TMOD1

TMOD0

MR0 Pulse output function select bit

0 : Pulse is not output (TAiOUT pin functions as I/O port)1 : Pulse is output (Note 1) (TAiOUT pin functions as a pulse output pin)

MR2

MR1

MR3 Must be set to “0” in one-shot timer mode

0 0 : f1 or f20 1 : f81 0 : f1 1 : Do not set

32

b7 b6

TCK1


1 00

0 : TAiOS bit is enabled1 : Selected by TAiTGH to TAiTGL bits

Trigger select bit

External trigger select bit (Note 2)

0 : Falling edge of input signal to TAiIN pin (Note 3)1 : Rising edge of input signal to TAiIN pin (Note 3)

Note 1: TA0OUT pin is N-channel open drain output.Note 2: Effective when the TAiGH and TAiGL bits of ONSF or TRGSR register are ‘00 2’ (TAi IN pin input). Note 3: The port direction bit for the TAi

There are not TA2IN and TA3IN. IN pin must be set to “0” (= input mode).

RW

RW

RW

RW

RW

RW

RW

RW

RW

Figure 1.12.9. TAiMR Register in One-shot Timer Mode



4. Pulse Width Modulation (PWM) ModeIn PWM mode, the timer outputs pulses of a given width in succession (see Table 1.12.5). The counter

functions as either 16-bit pulse width modulator or 8-bit pulse width modulator. Figure 1.12.10 shows

TAiMR register in pulse width modulation mode. Figures 1.12.11 and 1.12.12 show examples of how a

16-bit pulse width modulator operates and how an 8-bit pulse width modulator operates.

Table 1.12.5. Specifications in PWM Mode

Item SpecificationCount source f1, f2, f8, f32

Count operation • Down-count (operating as an 8-bit or a 16-bit pulse width modulator)• The timer reloads a new value at a rising edge of PWM pulse and continues counting• The timer is not affected by a trigger that occurs during counting

16-bit PWM • High level width n / fj n : set value of TAi register (i=o to 4)• Cycle time (216-1) / fj fixed fj: count source frequency (f1, f2, f8, f32)

8-bit PWM • High level width n x (m+1) / fj n : set value of TAiMR register high-order address• Cycle time (28-1) x (m+1) / fj m : set value of TAiMR register low-order address

Count start condition • TAiS bit of TABSR register is set to “1” (= start counting)• The TAiS bit = 1 and external trigger input from the TAiIN pin• The TAiS bit = 1 and one of the following external triggers occursTimer Aj (j=i-1, except j=4 if i=0) overflow or underflow,Timer Ak (k=i+1, except k=0 if i=4) overflow or underflow

Count stop condition TAiS bit is set to “0” (= stop counting)Interrupt request generation timing PWM pulse goes “L”TAiIN pin function I/O port or trigger inputTAiOUT pin function Pulse outputRead from timer An indeterminate value is read by reading TAi register

Write to timer • When not counting and until the 1st count source is input after counting startValue written to TAi register is written to both reload register and counter

• When counting (after 1st count source input)Value written to TAi register is written to only reload register(Transferred to counter when reloaded next)



Figure 1.12.10. TAiMR Register in PWM Mode

Bit name

Timer Ai mode register (i= 0 to 4)


FunctionBit symbol

b7 b6 b5 b4 b3 b2 b1 b0

Operation mode select bit 1 1 : PWM mode

b1 b0

TMOD1TMOD0

MR0

MR2

MR1

MR3

0 0 : f1 or f20 1 : f81 0 : f1 1 : Do not set

32

b7 b6

TCK1


RW

1 11

Must be set to “1” in PWM mode

16/8-bit PWM mode select bit

0: Functions as a 16-bit pulse width modulator1: Functions as an 8-bit pulse width modulator

Trigger select bit

External trigger select bit (Note 2)

0: Falling edge of input signal to TAi IN pin(Note 3)1: Rising edge of input signal to TAi IN pin(Note 3)

RW

RW

RW

RW

RW

RW

RW

RW

(Note 1)

0 : TAiOS bit is enabled1 : Selected by TAiTGH to TAiTGL bits

Note 1: TA0OUT pin is N-channel open drain output.Note 2: Effective when the TAiGH and TAiGL bits of ONSF or TRGSR register are ‘00 2’ (TAi IN pin input). Note 3: The port direction bit for the TAi

There are not TA2IN and TA3IN. IN pin must be set to “0” (= input mode).



1 / fi X (2 – 1) 16

Count source

Input signal to TAiIN pin

PWM pulse output from TAiOUT pin

Trigger is not generated by this signal

“H”

“H”

“L”

“L”

IR bit of TAiIC register

“1”

“0”

fj : Frequency of count source (f1, f2, f8, f32)i = 0 to 4

Note 1: n = 000016 to FFFE16.Note 2: This timing diagram is for the case where the TAi register is ‘000316,’ the TAiGH and TAiGL bits of ONSF

or TRGSR register = ‘002’ (TAi IN pin input), the MR1 bit of TAiMR register = 1 (rising edge), and the MR2 bit of TAiMR register = 1 (trigger selected by TAiTGH and TAiTGL bits).

1 / fj X n

Set to “0” upon accepting an interrupt request or by writing in program

Count source (Note1)

Input signal to TAiIN pin

Underflow signal of 8-bit prescaler (Note2)

PWM pulse output from TAiOUT pin

“H”

“H”

“H”

“L”

“L”

“L”

“1”

“0”

Set to “0” upon accepting an interrupt request or by writing in program

Note 1: The 8-bit prescaler counts the count source.Note 2: The 8-bit pulse width modulator counts the 8-bit prescaler's underflow signal.Note 3: m = 0016 to FF16; n = 0016 to FE16.Note 4: This timing diagram is for the case where the TAi register is ‘020216,’ the TAiGH and TAiGL bits of ONSF or

TRGSR register = ‘002’ (TAi IN pin input), the MR1 bit of TAiMR register = 0 (falling edge), and the MR2 bit of TAiMR register = 1 (trigger selected by TAiTGH and TAiTGL bits).

1 / fj X (m + 1) X (2 – 1) 8

1 / fj X (m + 1) X n

1 / fj X (m + 1)

IR bit of TAiIC register

fj : Frequency of count source (f1, f2, f8, f32)i = 0 to 4

Figure 1.12.11. Example of 16-bit Pulse Width Modulator Operation

Figure 1.12.12. Example of 8-bit Pulse Width Modulator Operation

M16C/6S Group Serial I/O


Serial I/OSerial I/O is configured with five channels: UART0 to UART2, SI/O3 and SI/O4.

UARTi (i=0 to 2)UARTi each have an exclusive timer to generate a transfer clock, so they operate independently of each

other.

Figure 1.13.1 shows the block diagram of UARTi. Figure 1.13.2 shows the block diagram of the UARTi

transmit/receive unit.

UARTi has the following modes:

• Clock synchronous serial I/O mode

• Clock asynchronous serial I/O mode (UART mode).

• Special mode 1 (I2C mode)

• Special mode 2

Figures 1.13.3 to 1.13.8 show the UARTi-related registers.

Refer to tables listing each mode for register setting.



Figure 1.13.1. UARTi Block Diagram

RXD0

1 / (n0+1)

1/16

1/16

1/2

U0BRG register

Clock synchronous type(when internal clock is selected)

Clock synchronous type


Clock synchronous type(when external clock is selected)

CLK0

Clock source selection

CTS0 / RTS0

f1SIO or f2SIO

f8SIO

f32SIO

Internal

External

RTS0

CTS0

TXD0

Transmit/receive

unit

(UART0)

CLK1 to CLK0

00h

01h

10h

CKDIR

CKPOL

UART reception

UART transmission


CKDIR

1

0

RXD polarity reversing circuit

0

1RCSP

1

VSS

0

1

SMD2 toSMD0010, 100, 101, 110

001

010, 100, 101, 110

001

0

1

CRS0

CRD

PCLK1

f1SIO or f2SIO1/2

Main clock or on-chip oscillator clock

1/2

1/8 f8SIO

f32SIO

f1SIO

f2SIO 0

1

1/4

Receive clock

Transmit clock

Reception control circuit

Transmission control circuit

TXD polarity

reversing circuit

CTS/RTS disabled

CTS/RTS disabled

CTS/RTS selected

CTS0 from UART1

CLK polarity

reversing circuit

n0: Values set to the U0BRG register PCLK1: Bit in the PCLKR registerSMD2 to SMD0, CKDIR: Bits in U0MR register CLK1 to CLK0, CKPOL, CRD, CRS: Bits in U0C0 registerCLKMD0, CLKMD1, RCSP: Bits in UCON register

RXD1



1 / (n1+1)

1/16

1/16

1/2

U1BRGregister

Clock synchronous type (when internal clock is selected)



Clock synchronous type (when external clock is selected))

CLK1


f1SIO or f2SIO

f8SIO

f32SIO

Internal

External

TXD1(UART1)

CLK1 to CLK0

00

01

10

CKDIR

UART reception

UART transmission


CKDIR


0

1

SMD2 to SMD0010, 100, 101, 110

001

010, 100, 101, 110

001

0

1

RTS1

CTS1

Clock output pin select CTS1 / RTS1/

CTS0 / CLKS1VSS

CRD

1

0

0

CRS

00

1

CLKMD0

1

CLK polarity

reversing circuit

CKPOL

1

CLKMD1

1

0

RCSP

n1: Values set to the U1BRG registerPCLK1: Bit in the PCLKR registerSMD2 to SMD0, CKDIR: Bits in U1MR register CLK1 to CLK0, CKPOL, CRD, CRS: Bits in U1C0 registerCLKMD0, CLKMD1, RCSP: Bits in UCON register

PCLK1

f1SIO or f2SIO1/2


1/2

1/8 f8SIO

f32SIO

f1SIO

f2SIO 0

1

1/4

Receive clock

Transmit clock

Transmit/receive

unit

TXD polarity

reversing circuit

CTS0 from UART0

CTS/RTS disabled

CTS/RTS disabled

CTS/RTS selected

RXD2

1 / (n2+1)

1/16

1/16

1/2

U2BRG register




f1SIO or f2SIO

f8SIO

f32SIO

Internal

External

RTS2

CTS2

TXD2(UART2)

CLK1 to CLK0

00

01

10

CKDIR

UART reception

UART transmission


CKDIR

1

0


0

1

VSS

0

SMD2 to SMD0010, 100, 101, 110

001

010, 100, 101, 110

001

0

CRS

CRD

CTS2 / RTS2

NOTES : 1. UART2 is the N-channel open-drain output. Cannot be set to the CMOS output2. UART2 does not have CLK2 port. So CKDIR must not be set "1."

.

n2: Values set to the U2BRG registerPCLK1: Bit in the PCLKR registerSMD2 to SMD0, CKDIR: Bits in U2MR register CLK1 to CLK0, CKPOL, CRD, CRS: Bits in U2C0 registerCLKMD0, CLKMD1, RCSP: Bits in UCON register

CTS/RTS disabled

CTS/RTS disabledCTS/RTS selected



Receive clock

Transmit clock

TXD polarity

reversing circuit (1)Transmit/

receive unit

PCLK1

f1SIO or f2SIO1/2


1/2

1/8 f8SIO

f32SIO

f1SIO

f2SIO 0

1

1/4



SP SP PAR

2SP

1SP

UART

TXDi

D8 D7 D6 D5 D4 D3 D2 D1 D0

2SP

1SP

UART

RXDi

D7 D6 D5 D4 D3 D2 D1 D0D80 0 0 0 0 0 0

SP SP PAR

SMD2 to SMD0

0

1

IOPOL

STPS

IOPOL

UiERE

PRYE

0

11

0

1

0

1

0

1

0

1

0

SMD2 to SMD0

0

1

0

1

0

1

0

1

0

1

0

1

STPS PRYE

Reverse

No reverse

RXD datareverse circuit


PAR enabled

PAR disabled

UART(7 bits)UART(8 bits)


UART(7 bits)

UART(9 bits)



UARTi receive register

UiTB register

UiRB register

Data bus low-order bits

Data bus high-order bits

Logic reverse circuit + MSB/LSB conversion circuit

Logic reverse circuit + MSB/LSB conversion circuit

UART(7 bits)UARTi transmit register






PAR disabled

PAR enabled

Error signal output circuit

Error signal output enable

Error signal output disable

Reverse

No reverse

TXD datareverse circuit

i=0 to 2SP: Stop bitPAR: Parity bitSMD2 to SMD0, STPS, PRYE, IOPOL, CKDIR: Bits in UiMR register UiERE: Bit in UiC1 register

UART(9 bits)

Figure 1.13.2. UARTi Transmit/Receive Unit



Figure 1.13.3. U0TB to U2TB Register, U0RB to U2RB Register, and U0BRG to U2BRG Register

b7

(b15)

(b15) Symbol Address After reset U0RB 03A716-03A616 Indeterminate U1RB 03AF16-03AE16 Indeterminate U2RB 037F16-037E16 Indeterminate

b7 b0(b8)

b7 b0

UARTi receive buffer register (i=0 to 2)

FunctionBit nameBit symbol

0 : No framing error1 : Framing error found

0 : No parity error1 : Parity error found

0 : No error1 : Error found

Note 1: When the UiMR register’s SMD2 to SMD0 bits = “0002” (serial I/O disabled) or the UiC1 register’s RE bit = “0” (reception disabled), all of the SUM, PER, FER and OER bits are set to “0” (no error). The SUM bit is set to “0” (no error) when all of the PER, FER and OER bits = “0” (no error). Also, the PER and FER bits are set to “0” by reading the lower byte of the UiRB register.Note 2: The ABT bit is set to “0” by writing “0” in a program. (Writing “1” has no effect.)

OER

FER

PER

SUM

Overrun error flag (Note 1)

Framing error flag (Note 1)

Parity error flag (Note 1)

Error sum flag (Note 1)

0 : No overrun error1 : Overrun error found

Nothing is assigned.In an attempt to write to these bits, write “0”. The value, if read, turns out to be “0”.

Receive data (D7 to D0)

ABT Arbitration lost detecting flag (Note 2)

0 : Not detected1 : Detected

UARTi bit rate generator (i=0 to 2)(Notes 1, 2)b0 Symbol Address After reset

U0BRG 03A116 Indeterminate U1BRG 03A916 Indeterminate U2BRG 037916 Indeterminate

Function

Assuming that set value = n, UiBRG divides the count source by n + 1

0016 to FF16

Setting range

Note 1: Write to this register while serial I/O is neither transmitting nor receiving. Note 2: Use MOV instruction to write to this register.

b7 b0(b8)

b7 b0

UARTi transmit buffer register (i=0 to 2)(Note)

Function

Transmit data

Nothing is assigned.In an attempt to write to these bits, write “0”. The value, if read, turns out to be indeterminate.

Symbol Address After reset U0TB 03A316-03A216 Indeterminate U1TB 03AB16-03AA16 Indeterminate U2TB 037B16-037A16 Indeterminate

RW

Note: Use MOV instruction to write to this register.

WO

RW

RW

RO

RO

RO

RO

RO

(b7-b0)

(b10-b9)

RW

WO

Receive data (D8) RO(b8)



UARTi transmit/receive mode register (i=0 to 2)

Symbol Address After reset U0MR to U2MR 03A016, 03A816, 037816 0016

b7 b6 b5 b4 b3 b2 b1 b0

Bit nameBit

symbol RW

CKDIR

SMD1

SMD0 Serial I/O mode select bit (Note 2)

SMD2

Internal/external clock select bit

STPS

PRY

PRYE

IOPOL

Parity enable bit

0 : Internal clock1 : External clock (Note 1) (Note 4)

Stop bit length select bit

Odd/even parity select bit

TxD, RxD I/O polarity reverse bit

0 : One stop bit1 : Two stop bits

0 : Parity disabled1 : Parity enabled

0 0 0 : Serial I/O disabled0 0 1 : Clock synchronous serial I/O mode0 1 0 : I2C mode1 0 0 : UART mode transfer data 7 bits long1 0 1 : UART mode transfer data 8 bits long 1 1 0 : UART mode transfer data 9 bits longMust not be set except above

b2 b1 b0

Effective when PRYE = 10 : Odd parity1 : Even parity

0 : No reverse1 : Reverse

Function

Note 1: Set the corresponding port direction bit for each CLKi pin to “0” (input mode).Note 2: To receive data, set the corresponding port direction bit for each RxDi pin to “0” (input mode). Note 3: Set the corresponding port direction bit for SCL and SDA pins to “0” (input mode).Note 4: Set “0” to select internal clock of UART2.

UARTi transmit/receive control register 0 (i=0 to 2)

Symbol Address After reset U0C0 to U2C0 03A416, 03AC16, 037C16 000010002

b7 b6 b5 b4 b3 b2 b1 b0

Function

TXEPT

CLK1

CLK0

CRS

CRD

NCH

CKPOL

BRG count source select bit

Transmit register empty flag

0 : Transmit data is output at falling edge of transfer clock and receive data is input at rising edge 1 : Transmit data is output at rising edge of transfer clock and receive data is input at falling edge

CLK polarity select bit

CTS/RTS function select bit

CTS/RTS disable bit

Data output select bit(Note 2)

0 0 : f1SIO or f2SIO is selected0 1 : f8SIO is selected1 0 : f32SIO is selected1 1 : Must not be set

b1 b0

0 : LSB first1 : MSB first

0 : Data present in transmit register (during transmission)1 : No data present in transmit register (transmission completed)

0 : CTS/RTS function enabled1 : CTS/RTS function disabled (P60, P64 and P73 can be used as I/O ports)

0 : TxDi/SDAi and SCLi pins are CMOS output1 : TxDi/SDAi and SCLi pins are N-channel open-drain output

UFORM Transfer format select bit(Note 3)

Effective when CRD = 00 : CTS function is selected (Note 1)1 : RTS function is selected

Bit nameBit symbol

Note 1: Set the corresponding port direction bit for each CTSi pin to “0” (input mode).Note 2: TXD2/SDA2 are N-channel open-drain output. Cannot be set to the CMOS output. NCH bit of U2C0 register is effective in an output set up of SCL2 pin.Note 3: Effective for clock synchronous serial I/O mode and UART mode transfer data 8 bits long. Note 4: CTS1/RTS1 can be used when the UCON register’s CLKMD1 bit = “0” (only CLK1 output) and the UCON register’s RCSP bit = “0” (CTS0/RTS0 not separated).

RW

RW

RW

RW

RW

RW

RW

RW

RW

RW

RW

RW

RW

RW

RW

RW

RO

(Note 3)

(Note 4)

Figure 1.13.4. U0MR to U2MR Register and U0C0 to U2C0 Register



UARTi transmit/receive control register 1 (i=0, 1)

Symbol Address After resetU0C1, U1C1 03A516,03AD16 000000102

b7 b6 b5 b4 b3 b2 b1 b0

Bit nameBit symbol RWFunction

TE

TI

RE

RI

Transmit enable bit

Receive enable bit

Receive complete flag

Transmit buffer empty flag

0 : Transmission disabled1 : Transmission enabled

0 : Data present in UiTB register 1 : No data present in UiTB register

0 : Reception disabled1 : Reception enabled

0 : No data present in UiRB register 1 : Data present in UiRB register

Nothing is assigned.When write, set “0”. When read, these contents are “0”.

UART2 transmit/receive control register 1

Symbol Address After resetU2C1 037D16 000000102

b7 b6 b5 b4 b3 b2 b1 b0

Bit nameBit symbol

Function

TE

TI

RE

RI

Transmit enable bit

Receive enable bit

Receive complete flag

Transmit buffer empty flag

0 : Transmission disabled1 : Transmission enabled

0 : Reception disabled1 : Reception enabled

U2IRS UART2 transmit interrupt cause select bit

0 : Transmit buffer empty (TI = 1)1 : Transmit is completed (TXEPT = 1)

U2RRM UART2 continuous receive mode enable bit

0 : Continuous receive mode disabled1 : Continuous receive mode enabled

Data logic select bit 0 : No reverse1 : Reverse

U2LCH

U2ERE Error signal output enable bit

0 : Output disabled1 : Output enabled

Data logic select bit 0 : No reverse1 : Reverse

UiLCH

UiERE Error signal output enable bit

0 : Output disabled1 : Output enabled

RW

RW

RW

RW

RO

RO

RW

RW

RW

RW

RW

RW

RW

RO

RO

(b5-b4)

0 : Data present in U2TB register 1 : No data present in U2TB register

0 : No data present in U2RB register 1 : Data present in U2RB register

NOTES:1. The UiLCH bit is enabled when the SMD2 to SMD0 bits in the UiMR register are set to “001b” (clock synchronous serial I/O

mode), “100b” (UART mode, 7-bit transfer data), or “101b” (UART mode, 8-bit transfer data).Set this bit to “0” when the SMD2 to SMD0 bits are set to “010b” (I2C mode) or “110b” (UART mode, 9-bit transfer data).

NOTES:1. The U2LCH bit is enabled when the SMD2 to SMD0 bits in the U2MR registerare set to “001b” (clock synchronous serial I/O

mode), “100b” (UART mode, 7-bit transfer data), or “101b” (UART mode, 8-bit transfer data).Set this bit to “0” when the SMD2 to SMD0 bits are set to “010b” (I2C mode) or “110b” (UART mode, 9-bit transfer data).

Figure 1.13.5. U0C1 to U2C1 Registers



Figure 1.13.6. UCON Register and U0SMR to U2SMR Registers

Note: When using multiple transfer clock output pins, make sure the following conditions are met: U1MR register’s CKDIR bit = “0” (internal clock)

UART transmit/receive control register 2

Symbol Address After reset UCON 03B016 X00000002

b7 b6 b5 b4 b3 b2 b1 b0

Bit name

Bit symbol RWFunction

CLKMD0

CLKMD1

UART0 transmit interrupt cause select bit

UART0 continuous receive mode enable bit

0 : Continuous receive mode disabled1 : Continuous receive mode enable

UART1 continuous receive mode enable bit

UART1 CLK/CLKS select bit 0

UART1 transmit interrupt cause select bit

0 : Transmit buffer empty (Tl = 1) 1 : Transmission completed (TXEPT = 1)

0 : Transmit buffer empty (Tl = 1)1 : Transmission completed (TXEPT = 1)

0 : CLK output is only CLK11 : Transfer clock output from multiple pins function selected

0 : Continuous receive mode disabled1 : Continuous receive mode enabled

Nothing is assigned. When write, set “0”. When read, its content is indeterminate.

U0IRS

U1IRS

U0RRM

U1RRM

UART1 CLK/CLKS select bit 1 (Note)

Effective when CLKMD1 = “1” 0 : Clock output from CLK11 : Clock output from CLKS1

UART2 special mode register (i=0 to 2)

Symbol Address After reset U0SMR to U2SMR 036F16, 037316, 037716 X00000002

b7 b6 b5 b4 b3 b2 b1 b0

Bit name

Bit symbol

Function

I2C mode select bit

Bus busy flag 0 : STOP condition detected1 : START condition detected (busy)

Arbitration lost detecting flag control bit

0 : Other than I2C mode1 : I2C mode

0 : Update per bit1 : Update per byte

IICM

ABC

BBS

Set to “0”

Note 1: The BBS bit is set to “0” by writing “0” in a program. (Writing “1” has no effect.).

(Note1)

RCSP Separate UART0 CTS/RTS bit

0 : CTS/RTS shared pin1 : CTS/RTS separated (CTS0 supplied from the P64 pin)


RW

RW

RW

RW

RW

RW

RW

(b7)

RW

RW

RW

RW

RW

(b7)

0000

(b3-b6) Reserved bit



UARTi special mode register 2 (i=0 to 2)

Symbol Address After reset U0SMR2 to U2SMR2 036E16, 037216, 037616 X00000002

b7 b6 b5 b4 b3 b2 b1 b0


STAC

SWC2

SDHI

I C mode select bit 2

SCL wait output bit 0 : Disabled1 : Enabled

SDA output stop bit

UARTi initialization bit

Clock-synchronous bit

Refer to Table 1.16.4


IICM2

CSC

SWC

ALS 0 : Disabled1 : Enabled

SDA output disable bit

SCL wait output bit 2

0: Enabled1: Disabled (high impedance)


0: Transfer clock1: 0 output

2


Symbol Address After reset U0SMR3 to U2SMR3 036D16, 037116, 037516 000X0X0X2

b7 b6 b5 b4 b3 b2 b1 b0

Bit nameBit

symbol Function

DL2

SDAi digital delay setup bit(Note 1, Note 2)

DL0

DL1

0 0 0 : Without delay0 0 1 : 1 to 2 cycle(s) of UiBRG count source0 1 0 : 2 to 3 cycles of UiBRG count source0 1 1 : 3 to 4 cycles of UiBRG count source1 0 0 : 4 to 5 cycles of UiBRG count source1 0 1 : 5 to 6 cycles of UiBRG count source1 1 0 : 6 to 7 cycles of UiBRG count source1 1 1 : 7 to 8 cycles of UiBRG count source

Nothing is assigned.When write, set “0”. When read, its content is indeterminate.

b7 b6 b5


0 : Without clock delay1 : With clock delay

Clock phase set bit

0 : CLKi is CMOS output1 : CLKi is N-channel open drain output

Clock output select bit

CKPH

NODC

Note 1 : The DL2 to DL0 bits are used to generate a delay in SDAi output by digital means during I2C mode. In other than I2C mode, set these bits to “0002” (no delay).Note 2 : The amount of delay varies with the load on SCLi and SDAi pins. Also, when using an external clock, the amount of delay increases by about 100 ns.

RW

RW

RW

RW

RW

RW

RW

(b7)

RW

RW

RW

RW

RW

RW

(b0)



(b2)

(b4)

Figure 1.13.7. U0SMR2 to U2SMR2 Registers and U0SMR3 to U2SMR3 Registers



Figure 1.13.8. U0SMR4 to U2SMR4 Registers


Symbol Address After reset U0SMR4 to U2SMR4 036C16, 037016, 037416 0016

b7 b6 b5 b4 b3 b2 b1 b0


ACKC

SCLHI

SWC9

Start conditiongenerate bit (Note)

Stop conditiongenerate bit (Note)

0 : Clear1 : Start

SCL,SDA outputselect bit

ACK data bit

Restart conditiongenerate bit (Note)

0 : Clear1 : Start

0 : Clear1 : Start

STAREQ

RSTAREQ

STPREQ

ACKD

0 : Start and stop conditions not output1 : Start and stop conditions output

SCL output stopenable bit

ACK data outputenable bit


0 : ACK1 : NACK

0 : Serial I/O data output1 : ACK data output

Note: Set to “0” when each condition is generated.

STSPSEL

0 : SCL “L” hold disabled1 : SCL “L” hold enabled

SCL wait bit 3

RW

RW

RW

RW

RW

RW

RW

RW

M16C/6S Group Clock Synchronous serial I/O Mode


Clock Synchronous serial I/O ModeThe clock synchronous serial I/O mode uses a transfer clock to transmit and receive data. Table 1.14.1lists the specifications of the clock synchronous serial I/O mode. Table 1.14.2 lists the registers used in

clock synchronous serial I/O mode and the register values set. UART2 is not available in this mode.

Item Specification

Transfer data format • Transfer data length: 8 bits

Transfer clock • UiMR(i=0 to 1) register’s CKDIR bit = “0” (internal clock) : fj/ 2(n+1)

fj = f1SIO, f2SIO, f8SIO, f32SIO. n: Setting value of UiBRG register 0016 to FF16

• CKDIR bit = “1” (external clock) : Input from CLKi pin

Transmission, reception control_______ _______ _______ _______

• Selectable from CTS function, RTS function or CTS/RTS function disable

Transmission start condition • Before transmission can start, the following requirements must be met (Note 1)_ The TE bit of UiC1 register= 1 (transmission enabled)_ The TI bit of UiC1 register = 0 (data present in UiTB register)

_______ ________ If CTS function is selected, input on the CTSi pin = “L”

Reception start condition • Before reception can start, the following requirements must be met (Note 1)_ The RE bit of UiC1 register= 1 (reception enabled)_ The TE bit of UiC1 register= 1 (transmission enabled)_ The TI bit of UiC1 register= 0 (data present in the UiTB register)

• For transmission, one of the following conditions can be selected_ The UiIRS bit (Note 3) = 0 (transmit buffer empty): when transferring data from the

UiTB register to the UARTi transmit register (at start of transmission)_ The UiIRS bit =1 (transfer completed): when the serial I/O finished sending data from

the UARTi transmit register

• For reception

When transferring data from the UARTi receive register to the UiRB register (at

completion of reception)

Error detection • Overrun error (Note 2)

This error occurs if the serial I/O started receiving the next data before reading the

UiRB register and received the 7th bit of the next data

Select function • CLK polarity selection

Transfer data input/output can be chosen to occur synchronously with the rising or

the falling edge of the transfer clock

• LSB first, MSB first selection

Whether to start sending/receiving data beginning with bit 0 or beginning with bit 7

can be selected

• Continuous receive mode selection

Reception is enabled immediately by reading the UiRB register

• Switching serial data logic

This function reverses the logic value of the transmit/receive data

• Transfer clock output from multiple pins selection (UART1)

The output pin can be selected in a program from two UART1 transfer clock pins that

have been set_______ _______

• Separate CTS/RTS pins (UART0)_________ _________

CTS0 and RTS0 are input/output from separate pinsNote 1: When an external clock is selected, the conditions must be met while if the UiC0 register’s CKPOL bit = “0”

(transmit data output at the falling edge and the receive data taken in at the rising edge of the transfer clock), theexternal clock is in the high state; if the UiC0 register’s CKPOL bit = “1” (transmit data output at the rising edgeand the receive data taken in at the falling edge of the transfer clock), the external clock is in the low state.

Note 2: If an overrun error occurs, the value of UiRB register will be indeterminate. The IR bit of SiRIC register does not change.Note 3: The U0IRS and U1IRS bits respectively are the UCON register bits 0 and 1.

Table 1.14.1. Clock Synchronous Serial I/O Mode Specifications

Interrupt request

generation timing



Table 1.14.2. Registers to Be Used and Settings in Clock Synchronous Serial I/O ModeRegister Bit Function

UiTB(Note3) 0 to 7 Set transmission data

UiRB(Note3) 0 to 7 Reception data can be read

OER Overrun error flag

UiBRG 0 to 7 Set a transfer rate

UiMR(Note3) SMD2 to SMD0 Set to “0012”

CKDIR Select the internal clock or external clock

IOPOL Set to “0”

UiC0 CLK1 to CLK0 Select the count source for the UiBRG register

CRS_______ _______

Select CTS or RTS to use

TXEPT Transmit register empty flag

CRD_______ _______

Enable or disable the CTS or RTS function

NCH Select TxDi pin output mode

CKPOL Select the transfer clock polarity

UFORM Select the LSB first or MSB first

UiC1 TE Set this bit to “1” to enable transmission/reception

TI Transmit buffer empty flag

RE Set this bit to “1” to enable reception

RI Reception complete flag

U2IRS (Note 1) Select the source of UART2 transmit interrupt

U2RRM (Note 1) Set this bit to “1” to use continuous receive mode

UiLCH Set this bit to “1” to use inverted data logic

UiERE Set to “0”

UiSMR 0 to 7 Set to “0”

UiSMR2 0 to 7 Set to “0”


NODC Select clock output mode

4 to 7 Set to “0”


UCON U0IRS, U1IRS Select the source of UART0/UART1 transmit interrupt

U0RRM, U1RRM Set this bit to “1” to use continuous receive mode

CLKMD0 Select the transfer clock output pin when CLKMD1 = 1

CLKMD1 Set this bit to “1” to output UART1 transfer clock from two pins

RCSP_________

Set this bit to “1” to accept as input the UART0 CTS0 signal from the P64 pin

7 Set to “0”

Note 1: Set the U0C1 and U1C1 register bit 4 and bit 5 to “0”. The U0IRS, U1IRS, U0RRM and U1RRM bits

are in the UCON register.

Note 2: Not all register bits are described above. Set those bits to “0” when writing to the registers in clock

synchronous serial I/O mode.

i=0 to 1



Table 1.14.3 lists the functions of the input/output pins during clock synchronous serial I/O mode. Table

1.14.3 shows pin functions for the case where the multiple transfer clock output pin select function is

deselected. Table 1.14.4 lists the P64 pin functions during clock synchronous serial I/O mode. Note that

for a period from when the UARTi operation mode is selected to when transfer starts, the TxDi pin outputs

an “H”. (If the N-channel open-drain output is selected, this pin is in a high-impedance state.)

Table 1.14.3. Pin Functions (When Not Select Multiple Transfer Clock Output Pin Function)Pin name Function Method of selection

TxDi (i = 0 to 2)(P63, P67)

Serial data output

Serial data input

Transfer clock output

Transfer clock input

I/O port

(Outputs dummy data when performing reception only)

RxDi(P62, P66)

CLKi(P61, P65)

UiMR register’s CKDIR bit=0

UiMR register’s CKDIR bit=1PD6 register’s PD6_1 bit=0, PD6_5 bit=0

PD6 register’s PD6_2 bit=0, PD6_6 bit=0(Can be used as an input port when performing transmission only)

UiC0 register’s CRD bit=0UiC0 register’s CRS bit=0PD6 register’s PD6_0 bit=0, PD6_4 bit=0

UiC0 register’s CRD bit=0UiC0 register’s CRS bit=1

UiC0 register’s CRD bit=1

CTS input

RTS output

CTSi/RTSi(P60, P64)

Table 1.14.4. P64 Pin Functions

Pin function Bit set value

U1C0 register UCON register PD6 register CRD CRS RCSP CLKMD1 CLKMD0 PD6_4

P64 1 0 0 Input: 0, Output: 1

CTS1 0 0 0 0

RTS1 1 0 0

CTS0(Note1) 0CLKS1

000 0

1(Note 2) 1

Note 1: In addition to this, set the U0C0 register’s CRD bit to “0” (CTS0/RTS0 enabled) and the U0 C0 register’s CRS bit to “1” (RTS0 selected).Note 2: When the CLKMD1 bit = 1 and the CLKMD0 bit = 0, the following logic levels are output: • High if the U1C0 register’s CLKPOL bit = 0 • Low if the U1C0 register’s CLKPOL bit = 1

1 0



Figure 1.14.1. Transmit and Receive Operation

(1) Example of transmit timing (when internal clock is selected)

D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7

Tc

TCLK

Stopped pulsing because the TE bit = “0”

Write data to the UiTB register

Tc = TCLK = 2(n + 1) / fj fj: frequency of UiBRG count source (f1SIO, f2SIO, f8SIO, f32SIO) n: value set to UiBRG register i: 0 to 2

Transfer clock

UiC1 registerTE bit

UiC1 registerTI bit

CLKi

TxDi

“H”

“L”

“0”

“1”

“0”

“1”

“0”

“1”

CTSi

“0”

“1”

Stopped pulsing because CTSi = “H”

Transferred from UiTB register to UARTi transmit register

The above timing diagram applies to the case where the register bits are set as follows: • UiMR register CKDIR bit = 0 (internal clock) • UiC0 register CRD bit = 0 (CTS/RTS enabled), CRS bit = 0 (CTS selected) • UiC0 register CKPOL bit = 0 (transmit data output at the falling edge and receive data taken in at the rising edge of the transfer clock) • UiRS bit = 0 (an interrupt request occurs when the transmit buffer becomes empty): U0IRS bit is the UCON register bit 0, U1IRS bit is the UCON register bit 1, and U2IRS bit is the U2C1 register bit 4

Cleared to “0” when interrupt request is accepted, or cleared to “0” in a program

UiC0 registerTXEPT bit

SiTIC registerIR bit

1 / fEXT

Write dummy data to UiTB registerUiC1 registerTE bit

UiC1 registerTI bit

CLKi

RxDi

UiC1 registerRI bit

RTSi“H”

“L”

“0”

“1”

“0”

“1”

“0”

“1”

UiC1 registerRE bit “0”

“1”

Receive data is taken in


Read out from UiRB register

fEXT: frequency of external clock

Transferred from UARTi receive registerto UiRB register

SiTIC registerIR bit “0”

“1”

D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5

Make sure the following conditions are met when input to the CLKi pin before receiving data is high: • UiC0 register TE bit = 1 (transmit enabled) • UiC0 register RE bit = 1 (Receive enabled) • Write dummy data to the UiTB register


The above timing diagram applies to the case where the register bits are set as follows: • UiMR register CKDIR bit = 1 (external clock) • UiC0 register CRD bit = 0 (CTS/RTS enabled), CRS bit = 1 (RTS selected) • UiC0 register CKPOL bit = 0 (transmit data output at the falling edge and receive data taken in at the rising edge of the transfer clock)

Even if the reception is completed, the RTS does not change. The RTS becomes “L” when the RI bit changes to “0” from “1”.

(2) Example of receive timing (when external clock is selected)



(2) When the UiC0 register’s CKPOL bit = 1 (transmit data output at the rising edge and the receive data taken in at the falling edge of the transfer clock)

D1 D2 D3 D4 D5 D6 D7

D1 D2 D3 D4 D5 D6 D7

D0

D0

TXDi

RXDi

CLKi

(1) When the UiC0 register’s CKPOL bit = 0 (transmit data output at the falling edge and the receive data taken in at the rising edge of the transfer clock)

D1 D2 D3 D4 D5 D6 D7D0

D1 D2 D3 D4 D5 D6 D7D0

TXDi

RXDi

CLKi

Note 1: This applies to the case where the UiC0 register’s UFORM bit = 0 (LSB first) and UiC1 register's UiLCH bit = 0 (no reverse).

Note 2: When not transferring, the CLKi pin outputs a high signal.Note 3: When not transferring, the CLKi pin outputs a low signal.i = 0 to 1

(Note 2)

(Note 3)

Figure 1.14.2. Transfer Clock Polarity

Counter Measure for Communication Error Occurs

If a communication error occurs while transmitting or receiving in clock synchronous serial I/O mode,

follow the procedures below.

• Resetting the UiRB register (i=0 to 2)

(1) Set the RE bit in the UiC1 register to “0” (reception disabled)

(2) Set the SMD2 to SMD0 bits in the UiMR register to “000b” (Serial I/O disabled)

(3) Set the SMD2 to SMD0 bits in the UiMR register to “001b” (Clock synchronous serial I/O mode)

(4) Set the RE bit in the UiC1 register to “1” (reception enabled)

• Resetting the UiTB register (i=0 to 2)

(1) Set the SMD2 to SMD0 bits in the UiMR register “000b” (Serial I/O disabled)

(2) Set the SMD2 to SMD0 bits in the UiMR register “001b” (Clock synchronous serial I/O mode)

(3) “1” is written to RE bit in the UiC1 register (reception enabled), regardless of the TE bit in the UiCi

register

(a) CLK Polarity Select Function

Use the UiC0 register (i = 0 to 1)’s CKPOL bit to select the transfer clock polarity. Figure 1.14.2 shows

the polarity of the transfer clock.



(c) Continuous Receive Mode

In continuous receive mode, receive operation becomes enable when the receive buffer register is

read. It is not necessary to write dummy data into the transmit buffer register to enable receive

operation in this mode. However, a dummy read of the receive buffer register is required when start-

ing the operation mode.

When the UiRRM bit (i = 0 to 1) = 1 (continuous receive mode), the UiC1 register’s TI bit is set to “1”

(data present in the UiTB register) by reading the UiRB register. In this case, i.e., UiRRM bit = 1, do not

write dummy data to the UiTB register in a program. The U0RRM and U1RRM bits are the UCON

register bit 2 and bit 3, respectively.

(d) Serial Data Logic Switching Function

When the UiC1 register (i = 0 to 1)’s UiLCH bit = 1 (reverse), the data written to the UiTB register has

its logic reversed before being transmitted. Similarly, the received data has its logic reversed when

read from the UiRB register. Figure 1.14.4 shows serial data logic.

(b) LSB First/MSB First Select Function

Use the UiC0 register (i = 0 to 1)’s UFORM bit to select the transfer format. Figure 1.14.3 shows the

transfer format.

Figure 1.14.3. Transfer Format

(1) When UiC0 register's UFORM bit = 0 (LSB first)

D0

D0

D1 D2 D3 D4 D5 D6 D7

D1 D2 D3 D4 D5 D6 D7

TXDi

RXDi

CLKi

(2) When UiC0 register's UFORM bit = 1 (MSB first)

D6 D5 D4 D3 D2 D1 D0D7

D7 D6 D5 D4 D3 D2 D1 D0

TXDi

RXDi

CLKi

Note: This applies to the case where the UiC0 register’s CKPOL bit = 0 (transmit data output at the falling edge and the receive data taken in at the rising edge of the transfer clock) and the UiC1 register’s UiLCH bit = 0 (no reverse).

i = 0 to 1



(e) Transfer Clock Output From Multiple Pins (UART1)

Use the UCON register’s CLKMD1 to CLKMD0 bits to select one of the two transfer clock output pins.

(See Figure 1.14.5.) This function can be used when the selected transfer clock for UART1 is an

internal clock.

Figure 1.14.5. Transfer Clock Output From Multiple Pins

Microcomputer

TXD1 (P67)

CLKS1 (P64)

CLK1 (P65) IN

CLK

IN

CLK

Note: This applies to the case where the U1MRregister's CKDIR bit = 0 (internal clock) and the UCON register's CLKMD1 bit = 1 (transfer clock output from multiple pins).

Transfer enabled when the UCON register's CLKMD0 bit = 0

Transfer enabled when the UCON register's CLKMD0 bit = 1

Figure 1.14.4. Serial Data Logic Switching

D0 D1 D2 D3 D4 D5 D6 D7

Transfer clock

TxDi(no reverse)

“H”

“L”

“H”

“L”

TxDi(reverse) D0 D1 D2 D3 D4 D5 D6 D7

“H”

“L”

(1) When the UiC1 register's UiLCH bit = 0 (no reverse)

Transfer clock“H”

“L”

(2) When the UiC1 register's UiLCH bit = 1 (reverse)

Note: This applies to the case where the UiC0 register’s CKPOL bit = 0 (transmit data output at the falling edge and the receive data taken in at the rising edge of the transfer clock) and the UFORM bit = 0 (LSB first).

i = 0 to 1



_______ _______

Figure 1.14.6. CTS/RTS Separate Function

MicrocomputerTXD0 (P63)

RXD0 (P62)INOUT

CTS

RTSCTS0 (P64)

RTS0 (P60)

IC

CLK0 (P61) CLK

_______ _______

(f) CTS/RTS Function_______ ________

When the CTS function is used transmit and receive operation start when “L” is applied to the CTSi/________ ________ ________

RTSi (i=0 to 2) pin. Transmit and receive operation begins when the CTSi/RTSi pin is held “L”. If the

“L” signal is switched to “H” during a transmit or receive operation, the operation stops before the next

data._______ ________ ________

When the RTS function is used, the CTSi/RTSi pin outputs on “L” signal when the microcomputer is

ready to receive. The output level becomes “H” on the first falling edge of the CLKi pin._______ _______

• CRD bit in UiC0 register = 1 ( CTS/RTS function disabled)________ ________

CTSi/RTSi pin is programmable I/O function_______

• CRD bit = 0, CRS bit = 0 (CTS function is selected)________ ________ _______

CTSi/RTSi pin is CTS function_______

• CRD bit = 0, CRS bit = 1 (RTS function is selected)________ ________ _______

CTSi/RTSi pin is RTS function

_______ _______

(g) CTS/RTS Separate Function (UART0)_______ _______ _______ _______

This function separates CTS0/RTS0, outputs RTS0 from the P60 pin, and accepts as input the CTS0

from the P64 pin. To use this function, set the register bits as shown below._______ _______

• U0C0 register's CRD bit = 0 (enables UART0 CTS/RTS)_______

• U0C0 register's CRS bit = 1 (outputs UART0 RTS)_______ _______


• U1C0 register's CRS bit = 0 (inputs UART1 CTS)_______

• UCON register's RCSP bit = 1 (inputs CTS0 from the P64 pin)

• UCON register's CLKMD1 bit = 0 (CLKS1 not used)_______ _______ _______ _______

Note that when using the CTS/RTS separate function, UART1 CTS/RTS separate function cannot be

used.

M16C/6S Group UART Mode


Item SpecificationTransfer data format • Character bit (transfer data): Selectable from 7, 8 or 9 bits

• Start bit: 1 bit

• Parity bit: Selectable from odd, even, or none• Stop bit: Selectable from 1 or 2 bits

Transfer clock • UiMR(i=0 to 2) register’s CKDIR bit = 0 (internal clock) : fj/ 16(n+1)


• CKDIR bit = “1” (external clock) : fEXT/16(n+1) (Note 3)

fEXT: Input from CLKi pin. n :Setting value of UiBRG register 0016 to FF16

Transmission, reception control_______ _______ _______ _______

• Selectable from CTS function, RTS function or CTS/RTS function disableTransmission start condition • Before transmission can start, the following requirements must be met

_ The TE bit of UiC1 register= 1 (transmission enabled)_ The TI bit of UiC1 register = 0 (data present in UiTB register)

_______ ________ If CTS function is selected, input on the CTSi pin = “L”

Reception start condition • Before reception can start, the following requirements must be met_ The RE bit of UiC1 register= 1 (reception enabled)_ Start bit detection

• For transmission, one of the following conditions can be selected_ The UiIRS bit (Note 2) = 0 (transmit buffer empty): when transferring data from the

UiTB register to the UARTi transmit register (at start of transmission)_ The UiIRS bit =1 (transfer completed): when the serial I/O finished sending data from


• For reception

When transferring data from the UARTi receive register to the UiRB register (at completion of reception)


This error occurs if the serial I/O started receiving the next data before reading theUiRB register and received the bit one before the last stop bit of the next data

• Framing error

This error occurs when the number of stop bits set is not detected• Parity error

This error occurs when if parity is enabled, the number of 1’s in parity and

character bits does not match the number of 1’s set• Error sum flag

This flag is set (= 1) when any of the overrun, framing, and parity errors is encountered

Select function • LSB first, MSB first selection

Whether to start sending/receiving data beginning with bit 0 or beginning with bit 7can be selected

• Serial data logic switch

This function reverses the logic of the transmit/receive data. The start and stop bitsare not reversed.

• TXD, RXD I/O polarity switch

This function reverses the polarities of hte TXD pin output and RXD pin input. Thelogic levels of all I/O data is reversed.

_______ _______

• Separate CTS/RTS pins (UART0)_________ _________

CTS0 and RTS0 are input/output from separate pinsNote 1: If an overrun error occurs, the value of UiRB register will be indeterminate. The IR bit of SiRIC register does not change.Note 2: The U0IRS and U1IRS bits respectively are the UCON register bits 0 and 1; the U2IRS bit is the U2C1 register bit 4.Note 3: CKDIR of U2MR must be set “0” to select internal clock.

Clock Asynchronous Serial I/O (UART) ModeThe UART mode allows transmitting and receiving data after setting the desired transfer rate and transferdata format. Table 1.15.1 lists the specifications of the UART mode.

Interrupt requestgeneration timing

Table 1.15.1. UART Mode Specifications



Table 1.15.2. Registers to Be Used and Settings in UART ModeRegister Bit Function

UiTB 0 to 8 Set transmission data (Note 1)

UiRB 0 to 8 Reception data can be read (Note 1)

OER,FER,PER,SUM Error flag

UiBRG 0 to 7 Set a transfer rate

UiMR SMD2 to SMD0 Set these bits to ‘1002’ when transfer data is 7 bits long

Set these bits to ‘1012’ when transfer data is 8 bits long

Set these bits to ‘1102’ when transfer data is 9 bits long

CKDIR Select the internal clock or external clock

STPS Select the stop bit

PRY, PRYE Select whether parity is included and whether odd or even

IOPOL Select the TxD/RxD input/output polarity

UiC0 CLK0, CLK1 Select the count source for the UiBRG register

CRS_______ _______

Select CTS or RTS to use

TXEPT Transmit register empty flag

CRD_______ _______

Enable or disable the CTS or RTS function

NCH Select TxDi pin output mode (Note 2)

CKPOL Set to “0”

UFORM LSB first or MSB first can be selected when transfer data is 8 bits long. Set this

bit to “0” when transfer data is 7 or 9 bits long.

UiC1 TE Set this bit to “1” to enable transmission

TI Transmit buffer empty flag

RE Set this bit to “1” to enable reception

RI Reception complete flag

U2IRS (Note 2) Select the source of UART2 transmit interrupt

U2RRM (Note 2) Set to “0”

UiLCH Set this bit to “1” to use inverted data logic

UiERE Set to “0”

UiSMR 0 to 7 Set to “0”




UCON U0IRS, U1IRS Select the source of UART0/UART1 transmit interrupt

U0RRM, U1RRM Set to “0”

CLKMD0 Invalid because CLKMD1 = 0

CLKMD1 Set to “0”

RCSP_________

Set this bit to “1” to accept as input the UART0 CTS0 signal from the P64 pin

7 Set to “0”

Note 1: The bits used for transmit/receive data are as follows: Bit 0 to bit 6 when transfer data is 7 bits long;

bit 0 to bit 7 when transfer data is 8 bits long; bit 0 to bit 8 when transfer data is 9 bits long.

Note 2: Set the U0C1 and U1C1 registers bit 4 to bit 5 to “0”. The U0IRS, U1IRS, U0RRM and U1RRM bits

are included in the UCON register.

Note 3: TxD2 pin is N channel open-drain output. Set the U2C0 register's NCH bit to “0”.

i=0 to 2



Table 1.15.3 lists the functions of the input/output pins during UART mode. Table 1.15.4 lists the P64 pin

functions during UART mode. Note that for a period from when the UARTi operation mode is selected to

when transfer starts, the TxDi pin outputs an “H”. (If the N-channel open-drain output is selected, this pin

is in a high-impedance state.)

Table 1.15.3. I/O Pin Functions

Pin name Function Method of selection

TxDi (i = 0 to 2)(P63, P67, P70)

Serial data output

Serial data input

Input/output port

Transfer clock input

Input/output port

(Outputs dummy data when performing reception only)

RxDi(P62, P66, P71)

CLKi(P61, P65)

UiMR register’s CKDIR bit=0

UiMR register’s CKDIR bit=1PD6 register’s PD6_1 bit=0, PD6_5 bit=0, PD7 register’s PD7_2 bit=0

PD6 register’s PD6_2 bit=0, PD6_6 bit=0, PD7 register’s PD7_1 bit=0(Can be used as an input port when performing transmission only)

UiC0 register’s CRD bit=0UiC0 register’s CRS bit=0PD6 register’s PD6_0 bit=0, PD6_4 bit=0, PD7 register’s PD7_3 bit=0

UiC0 register’s CRD bit=0UiC0 register’s CRS bit=1

UiC0 register’s CRD bit=1

CTS input

RTS output

CTSi/RTSi(P60, P64, P73)

Table 1.15.4. P64 Pin Functions

Pin function Bit set value

U1C0 register UCON register PD6 register CRD CRS RCSP CLKMD1 PD6_4

P64 1 0 0 Input: 0, Output: 1CTS1 0 0 0 0RTS1 1 0 0CTS0 (Note) 0

000 0 1 0

Note: In addition to this, set the U0C0 register’s CRD bit to “0” (CTS0/RTS0 enabled) and the U0C0 register’s CRS bit to “1” (RTS0 selected).



Startbit

Parity bit

TxDi

CTSi

“1”

“0”

“1”

“L”

“H”

“0”

“1”

Tc = 16 (n + 1) / fj or 16 (n + 1) / fEXT

fj : frequency of UiBRG count source (f1SIO, f2SIO, f8SIO, f32SIO) fEXT : frequency of UiBRG count source (external clock) n : value set to UiBRG i: 0 to 2

“0”

“1”

TxDi

“0”

“1”

“0”

“1”

“0”

“1”

Transfer clock

Tc

“0”

“1”

Tc

Transfer clock

D0 D1 D2 D3 D4 D5 D6 D7ST P D0 D1 D2 D3 D4 D5 D6 D7SP ST P SP D0 D1ST

Stop bit

Start bit

The transfer clock stops momentarily as CTSi is “H” when the stop bit is checked. The transfer clock starts as the transfer starts immediately CTSi changes to “L”.

D0 D1 D2 D3 D4 D5 D6 D7ST SPD8 D0 D1 D2 D3 D4 D5 D6 D7ST D8 D0 D1STSPSP

Stop bit

Stop bit

“0”

SP

Stopped pulsing because the TE bit = “0”


UiC1 registerTE bit

UiC1 registerTI bit




The above timing diagram applies to the case where the register bits are set as follows: • UiMR register PRYE bit = 1 (parity enabled) • UiMR register STPS bit = 0 (1 stop bit) • UiC0 register CRD bit = 0 (CTS/RTS enabled), CRS bit = 0 (CTS selected) • UiRS bit = 1 (an interrupt request occurs when transmit completed): U0IRS bit is the UCON register bit 0, U1IRS bit is the UCON register bit 1, and U2IRS bit is the U2C1 register bit 4


UiC1 registerTE bit

UiC1 registerTI bit






Tc = 16 (n + 1) / fj or 16 (n + 1) / fEXT

fj : frequency of UiBRG count source (f1SIO, f2SIO, f8SIO, f32SIO) fEXT : frequency of UiBRG count source (external clock) n : value set to UiBRG i: 0 to 2

The above timing diagram applies to the case where the register bits are set as follows: • UiMR register PRYE bit = 0 (parity disabled) • UiMR register STPS bit = 1 (2 stop bits) • UiC0 register CRD bit = 1 (CTS/RTS disabled) • UiRS bit = 0 (an interrupt request occurs when transmit buffer becomes empty): U0IRS bit is the UCON register bit 0, U1IRS bit is the UCON register bit 1, and U2IRS bit is the U2C1 register bit 4

(1) Example of transmit timing when transfer data is 8 bits long (parity enabled, one stop bit)

(2) Example of transmit timing when transfer data is 9 bits long (parity disabled, two stop bits)

Figure 1.15.1. Transmit Operation



• Example of receive timing when transfer data is 8 bits long (parity disabled, one stop bit)

Figure 1.15.2. Receive Operation

D0Start bit

Sampled “L”

UiBRG count source

RxDi

Transfer clock

RTSi

Stop bit

“1”

“0”

“0”

“1”

“H”“L”

“0”“1”

Reception triggered when transfer clock is generated by falling edge of start bit

UiC1 registerRE bit

UiC1 registerRI bit

SiRIC registerIR bit


Receive data taken in

D7D1

Transferred from UARTi receive register to UiRB register

The above timing diagram applies to the case where the register bits are set as follows: • UiMR register PRYE bit = 0 (parity disabled) • UiMR register STPS bit = 0 (1 stop bit) • UiC0 register CRD bit = 0 (CTSi/RTSi enabled), CRS bit = 1 (RTSi selected) i = 0 to 2

Table 1.15.5. Example of Bit Rates and Settings

etaRtiB)spb(

ecruoStnuoCGRBfo

zHM61:kcolCnoitcnuFlarehpireP zHM42:kcolCnoitcnuFlarehpireP

n:GRBfoeulaVteS )spb(emiTlautcA n:GRBfoeulavteS )spb(emiTlautcA

0021 8f )h76(301 2021 )h69(551 2021

0042 8f )h33(15 4042 )h64(77 4042

0084 8f )h91(52 8084 )h62(83 8084

0069 1f )h76(301 5169 )h69(551 5169

00441 1f )h44(86 39441 )h76(301 32441

00291 1f )h33(15 13291 )h64(77 13291

00882 1f )h22(43 17582 )h33(15 64882

05213 1f )hF1(13 05213 )hF2(74 05213

00483 1f )h91(52 26483 )h62(83 26483

00215 1f )h31(91 00005 )hC1(82 42715

Bit Rates

In UART mode, the frequency set by the UiBRG register (i=0 to 2) divided by 16 become the bit rates.

Table 1.15.5 lists example of bit rates and settings.



(a) LSB First/MSB First Select Function

As shown in Figure 1.15.3, use the UiC0 register’s UFORM bit to select the transfer format. This

function is valid when transfer data is 8 bits long.

Figure 1.15.3. Transfer Format

(1) When UiC0 register's UFORM bit = 0 (LSB first)

(2) When UiC0 register's UFORM bit = 1 (MSB first)

Note: This applies to the case where the UiC0 register’s CKPOL bit = 0 (transmit data output at the falling edge and the receive data taken in at the rising edge of the transfer clock), the UiC1 register’s UiLCH bit = 0 (no reverse), UiMR register's STPS bit = 0 (1 stop bit) and UiMR register's PRYE bit = 1 (parity enabled).

D1 D2 D3 D4 D5 D6 SPD0

D1 D2 D3 D4 D5 D6 SPD0

TXDi

RXDi

CLKi

D6 D5 D4 D3 D2 D1 D0D7

TXDi

RXDi

CLKi

ST

ST

D7 P

D7 P

SP

SP

ST

ST

P

P

D6 D5 D4 D3 D2 D1 D0D7

ST : Start bitP : Parity bitSP : Stop biti = 0 to 2

Counter Measure for Communication Error Occurs

If a communication error occurs while transmitting or receiving in UART mode, follow the procedures

below.

• Resetting the UiRB register (i=0 to 2)

(1) Set the RE bit in the UiC1 register to “0” (reception disabled)

(2) Set the RE bit in the UiC1 register to “1” (reception enabled)

• Resetting the UiTB register (i=0 to 2)

(1) Set the SMD2 to SMD0 bits in the UiMR register “000b” (Serial I/O disabled)

(2) Set the SMD2 to SMD0 bits in the UiMR register “001b”, “101b”, “110b”.

(3) “1” is written to RE bit in the UiC1 register (reception enabled), regardless of the TE bit in the UiCi

register



(c) TxD and RxD I/O Polarity Inverse Function

This function inverses the polarities of the TXDi pin output and RXDi pin input. The logic levels of all

input/output data (including the start, stop and parity bits) are inversed. Figure 1.15.5 shows the TXD

pin output and RXD pin input polarity inverse.

Figure 1.15.5. TXD and RXD I/O Polarity Inverse

(1) When the UiMR register's IOPOL bit = 0 (no reverse)

(2) When the UiMR register's IOPOL bit = 1 (reverse)

Note: This applies to the case where the UiC0 register's UFORM bit = 0 (LSB first), the UiMR register's STPS bit = 0 (1 stop bit) and the UiMR register's PRYE bit = 1 (parity enabled).


D0 D1 D2 D3 D4 D5 D6 D7 P SPST

SPST D3 D4 D5 D6 D7 PD0 D1 D2

D0 D1 D2 D3 D4 D5 D6 D7 P SPST“H”

SPST D3 D4 D5 D6 D7 PD0 D1 D2

Transfer clock

TxDi(no reverse)

RxDi(no reverse)

Transfer clock

TxDi(reverse)

RxDi(reverse)

“L”

“H”

“L”

“H”

“L”

“H”

“L”

“H”

“L”

“H”

“L”

(b) Serial Data Logic Switching Function

The data written to the UiTB register has its logic reversed before being transmitted. Similarly, the

received data has its logic reversed when read from the UiRB register. Figure 1.15.4 shows serial data

logic.

Figure 1.15.4. Serial Data Logic Switching

Transfer clock “H”

“L”

D0 D1 D2 D3 D4 D5 D6 D7 P SPSTTxDi(no reverse)

“H”

“L”

TxDi(reverse) SPST D3 D4 D5 D6 D7 PD0 D1 D2

“H”

“L”

(1) When the UiC1 register's UiLCH bit = 0 (no reverse)

(2) When the UiC1 register's UiLCH bit = 1 (reverse)

Transfer clock “H”

“L”

Note: This applies to the case where the UiC0 register’s CKPOL bit = 0 (transmit data output at the falling edge of the transfer clock), the UiC0 register's UFORM bit = 0 (LSB first), the UiMR register's STPS bit = 0 (1 stop bit) and UiMR register's PRYE bit = 1 (parity enabled).




_______ _______

(e) CTS/RTS Separate Function (UART0)_______ _______ _______ _______

This function separates CTS0/RTS0, outputs RTS0 from the P60 pin, and accepts as input the CTS0

from the P64 pin. To use this function, set the register bits as shown below._______ _______


• U0C0 register's CRS bit = 1 (outputs UART0 RTS)_______ _______


• U1C0 register's CRS bit = 0 (inputs UART1 CTS)_______

• UCON register's RCSP bit = 1 (inputs CTS0 from the P64 pin)

• UCON register's CLKMD1 bit = 0 (CLKS1 not used)_______ _______ _______ _______

Note that when using the CTS/RTS separate function, UART1 CTS/RTS separate function cannot be

used.

_______ _______

Figure 1.15.6. CTS/RTS Separate Function

MicrocomputerTXD0 (P63)

RXD0 (P62)INOUT

CTS

RTSCTS0 (P64)

RTS0 (P60)

IC

_______ _______

(d) CTS/RTS Function_______ ________ ________

When the CTS function is used transmit operation start when “L” is applied to the CTSi/RTSi (i=0 to 2)________ ________

pin. Transmit operation begins when the CTSi/RTSi pin is held “L”. If the “L” signal is switched to “H”

during a transmit operation, the operation stops before the next data._______ ________ ________

When the RTS function is used, the CTSi/RTSi pin outputs on “L” signal when the microcomputer is

ready to receive. The output level becomes “H” on the first falling edge of the CLKi pin._______ _______

• CRD bit in UiC0 register = 1 (disable CTS/RTS function of UART0)________ ________

CTSi/RTSi pin is programmable I/O function_______

• CRD bit = 0, CRS bit = 0 (CTS function is selected)________ ________ _______

CTSi/RTSi pin is CTS function_______

• CRD bit = 0, CRS bit = 1 (RTS function is selected)________ ________ _______

CTSi/RTSi pin is RTS function

M16C/6S Group Special Mode


Special Mode 1 (I2C mode)I2C mode is provided for use as a simplified I2C interface compatible mode. Table 1.16.1 lists the speci-

fications of the I2C mode. Table 1.16.2 lists the registers used in the I2C mode and the register values

set. Figure 1.16.1 shows the block diagram for I2C mode. Figure 1.16.2 shows SCLi timing.

As shown in Table 1.16.4, the microcomputer is placed in I2C mode by setting the SMD2 to SMD0 bits to

‘0102’ and the IICM bit to “1”. Because SDAi transmit output has a delay circuit attached, SDAi output

does not change state until SCLi goes low and remains stably low.

Table 1.16.1. I2C Mode SpecificationsItem Specification


Transfer clock • During master

UiMR(i=0 to 2) register’s CKDIR bit = “0” (internal clock) : fj/ 2(n+1)


• During slave

CKDIR bit = “1” (external clock) : Input from CLKi pin



When start or stop condition is detected, acknowledge undetected, and acknowledge

detected



UiRB register and received the 8th bit of the data

Select function • Arbitration lost

Timing at which the UiRB register’s ABT bit is updated can be selected

• SDAi digital delay

No digital delay or a delay of 2 to 8 UiBRG count source clock cycles selectable

• Clock phase setting

With or without clock delay selectable

Note 1: When an external clock is selected, the conditions must be met while the external clock is in the

high state.

Note 2: If an overrun error occurs, the value of UiRB register will be indeterminate. The IR bit of SiRIC

register does not change.

Interrupt requestgeneration timing



CLK control

Falling edge detection

External clock

Internal clock

Start/stop condition detection interrupt request

Start condition detection

Stop condition detection

Reception register

Bus busy

Transmission register

ArbitrationNoiseFilter

SDAi

SCLi

UARTi

D

TQ

D

TQ

D

TQ

NACK

ACK

UARTi

UARTi

UARTi

R

UARTi transmit, NACK interrupt request

UARTi receive,ACK interrupt request,DMA1 request

IICM=1 andIICM2=0

S

RQ

ALS

R

S SWC

IICM=1 and IICM2=0

IICM2=1

IICM2=1

SWC2

SDHI

DMA0, DMA1 request(UART1: DMA0 only)

NoiseFilter

i=0 to 2

IICM=0

IICM=1

DMA0(UART0, UART2)

STPSEL=0

STPSEL=1

STPSEL=1

STPSEL=0

SDASTSP

SCLSTSP

ACK=1 ACK=0

Q

Port register(Note)I/O port

9th bit falling edge

9th bit

ACKD register

Delay circuit

This diagram applies to the case where the UiMR register's SMD2 to SMD0 bits = 0102 and the UiSMR register's IICM bit = 1.

Note: When the IICM bit =1, the pins can be read even if the direction bit = 1 (output).

Start and stop condition generation block

IICM : Bit in UiSMR registerIICM2, SWC, ALS, SWC2, SDHI : Bit in UiSMR2 registerSTSPSEL, ACKD, ACKC : Bit in UiSMR4 register

Figure 1.16.1. I2C Mode Block Diagram



Table 1.16.2. Registers to Be Used and Settings in I2C Mode (1) (Continued)Register Bit Function

Master SlaveUiTB3 0 to 7 Set transmission data Set transmission dataUiRB3 0 to 7 Reception data can be read Reception data can be read

8 ACK or NACK is set in this bit ACK or NACK is set in this bitABT Arbitration lost detection flag InvalidOER Overrun error flag Overrun error flag

UiBRG 0 to 7 Set a transfer rate InvalidUiMR3 SMD2 to SMD0 Set to ‘0102’ Set to ‘0102’

CKDIR Set to “0” Set to “1”IOPOL Set to “0” Set to “0”

UiC0 CLK1, CLK0 Select the count source for the UiBRG Invalidregister

CRS Invalid because CRD = 1 Invalid because CRD = 1TXEPT Transmit buffer empty flag Transmit buffer empty flagCRD Set to “1” Set to “1”NCH Set to “1”2 Set to “1”2

CKPOL Set to “0” Set to “0”UFORM Set to “1” Set to “1”

UiC1 TE Set this bit to “1” to enable transmission Set this bit to “1” to enable transmissionTI Transmit buffer empty flag Transmit buffer empty flagRE Set this bit to “1” to enable reception Set this bit to “1” to enable receptionRI Reception complete flag Reception complete flagU2IRS1 Invalid InvalidU2RRM1, Set to “0” Set to “0”UiLCH, UiERE

UiSMR IICM Set to “1” Set to “1”ABC Select the timing at which arbitration-lost Invalid

is detectedBBS Bus busy flag Bus busy flag3 to 7 Set to “0” Set to “0”

UiSMR2 IICM2 Refer to Table 1.16.4. Refer to Table 1.16.4.CSC Set this bit to “1” to enable clock Set to “0”

synchronizationSWC Set this bit to “1” to have SCLi output Set this bit to “1” to have SCLi output

fixed to “L” at the falling edge of the 9th fixed to “L” at the falling edge of the 9thbit of clock bit of clock

ALS Set this bit to “1” to have SDAi output Set to “0”stopped when arbitration-lost is detected

STAC Set to “0” Set this bit to “1” to initialize UARTi atstart condition detection

SWC2 Set this bit to “1” to have SCLi output Set this bit to “1” to have SCLi outputforcibly pulled low forcibly pulled low

SDHI Set this bit to “1” to disable SDAi output Set this bit to “1” to disable SDAi output7 Set to “0” Set to “0”

UiSMR3 0, 2, 4 and NODC Set to “0” Set to “0”CKPH Refer to Table 1.16.4 Refer to Table 1.16.4DL2 to DL0 Set the amount of SDAi digital delay Set the amount of SDAi digital delay

i=0 to 2Notes: 1. Set the U0C1 and U1C1 register bit 4 and bit 5 to “0”. The U0IRS, U1IRS, U0RRM and U1RRM bits are

in the UCON register. 2. TxD2 pin is N channel open-drain output. Set the NCH bit in the U2C0 register to “0”. 3. Not all register bits are described above. Set those bits to “0” when writing to the registers in I2C mode.



UiSMR4 STAREQ Set this bit to “1” to generate start Set to “0”condition

RSTAREQ Set this bit to “1” to generate restart Set to “0”condition

STPREQ Set this bit to “1” to generate stop Set to “0”condition

STSPSEL Set this bit to “1” to output each condition Set to “0”ACKD Select ACK or NACK Select ACK or NACKACKC Set this bit to “1” to output ACK data Set this bit to “1” to output ACK dataSCLHI Set this bit to “1” to have SCLi output Set to “0”

stopped when stop condition is detectedSWC9 Set to “0” Set this bit to “1” to set the SCLi to “L”

hold at the falling edge of the 9th bit ofclock

IFSR2A IFSR26, ISFR27 Set to “1” Set to “1”UCON U0IRS, U1IRS Invalid Invalid

2 to 7 Set to “0” Set to “0”

Register Bit FunctionMaster Slave

Table 1.16.3. Registers to Be Used and Settings in I2C Mode (2) (Continued)

i=0 to 2



Table 1.16.4. I2C Mode FunctionsFunction I2C Mode (SMD2 to SMD0 = 010b, IICM = 1)Clock Synchronous Serial I/O

Mode (SMD2 to SMD0 = 001b, IICM = 0)

Factor of Interrupt Number 15, 17 and 19 (1, 6)

No acknowledgment detection (NACK) Rising edge of SCLi 9th bit

Factor of Interrupt Number 16, 18 and 20 (1, 6)

Start condition detection or stop condition detection(See Table 1.16.5 STSPSEL Bit Functions)

UARTi Transmission Output Delay

Functions of P6_3, P6_7 and P7_0 Pins

Noise Filter Width

Read RXDi and SCLi Pin Levels

Factor of Interrupt Number 6, 7 and 10 (1, 5, 7)

Acknowledgment detection (ACK) Rising edge of SCLi 9th bit

Initial Value of TXDi and SDAi Outputs

UARTi transmissionTransmission started or completed (selected by UiIRS)UARTi receptionWhen 8th bit receivedCKPOL = 0 (rising edge)CKPOL = 1 (falling edge)

Not delayed

TXDi output

RXDi input

CLKi input or output selected

15ns

Possible when the corresponding port direction bit = 0

CKPOL = 0 (H)CKPOL = 1 (L)

Delayed

SDAi input/output

SCLi input/output

(Cannot be used in I2C mode)

Initial and End Values of SCLi

H

200ns

Always possible no matter how the corresponding port direction bit is set

The value set in the port register before setting I2C mode (2)

Timing for Transferring Data From the UART Reception Shift Register to the UiRB Register

IICM2 = 0 (NACK/ACK interrupt)

IICM2 = 1(UART transmit/ receive interrupt)

CKPH = 1(Clock delay)

CKPH = 1(Clock delay)

UARTi transmissionRising edge of SCLi 9th bit

UARTi transmissionFalling edge of SCLi next to the 9th bit

UARTi receptionFalling edge of SCLi 9th bit

CKPOL = 0 (rising edge)CKPOL = 1 (falling edge)

Rising edge of SCLi 9th bit Falling edge of SCLi 9th bit

Falling and rising edges of SCLi 9th bit



i = 0 to 2NOTES :

1. If the source or cause of any interrupt is changed, the IR bit in the interrupt control register for the changed interrupt may inadvertently be set to “1” (interrupt requested). (Refer to Changing the Interrupt Generate Factor.) If one of the bits shown below is changed, the interrupt source, the interrupt timing, etc. change. Therefore, always be sure to clear the IR bit to “0” (interrupt not requested) after changing those bits.SMD2 to SMD0 bits in the UiMR register, IICM bit in the UiSMR register, IICM2 bit in the UiSMR2 register, CKPH bit in the UiSMR3 register

2. Set the initial value of SDAi output while the SMD2 to SMD0 bits in the UiMR register = 000b (serial I/O disabled).3. Second data transfer to UiRB register (Rising edge of SCLi 9th bit)4. First data transfer to UiRB register (Falling edge of SCLi 9th bit)5. See Figure 1.16.4 STSPSEL Bit Functions.6. See Figure 1.16.2 Transfer to UiRB Register and Interrupt Timing.7. When using UART0, be sure to set the IFSR26 bit in the IFSR2A register to “1” (factor of interrupt: UART0 bus collision).

When using UART1, be sure to set the IFSR27 bit to “1” (factor of interrupt: UART1 bus collision).

DMA1 Factor (6) UARTi reception Acknowledgment detection (ACK)

UARTi receptionFalling edge of SCLi 9th bit

Store Received Data1st to 8th bits of the received data are stored into bits 7 to 0 in the UiRB register

1st to 8th bits of the received data are stored into bits 7 to 0 in the UiRB register

1st to 7th bits of the received data are stored into bits 6 to 0 in the UiRB register. 8th bit is stored into bit 8 in the UiRB register.

L

Bits 6 to 0 in the UiRB register (4) are read as bits 7 to 1. Bit 8 in the UiRB register is read as bit 0.

Read Received Data The UiRB register status is read

CKPH = 0(No clock delay)

CKPH = 0(No clock delay)

HL

1st to 8th bits are stored into bits 7 to 0 in the UiRB register (3)



Figure 1.16.2. Transfer to UiRB Register and Interrupt Timing

(3) IICM2= 1 (UART transmit/receive interrupt), CKPH= 0

(1) IICM2= 0 (ACK and NACK interrupts), CKPH= 0 (no clock delay)

i=0 to 2

This diagram applies to the case where the following condition is met. • UiMR register CKDIR bit = 0 (Slave selected)

ACK interrupt (DMA1 request), NACK interrupt

Transfer to UiRB register

Receive interrupt (DMA1 request)

Transmit interrupt


(4) IICM2= 1, CKPH= 1

D6 D5 D4 D3 D2 D1D7SDAi

SCLi

D0

D6 D5 D4 D3 D2 D1D7SDAi

SCLi

D0

D6 D5 D4 D3 D2 D1 D8 (ACK, NACK)D7SDAi

SCLi

D0

D8 (ACK, NACK)

D8 (ACK, NACK)

D6 D5 D4 D3 D2 D1 D8 (ACK, NACK)D7SDAi

SCLi

D0

1st bit 2nd bit 3rd bit 4th bit 5th bit 6th bit 7th bit 8th bit 9th bit

b15

•••

b9 b8 b7 b0

D8 D7 D6 D5 D4 D3 D2 D1 D0

UiRB register

b15

•••

b9 b8 b7 b0

D8 D7 D6 D5 D4 D3 D2 D1 D0

b15

•••

b9 b8 b7 b0

D0 D7 D6 D5 D4 D3 D2 D1

b15

•••

b9 b8 b7 b0

D0 D7 D6 D5 D4 D3 D2 D1

b15

•••

b9 b8 b7 b0

D8 D7 D6 D5 D4 D3 D2 D1 D0




(2) IICM2= 0, CKPH= 1 (clock delay)

ACK interrupt (DMA1 request), NACK interrupt


UiRB register

Transmit interrupt


Receive interrupt (DMA1 request)


UiRB register

UiRB register UiRB register



• Detection of Start and Stop Condition

Whether a start or a stop condition has been detected is determined.

A start condition-detected interrupt request is generated when the SDAi pin changes state from high to

low while the SCLi pin is in the high state. A stop condition-detected interrupt request is generated

when the SDAi pin changes state from low to high while the SCLi pin is in the high state.

Because the start and stop condition-detected interrupts share the interrupt control register and vec-

tor, check the UiSMR register’s BBS bit to determine which interrupt source is requesting the interrupt.

Figure 1.16.3. Detection of Start and Stop Condition

• Output of Start and Stop Condition

A start condition is generated by setting the STAREQ bit in the UiSMR4 register (i = 0 to 2) to “1”

(start).

A restart condition is generated by setting the RSTAREQ bit in the UiSMR4 register to “1” (start).

A stop condition is generated by setting the STPREQ bit in the UiSMR4 register to “1” (start).

The output procedure is described below.

(1) Set the STAREQ bit, RSTAREQ bit or STPREQ bit to “1” (start).

(2) Set the STSPSEL bit in the UiSMR4 register to “1” (output).

The function of the STSPSEL bit is shown in Table 1.16.5 and Figure 1.16.4.

3 to 6 cycles < duration for setting-up (Note)

3 to 6 cycles < duration for holding (Note)

i = 0 to 2Note: When the PCLKR register's PCLK1 bit = 1, this is the cycle number of f1SIO, and the PCLK1 bit = 0, this is the cycle number of f2SIO.

Duration for setting up

Duration for holding

SCLi

SDAi(Start condition)

SDA i(Stop condition)



Table 1.16.5. STSPSEL Bit Functions

Figure 1.16.4. STSPSEL Bit Functions

Function

Output of SCLi and SDAi pins

Star/stop condition interrupt

request generation timing

STSPSEL = 0

Output of transfer clock and

data

Output of start/stop condition is

accomplished by a program

using ports (not automatically

generated in hardware)

Start/stop condition detection

STSPSEL = 1

Output of a start/stop condition

according to the STAREQ,

RSTAREQ and STPREQ bit

Finish generating start/stop condi-

tion

Start condition detection interrupt

Stop condition detection interrupt

(1) When slave CKDIR=1 (external clock)

Start condition detection interrupt

Stop condition detection interrupt

(2) When master CKDIR=0 (internal clock), CKPH=1 (clock delayed)

SDAi

SCLi

Set STAREQ=1 (start)

Set STPREQ=1 (start)

STPSEL bit 0

SDAi

SCLi

STPSEL bit

Set to “1” in a program




1st 2nd 3rd 4th 5th 6th 7th 8th 9th bit

1st 2nd 3rd 4th 5th 6th 7th 8th 9th bit

• Arbitration

Unmatching of the transmit data and SDAi pin input data is checked synchronously with the rising

edge of SCLi. Use the UiSMR register’s ABC bit to select the timing at which the UiRB register’s ABT

bit is updated. If the ABC bit = 0 (updated bitwise), the ABT bit is set to “1” at the same time

unmatching is detected during check, and is cleared to “0” when not detected. In cases when the ABC

bit is set to “1”, if unmatching is detected even once during check, the ABT bit is set to “1” (unmatching

detected) at the falling edge of the clock pulse of 9th bit. If the ABT bit needs to be updated bytewise,

clear the ABT bit to “0” (undetected) after detecting acknowledge in the first byte, before transferring

the next byte.

Setting the UiSMR2 register’s ALS bit to “1” (SDA output stop enabled) causes arbitration-lost to

occur, in which case the SDAi pin is placed in the high-impedance state at the same time the ABT bit

is set to “1” (unmatching detected).



• Transfer Clock

Data is transmitted/received using a transfer clock like the one shown in Figure 1.16.4.

The UiSMR2 register’s CSC bit is used to synchronize the internally generated clock (internal SCLi)

and an external clock supplied to the SCLi pin. In cases when the CSC bit is set to “1” (clock synchro-

nization enabled), if a falling edge on the SCLi pin is detected while the internal SCLi is high, the

internal SCLi goes low, at which time the UiBRG register value is reloaded with and starts counting in

the low-level interval. If the internal SCLi changes state from low to high while the SCLi pin is low,

counting stops, and when the SCLi pin goes high, counting restarts.

In this way, the UARTi transfer clock is comprised of the logical product of the internal SCLi and SCLi

pin signal. The transfer clock works from a half period before the falling edge of the internal SCLi 1st

bit to the rising edge of the 9th bit. To use this function, select an internal clock for the transfer clock.

The UiSMR2 register’s SWC bit allows to select whether the SCLi pin should be fixed to or freed from

low-level output at the falling edge of the 9th clock pulse.

If the UiSMR4 register’s SCLHI bit is set to “1” (enabled), SCLi output is turned off (placed in the high-

impedance state) when a stop condition is detected.

Setting the UiSMR2 register’s SWC2 bit = 1 (0 output) makes it possible to forcibly output a low-level

signal from the SCLi pin even while sending or receiving data. Clearing the SWC2 bit to “0” (transfer

clock) allows the transfer clock to be output from or supplied to the SCLi pin, instead of outputting a

low-level signal.

If the UiSMR4 register’s SWC9 bit is set to “1” (SCL hold low enabled) when the UiSMR3 register’s

CKPH bit = 1, the SCLi pin is fixed to low-level output at the falling edge of the clock pulse next to the

ninth. Setting the SWC9 bit = 0 (SCL hold low disabled) frees the SCLi pin from low-level output.

• SDA Output

The data written to the UiTB register bit 7 to bit 0 (D7 to D0) is sequentially output beginning with D7.

The ninth bit (D8) is ACK or NACK.

The initial value of SDAi transmit output can only be set when IICM = 1 (I2C mode) and the UiMR

register’s SMD2 to SMD0 bits = ‘0002’ (serial I/O disabled).

The UiSMR3 register’s DL2 to DL0 bits allow to add no delays or a delay of 2 to 8 UiBRG count source

clock cycles to SDAi output.

Setting the UiSMR2 register’s SDHI bit = 1 (SDA output disabled) forcibly places the SDAi pin in the

high-impedance state. Do not write to the SDHI bit synchronously with the rising edge of the UARTi

transfer clock. This is because the ABT bit may inadvertently be set to “1” (detected).

• SDA Input

When the IICM2 bit = 0, the 1st to 8th bits (D7 to D0) of received data are stored in the UiRB register bit

7 to bit 0. The 9th bit (D8) is ACK or NACK.

When the IICM2 bit = 1, the 1st to 7th bits (D7 to D1) of received data are stored in the UiRB register bit

6 to bit 0 and the 8th bit (D0) is stored in the UiRB register bit 8. Even when the IICM2 bit = 1, providing

the CKPH bit = 1, the same data as when the IICM2 bit = 0 can be read out by reading the UiRB

register after the rising edge of the corresponding clock pulse of 9th bit.



• ACK and NACK

If the STSPSEL bit in the UiSMR4 register is set to “0” (start and stop conditions not generated) and

the ACKC bit in the UiSMR4 register is se to “1” (ACK data output), the value of the ACKD bit in the

UiSMR4 register is output from the SDAi pin.

If the IICM2 bit = 0, a NACK interrupt request is generated if the SDAi pin remains high at the rising

edge of the 9th bit of transmit clock pulse. An ACK interrupt request is generated if the SDAi pin is low

at the rising edge of the 9th bit of transmit clock pulse.

If ACKi is selected for the cause of DMA1 request, a DMA transfer can be activated by detection of an

acknowledge.

• Initialization of Transmission/Reception

If a start condition is detected while the STAC bit = 1 (UARTi initialization enabled), the serial I/O

operates as described below.

- The transmit shift register is initialized, and the content of the UiTB register is transferred to the

transmit shift register. In this way, the serial I/O starts sending data synchronously with the next

clock pulse applied. However, the UARTi output value does not change state and remains the same

as when a start condition was detected until the first bit of data is output synchronously with the input

clock.

- The receive shift register is initialized, and the serial I/O starts receiving data synchronously with the

next clock pulse applied.

- The SWC bit is set to “1” (SCL wait output enabled). Consequently, the SCLi pin is pulled low at the

falling edge of the ninth clock pulse.

Note that when UARTi transmission/reception is started using this function, the TI does not change

state. Note also that when using this function, the selected transfer clock should be an external clock.



Special Mode 2Multiple slaves can be serially communicated from one master. Synchronous clock polarity and phase

are selectable. Table 1.16.6 lists the specifications of Special Mode 2. Table 1.16.7 lists the registers

used in Special Mode 2 and the register values set. Figure 1.16.5 shows communication control example

for Special Mode 2. UART2 is not available in this mode.

Table 1.16.6. Special Mode 2 SpecificationsItem Specification


Transfer clock • Master mode

UiMR(i=0 to 1) register’s CKDIR bit = “0” (internal clock) : fj/ 2(n+1)


• Slave mode

CKDIR bit = “1” (external clock selected) : Input from CLKi pin

Transmit/receive control Controlled by input/output ports



• For transmission, one of the following conditions can be selected_ The UiIRS bit of UiC1 register = 0 (transmit buffer empty): when transferring data

from the UiTB register to the UARTi transmit register (at start of transmission)_ The UiIRS bit =1 (transfer completed): when the serial I/O finished sending data from


• For reception

When transferring data from the UARTi receive register to the UiRB register (at

completion of reception)



UiRB register and received the 7th bit of the next data

Select function • Clock phase setting

Selectable from four combinations of transfer clock polarities and phases

Note 1: When an external clock is selected, the conditions must be met while if the UiC0 register’s CKPOL bit = “0”

(transmit data output at the falling edge and the receive data taken in at the rising edge of the transfer clock),

the external clock is in the high state; if the UiC0 register’s CKPOL bit = “1” (transmit data output at the rising

edge and the receive data taken in at the falling edge of the transfer clock), the external clock is in the low

state.

Note 2: If an overrun error occurs, the value of UiRB register will be indeterminate. The IR bit of SiRIC register does

not change.

Interrupt request

generation timing



P81

P80

P63(TxD0)

P61(CLK0)

P62(RxD0)

P83

P63(TxD0)

P61(CLK0)

P62(RxD0)

P93

P63(TxD0)

P61(CLK0)

P62(RxD0)

Microcomputer (Master)

Microcomputer (Slave)

Microcomputer (Slave)

Figure 1.16.5. Serial Bus Communication Control Example (UART0)



Table 1.16.7. Registers to Be Used and Settings in Special Mode 2Register Bit FunctionUiTB(Note2) 0 to 7 Set transmission dataUiRB(Note2) 0 to 7 Reception data can be read

OER Overrun error flagUiBRG 0 to 7 Set a transfer rateUiMR(Note2) SMD2 to SMD0 Set to ‘0012’

CKDIR Set this bit to “0” for master mode or “1” for slave modeIOPOL Set to “0”

UiC0 CLK1, CLK0 Select the count source for the UiBRG registerCRS Invalid because CRD = 1TXEPT Transmit register empty flagCRD Set to “1”NCH Select TxDi pin output formatCKPOL Clock phases can be set in combination with the UiSMR3 register's CKPH bitUFORM Set to “0”

UiC1 TE Set this bit to “1” to enable transmissionTI Transmit buffer empty flagRE Set this bit to “1” to enable receptionRI Reception complete flagU2IRS (Note 1) Select UART2 transmit interrupt causeU2RRM(Note 1), Set to “0”U2LCH, UiERE

UiSMR 0 to 7 Set to “0”UiSMR2 0 to 7 Set to “0”UiSMR3 CKPH Clock phases can be set in combination with the UiC0 register's CKPOL bit

NODC Set to “0”0, 2, 4 to 7 Set to “0”

UiSMR4 0 to 7 Set to “0”UCON U0IRS, U1IRS Select UART0 and UART1 transmit interrupt cause

U0RRM, U1RRM Set to “0”CLKMD0 Invalid because CLKMD1 = 0CLKMD1, RCSP, 7 Set to “0”

Note 1: Set the U0C0 and U1C1 register bit 4 and bit 5 to “0”. The U0IRS, U1IRS, U0RRM and U1RRM bitsare in the UCON register.

Note 2: Not all register bits are described above. Set those bits to “0” when writing to the registers in SpecialMode 2.

i = 0 to 1



• Clock Phase Setting Function

One of four combinations of transfer clock phases and polarities can be selected using the UiSMR3

register’s CKPH bit and the UiC0 register’s CKPOL bit.

Make sure the transfer clock polarity and phase are the same for the master and salves to be commu-

nicated.

Figure 1.16.6 shows the transmission and reception timing in master (internal clock).

Figure 1.16.7 shows the transmission and reception timing (CKPH=0) in slave (external clock) while

Figure 1.16.8 shows the transmission and reception timing (CKPH=1) in slave (external clock).

Data output timing

Data input timing

D0 D1 D2 D3 D4 D6 D7D5

Clock output(CKPOL=0, CKPH=0)

"H"

"L"


"H"

"L"


"H"

"L"


"H"

"L"

"H"

"L"

Figure 1.16.6. Transmission and Reception Timing in Master Mode (Internal Clock)



Figure 1.16.7. Transmission and Reception Timing (CKPH=0) in Slave Mode (External Clock)

Figure 1.16.8. Transmission and Reception Timing (CKPH=1) in Slave Mode (External Clock)

Slave control input

Clock input(CKPOL=0, CKPH=0)


Data output timing

Data input timing

"H"

"L"

"H"

"L"

"H"

"L"

"H"

"L"D0 D1 D2 D3 D4 D6 D7D5

Indeterminate

(Note)



Data output timing

Data input timing

"H"

"L"

"H"

"L"

"H"

"L"

"H"

"L"D0 D1 D2 D3 D6 D7D4 D5

(Note)

Slave control input

M16C/6S Group SI/O3 and SI/O4


SI/O3 and SI/O4SI/O3 and SI/O4 are exclusive clock-synchronous serial I/Os.

Figure 1.17.1 shows the block diagram of SI/O3 and SI/O4, and Figure 1.17.2 shows the SI/O3 and SI/O4-

related registers. SI/O4 is derectly connected to IT800 internally.

Table 1.17.1 shows the specifications of SI/O3 and SI/O4.

Figure 1.17.1. SI/O3 and SI/O4 Block Diagram

Data bus

SI/Oi interrupt request

Note: i = 3, 4. n = A value set in the SiBRG register.

SiTRR register

SI/O counter i

8

SMi5 LSB MSB

SMi2SMi3

SMi3SMi6

SMi1 to SMi0

CLKi

SOUTi

SINi

SiBRG registerSMi6

1/(n+1)1/2

1/2

Main clock,or On-chip Oscillator clock

f1SIO

1/2

1/8

1/4

f8SIO

f32SIO

f2SIO PCLK1=0

PCLK1=1

SMi4

002

012

102

Clock source select

Synchronous circuit

CLK polarity

reversing circuit



Figure 1.17.2. S3C and S4C Registers, S3BRG and S4BRG Registers, and S3TRR and S4TRR Registers

SI/Oi bit rate generator (i = 3, 4) (Notes 1, 2)b7 b0 Symbol Address After reset

S3BRG 036316 Indeterminate S4BRG 036716 Indeterminate

Description

Assuming that set value = n, BRGi divides the count source by n + 1

0016 to FF16

Setting range RW

SI/Oi transmit/receive register (i = 3, 4) (Note 1, 2)

b7 b0 Symbol Address After reset S3TRR 036016 Indeterminate S4TRR 036416 Indeterminate

Description

Transmission/reception starts by writing transmit data to this register. After transmission/reception finishes, reception data can be read by reading this register.

Note 1: Write to this register while serial I/O is neither transmitting nor receiving. Note 2: To receive data, set the corresponding port direction bit for SINi to “0” (input mode).

S I/Oi control register (i = 3, 4) (Note 1)

Symbol Address After reset S3C 036216 010000016 S4C 036616 010000016

b7 b6 b5 b4 b3 b2 b1 b0

Description

SMi5

SMi1

SMi0

SMi3

SMi6

SMi7

Internal synchronous clock select bit

Transfer direction select bit

S I/Oi port select bit

SOUTi initial value set bit

0 0 : Selecting f1SIO or f2SIO 0 1 : Selecting f8SIO 1 0 : Selecting f32SIO

1 1 : Must not be set.

b1 b0

0 : External clock 1 : Internal clock

Effective when SMi3 = 00 : “L” output 1 : “H” output

0 : Input/output port 1 : SOUTi output, CLKi function

Bit nameBit symbol

Synchronous clock select bit

0 : LSB first 1 : MSB first

SMi2 SOUTi output disable bit 0 : SOUTi output 1 : SOUTi output disable(high impedance)

Note 1: Make sure this register is written to by the next instruction after setting the PRCR register's PRC2 bit to “1” (write enable).Note 2: Set the SMi3 bit to “1” (SOUTi output, CLKi function).Note 3: Set the SMi3 bit to “1” and the corresponding port direction bit to “0” (input mode).Note 4: Effective when SMi3 bit = 1.

CLK polarity select bitSMi4 0 : Transmit data is output at falling edge of transfer clock and receive data is input at rising edge 1 : Transmit data is output at rising edge of transfer clock and receive data is input at falling edge

RW

RW

RW

RW

RW

RW

RW

RW

RW

WO

RW

RW

(Note 4)

(Note 2)(Note 3)

Note 1: Write to this register while serial I/O is neither transmitting nor receiving. Note 2: Use MOV instruction to write to this register.



Item Specification


Transfer clock • SiC (i=3, 4) register’s SMi6 bit = “1” (internal clock) : fj/ 2(n+1)

fj = f1SIO, f8SIO, f32SIO. n=Setting value of SiBRG register 0016 to FF16.

• SMi6 bit = “0” (external clock) : Input from CLKi pin (Note 1)

Transmission/reception • Before transmission/reception can start, the following requirements must be met

start condition Write transmit data to the SiTRR register (Notes 2, 3)

• When SiC register's SMi4 bit = 0

The rising edge of the last transfer clock pulse (Note 4)

• When SMi4 = 1

The falling edge of the last transfer clock pulse (Note 4)

CLKi pin function I/O port, transfer clock input, transfer clock output

SOUTi pin function I/O port, transmit data output, high-impedance

SINi pin function I/O port, receive data input

Select function • LSB first or MSB first selection

Whether to start sending/receiving data beginning with bit 0 or beginning with bit 7

can be selected

• Function for setting an SOUTi initial value set function

When the SiC register's SMi6 bit = 0 (external clock), the SOUTi pin output level while

not transmitting can be selected.

• CLK polarity selection

Whether transmit data is output/input timing at the rising edge or falling edge of

transfer clock can be selected.

Note 1: To set the SiC register’s SMi6 bit to “0” (external clock), follow the procedure described below.

• If the SiC register’s SMi4 bit = 0, write transmit data to the SiTRR register while input on the CLKi pin is

high. The same applies when rewriting the SiC register’s SMi7 bit.

• If the SMi4 bit = 1, write transmit data to the SiTRR register while input on the CLKi pin is low. The same

applies when rewriting the SMi7 bit.

• Because shift operation continues as long as the transfer clock is supplied to the SI/Oi circuit, stop the

transfer clock after supplying eight pulses. If the SMi6 bit = 1 (internal clock), the transfer clock automatically

stops.

Note 2: Unlike UART0 to UART2, SI/Oi (i = 3 to 4) is not separated between the transfer register and buffer. There-

fore, do not write the next transmit data to the SiTRR register during transmission.

Note 3: When the SiC register’s SMi6 bit = 1 (internal clock), SOUTi retains the last data for a 1/2 transfer clock period

after completion of transfer and, thereafter, goes to a high-impedance state. However, if transmit data is

written to the SiTRR register during this period, SOUTi immediately goes to a high-impedance state, with the

data hold time thereby reduced.

Note 4: When the SiC register’s SMi6 bit = 1 (internal clock), the transfer clock stops in the high state if the SMi4 bit

= 0, or stops in the low state if the SMi4 bit = 1.

Table 1.17.1. SI/O3 and SI/O4 Specifications

Interrupt request

generation timing



(a) SI/Oi Operation Timing

Figure 1.17.3 shows the SI/Oi operation timing

D7D0 D1 D2 D3 D4 D5 D6

i= 3, 4

1.5 cycle (max)

SI/Oi internal clock

CLKi output

Signal written to the SiTRR register

SOUTi output

SINi input

SiIC registerIR bit

(Note 2)

Note 1: This diagram applies to the case where the SiC register bits are set as follows: SMi2=0 (SOUTi output), SMi3=1 (SOUTi output, CLKi function), SMi4=0 (transmit data output at the falling edge and receive data input at the rising edge of the transfer clock), SMi5=0 (LSB first) and SMi6=1 (internal clock)Note 2: When the SMi6 bit = 1 (internal clock), the SOUTi pin is placed in the high-impedance state after the transfer finishes.Note 3: If the SMi6 bit=0 (internal clock), the serial I/O starts sending or receiving data a maximum of 1.5 transfer clock cycles after writing to the SiTRR register.

"H""L"

"H""L"

"H""L"

"H""L"

"H""L"

"1""0"

(Note 3)

Figure 1.17.3. SI/Oi Operation Timing

(b) CLK Polarity Selection

The SiC register's SMi4 bit allows selection of the polarity of the transfer clock. Figure 1.17.4 shows

the polarity of the transfer clock.

Figure 1.17.4. Polarity of Transfer Clock

(2) When SiC register's SMi4 bit = “1”

(Note 3)

D1 D2 D3 D4 D5 D6 D7

D1 D2 D3 D4 D5 D6 D7

D0

D0

SINi

SOUTi

CLKi

(1) When SiC register's SMi4 bit = “0”

Note 1: This diagram applies to the case where the SiC register bits are set as follows: SMi5=0 (LSB first) and SMi6=1 (internal clock)Note 2: When the SMi6 bit=1 (internal clock), a high level is output from the CLKi pin if not transferring data.Note 3: When the SMi6 bit=1 (internal clock), a low level is output from the CLKi pin if not transferring data.

D1 D2 D3 D4 D5 D6 D7D0

D1 D2 D3 D4 D5 D6 D7D0

SINi

SOUTi

CLKi (Note 2)

i=3 and 4



(c) Functions for Setting an SOUTi Initial Value

If the SiC register’s SMi6 bit = 0 (external clock), the SOUTi pin output can be fixed high or low when not

transferring. Figure 1.17.5 shows the timing chart for setting an SOUTi initial value and how to set it.

Figure 1.17.5. SOUTi’s Initial Value Setting

Setting of the initial value of SOUTi output and starting of transmission/

reception

Set the SMi3 bit to “0” (SOUTi pin functions as an I/O port)

Write to the SiTRR register

Serial transmit/reception starts

Set the SMi7 bit to “1” (SOUTi initial value = “H”)

Set the SMi3 bit to “1” (SOUTi pin functions as SOUTi output)

“H” level is output from the SOUTi pin

Signal written to SiTRR register

SOUTi (internal)

SMi7 bit

SOUTi pin output

SMi3 bit

Setting the SOUTi initial value to “H”

Port selection switching(I/O port SOUTi)

D0

(i = 3, 4)

Initial value = “H” (Note 3)

Port output D0

(Example) When “H” selected for SOUTi initial value (Note 1)

Note 1: This diagram applies to the case where the SiC register bits are set as follows: SMi2=0 (SOUTi output), SMi5=0 (LSB first) and SMi6=0 (external clock)Note 2: SOUTi can only be initialized when input on the CLKi pin is in the high state if the SiC register’s SMi4 bit = 0 (transmit data output at the falling edge of the transfer clock) or in the low state if the SMi4 bit = 1 (transmit data output at the rising edge of the transfer clock).Note 3: If the SMi6 bit = 1 (internal clock) or if the SMi2 bit = 1 (SOUT output disabled), this output goes to the high-impedance state.

(Note 2)

M16C/6S Group Programmable I/O Ports


Programmable I/O PortsThe programmable input/output ports (hereafter referred to simply as “I/O ports”) consist of 55 lines P1, P4

to P9 (except P85). Each port can be set for input or output every line by using a direction register, and can

also be chosen to be or not be pulled high every 4 lines. P85 is an input-only port and does not have a pull-

up resistor. There is no external connections for port P1_0 to P1_4, P1_6 to P1_7, P4_0 to P4_7, P5_0 to

P5_7, P7_2, P7_5, P7_7, P8_2, P8_6 to P8_7, P9_3 to P9_7.

Figures 1.18.1 to 1.18.4 show the I/O ports. Figure 1.18.5 shows the I/O pins.

Each pin functions as an I/O port, a peripheral function input/output.

For details on how to set peripheral functions, refer to each functional description in this manual. If any pin

is used as a peripheral function input, set the direction bit for that pin to “0” (input mode). Any pin used as an

output pin for peripheral functions is directed for output no matter how the corresponding direction bit is set.

(1) Port Pi Direction Register (PDi Register, i = 1, 4 to 9)

Figure 1.18.6 shows the direction registers.

This register selects whether the I/O port is to be used for input or output. The bits in this register corre-

spond one for one to each port.

No direction register bit for P85 is available.

(2) Port Pi Register (Pi Register, i = 1, 4 to 9)

Figure 1.18.7 show the Pi registers.

Data input/output to and from external devices are accomplished by reading and writing to the Pi register.

The Pi register consists of a port latch to hold the input/output data and a circuit to read the pin status. For

ports set for input mode, the input level of the pin can be read by reading the corresponding Pi register,

and data can be written to the port latch by writing to the Pi register.

For ports set for output mode, the port latch can be read by reading the corresponding Pi register, and

data can be written to the port latch by writing to the Pi register. The data written to the port latch is output

from the pin. The bits in the Pi register correspond one for one to each port.

(3) Pull-up Control Register 0 to Pull-up Control Register 2 (PUR0 to PUR2 Registers)Figure 1.18.8 shows the PUR0 to PUR2 registers.

The PUR0 to PUR2 register bits can be used to select whether or not to pull the corresponding port high

in 4 bit units. The port chosen to be pulled high has a pull-up resistor connected to it when the direction bit

is set for input mode.

(4) Port Control Register

Figure 1.18.9 shows the port control register.

When the P1 register is read after setting the PCR register’s PCR0 bit to “1”, the corresponding port latch

can be read no matter how the PD1 register is set.



Figure 1.18.1. I/O Ports (1)

P40, P42, P56

P53, P54

P15

P60, P64, P73, P74, P76, P80, P81, P90, P92

Data bus

Direction register

IT800

Port latch

Data bus Port latch

IT800

Input to respective peripheral functions

Port P1 control register

Data bus Port latch

Pull-up selection

(Note 1)

Pull-up selection

Data bus Port latchOutput

"1"


(Note 1)

Direction register

Direction register

Note 1: symbolizes a parasitic diode. Make sure the input voltage on each port will not exceed Vcc.




P83, P84

(Note 1)

P91

Data bus

Pull-up selection

Direction register

Port latch

Data bus

Pull-up selection

Direction register

Port latch



(Note 1)

P61, P65"1"

OutputData bus

Direction register

Port latch

Pull-up selection

(Note 1)



Switching betweenCMOS andNch




P62, P66, P71

Data bus

Pull-up selection

Direction register

Port latch


(Note 1)

P70

Data bus

Direction register

Port latch


(Note 2)

Output

“1”

P85

Data bus

(Note 1)

P63, P67

Output

“1”

Data bus

Pull-up selection

Direction register

Port latch

(Note 1)

Switching between CMOS and Nch

Note 2: symbolizes a parasitic diode.


Switching between CMOS and Nch




Data busP95, P96

P82, P97, P41

Direction register

Port latchOutput

“1”

IT800

Testing signal

Data bus


Port latch

P10, P11 Data bus Port latch

IT800

Direction register

Direction register



Figure 1.18.5. I/O Pins

CNVSS

CNVSS signal input

RESETRESET signal input

(Note 2)

(Note 1)

(Note 1)

Note 1: symbolizes a parasitic diode. Make sure the input voltage on each port will not exceed Vcc.Note 2: A parasitic diode on the VCC side is added to the mask ROM version. Make sure the input voltage on each port will not exceed Vcc.



Figure 1.18.6. PD1, PD4 to PD9 Registers

Port Pi direction register (i=1, 4 to 7 and 9) (Note 1)

Symbol Address(Note 2)

After resetPD1 03E316 0016PD4 to PD7 03EA16, 03EB16, 03EE16, 03EF16 0016PD9 03F316 0016


b7 b6 b5 b4 b3 b2 b1 b0

PDi_0 Port Pi0 direction bit








0 : Input mode (Functions as an input port)1 : Output mode (Functions as an output port)

(i = 0 to 7 and 9 to 13)

Port P8 direction register

Symbol Address After resetPD8 03F216 00X000002


b7 b6 b5 b4 b3 b2 b1 b0

PD8_0 Port P80 direction bit




PD8_4 Port P84 direction bitNothing is assigned. In an attempt to write to this bit, write “0”. The value, if read, turns out to be indeterminate.





Note 1: Make sure the PD9 register is written to by the next instruction after setting the PRCR

Note 2: Set PD1_0 and PD1_1 bits to “0.” register’s PRC2 bit to “1” (write enabled).

RWRWRWRW

RW

RWRWRW

RW

RW

RWRWRWRW

RW

RW

(b5)



Port Pi register (i=1, 4 to 7 and 9) Symbol Address

(Note 2)After reset

P1 03E116 IndeterminateP4 to P7 03E816, 03E916, 03EC16, 03ED16 IndeterminateP9 03F116 Indeterminate


b7 b6 b5 b4 b3 b2 b1 b0

Pi_0 Port Pi0 bit

Pi_1 Port Pi1 bit

Pi_2 Port Pi2 bit

Pi_3 Port Pi3 bit

Pi_4 Port Pi4 bit

Pi_5 Port Pi5 bit

Pi_6 Port Pi6 bit

Pi_7 Port Pi7 bit

The pin level on any I/O port which is set for input mode can be read by reading the corresponding bit in this register. The pin level on any I/O port which is set for output mode can be controlled by writing to the corresponding bit in this register 0 : “L” level 1 : “H” level (Note 1)

(i = 0 to 7 and 9 to 13)

Port P8 register

Symbol Address After reset P8 03F016 Indeterminate


b7 b6 b5 b4 b3 b2 b1 b0

P8_0 Port P80 bit

P8_1 Port P81 bit

P8_2 Port P82 bit

P8_3 Port P83 bit

P8_4 Port P84 bit

P8_5 Port P85 bit

P8_6 Port P86 bit

P8_7 Port P87 bit

The pin level on any I/O port which is set for input mode can be read by reading the corresponding bit in this register. The pin level on any I/O port which is set for output mode can be controlled by writing to the corresponding bit in this register (except for P85)0 : “L” level1 : “H” level

Note 1: Since P70 is N-channel open drain ports, the data is high-impedance.

RWRWRWRWRW

RWRWRW

RWRWRW

RW

RWRW

RWRW

RO

Note 2: Set P1_0 and P1_1 bits to “0.”

Figure 1.18.7. P1, P4 to P9



Pull-up control register 0 (Note 1)

Symbol Address After reset PUR0 03FC16 0016

Bit name Function Bit symbol RW

b7 b6 b5 b4 b3 b2 b1 b0

PU03 P14 to P17 pull-up

Pull-up control register 1

Symbol Address After reset(Note 5) PUR1 03FD16 000000002 000000102

Bit name Function Bit symbol

b7 b6 b5 b4 b3 b2 b1 b0



PU16 P72 to P73 pull-up (Note 1)


Note 1: The P70 and P71 pins do not have pull-ups.Note 2: During memory extension and microprocessor modes, the pins are not pulled high although the contents of these bits can be modified.Note 3: The pin for which this bit is “1” (pulled high) and the direction bit is “0” (input mode) is pulled high.Note 4: If the PM01 to PM00 bits are set to “012” (memory expansion mode) or “112” (microprocessor mode) in a program during single-chip mode, the PU11 bit becomes “1”.Note 5: The values after hardware reset 1 and 2 are as follows: • 000000002 when input on CNVss pin is “L“ • 000000102 when input on CNVss pin is “H“ The values after software reset, watchdog timer reset and oscillation stop detection reset are as follows: • 000000002 when PM 01 to PM00 bits of PM0 register are “002“ (single-chip mode) • 000000102 when PM 01 to PM00 bits of PM0 register are “012“ (memory expansion mode) or “112“ (microprocessor mode)

Note 1: During memory extension and microprocessor modes, the pins are not pulled high although their corresponding register contents can be modified.

RW

RW

RWRWRWRW

Note 2: The pin for which this bit is “1” (pulled high) and the direction bit is “0” (input mode) is pulled high.

Pull-up control register 2

Symbol Address After reset PUR2 03FE16 0016


b7 b6 b5 b4 b3 b2 b1 b0


PU21 P84 to P87 pull-upPU22 P90 to P93 pull-up

Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be “0”.

0 : Not pulled high 1 : Pulled high (Note 1)

RWRWRW

RW

Note 1: The pin for which this bit is “1” (pulled high) and the direction bit is “0” (input mode) is pulled high.Note 2: The P85 pin does not have pull-up.

(Note 2)




(b7-b3)



Figure 1.18.8. PUR0 to PUR2 Registers



Figure 1.18.9. PCR Register

Port control register

Symbpl Address After reset PCR 03FF16 0016


b7 b6 b5 b4 b3 b2 b1 b0

PCR0 Port P1 control bit

Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be “0”.

RW

(b7-b1)

Operation performed when the P1 register is read 0: When the port is set for input,

the input levels of P10 to P17 pins are read. When set for output, the port latch is read.

1: The port latch is read regardless of whether the port is set for input or output.



Pin name Connection

Ports P1, P6 to P9(excluding P85)

XOUT (Note 1)

VSSA

VCCA

After setting for input mode, connect every pin to VSS via a resistor(pull-down); or after setting for output mode, leave these pins open. (2, 3, 4)

Open

Connect to VCC

Connect to VSS

P85 Connect via resistor to VCC (pull-up)

NOTES:

2. When setting the port for output mode and leave it open, be aware that the port remains in input mode until 1. With external clock input to XIN pin.

it is switched to output mode in a program after reset. For this reason, the voltage level on the pin becomes indeterminate, causing the power supply current to increase while the port remains in input mode. Furthermore, by considering a possibility that the contents of the direction registers could be changed by noise or noise-induced runaway, it is recommended that the contents of the direction registers be periodically reset in software, for the increased reliability of the program.

3. Make sure the unused pins are processed with the shortest possible wiring from the microcomputer pins (within 2 cm).

4. When the port P7_0 is set for output mode, make sure a low-level signal is output from the pin. The port P7_0 is N-channel open-drain output.

Table 1.18.1. Unassigned Pin Handling in Single-chip Mode (Excluding Analog Pins)



Figure 1.18.10. Unassigned Pins Handling (Excluding Analog Pins)

(Input mode) · ··

(Input mode)

(Output mode)

P85

XOUT

VCCA

VSSA

Microcomputer

VCC

VSS

In single-chip mode

Open

Open

···

(Note 2)Port P1, P6 to P9 (except for P85)

M16C/6S Group Electrical Characteristics


Table 1.19.1. Absolute Maximum Ratings

Electrical Characteristics

Note 1: Refer to Tables 1.1.5 and 1.1.6 Product code.

Operating ambient temperature

Parameter Unit

XIN

Input voltage

Analog supply voltage

Supply voltage

Output voltage

XOUT, TSVO

-0.3 to VCC+0.3

-0.3 to VCC1+0.3

Pd Power dissipation

Storage temperature

Rated valueV

V

V

Condition

VI

VCCA

VCC

Tstg

Topr

Symbol

mW

P60 to P67, P71, P73, P74, P76, P80 to P85,

P60 to P67, P71, P73, P74, P76, P80 to P84,

P90 to P92,

P90 to P92,

P70

P70

-0.3 to 6.5

V

V

RESET, CNVSS

VCC=VCCA

VCC=VCCA -0.3 to 4.2

V

-0.3 to 4.2

-65 to 150

500

-20 to 85/-40 to 85/-40 to 105 (Note 1)

-0.3 to 6.5

C

C



Table 1.19.2. Recommended Operating Conditions (Note 1)

3

.

6T

y

p

. M

a

x

. U

n

i

tP

a

r

a

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VC

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3

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3S

u

p

p

l

y

v

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l

t

a

g

e

M

i

n

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t

a

n

d

a

r

d

VC

C

A V

c

c VV0

0A

n

a

l

o

g

s

u

p

p

l

y

v

o

l

t

a

g

e

Supply voltage

VI

H

H

I

G

H

a

v

e

r

a

g

e

o

u

t

p

u

t

c

u

r

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n

t

m

A

m

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Vss

A V

s

s

V

V

0

.

2

VC

C

0

L

O

W

i

n

p

u

t

v

o

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a

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e

H

I

G

H

p

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a

k

o

u

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p

u

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c

u

r

r

e

n

t

H

I

G

H

i

n

p

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t

v

o

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t

a

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e

-

5

.

0

-

1

0

.

0

1

0

.

0

5

.

0

m

A

f (

XI

N)M

a

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n

c

l

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c

k

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p

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c

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f

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y(

N

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4

)

L

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W

a

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a

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o

u

t

p

u

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c

u

r

r

e

n

t

m

A

V

0

.

8

VC

C

6

.

5 V

VCC=3.0 to 3.6V

MHz

N

o

t

e

1

:

N

o

t

e

2

:

T

h

e

m

e

a

n

o

u

t

p

u

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c

u

r

r

e

n

t

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s

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a

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u

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w

i

t

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i

n

1

0

0

m

s

.N

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3

:

T

h

e

t

o

t

a

l

IO

L

(

p

e

a

k

)

f

o

r all ports must be 80mA max, the total IOH (peak) for all ports must be -40mA max.

0.8VCC VVC

C P60 to P67, P71, P73, P74, P76,

P80 to P84, P90 to P92

f (Ring) Ring oscillation frequency M

H

z1

C

P

U

o

p

e

r

a

t

i

o

n

c

l

o

c

k M

H

z

TSU(PLL) P

L

L

f

r

e

q

u

e

n

c

y

s

y

n

t

h

e

s

i

z

e

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s

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a

b

i

l

i

z

a

t

i

o

n

w

a

i

t

t

i

m

e VCC=3.0V 50

m

s

Referenced to VCC = 3.0 to 3.6V at Topr = -20 to 85 °C/-40 to 85 °C/-40 to 105 °C unless otherwise specified.

3 0

.

lm oyS

b

P70

XIN, RESET, CNVSS

XIN, RESET, CNVSS

VI

L

P60 to P67, P70, P71, P73, P74, P76, P80 to P84, P90 to P92

P60 to P67, P70, P71, P73, P74, P76, P80 to P84, P90 to P92, TS

P60 to P67, P70, P71, P73, P74, P76, P80 to P84, P90 to P92, TS

P60 to P67, P71, P73, P74, P76,P80 to P84, P90 to P92, TS

P60 to P67, P71, P73, P74, P76,P80 to P84, P90 to P92, TS

L

O

W

p

e

a

k

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t

p

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5.12

15.36f (

B

C

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K

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A

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a

l

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s

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p

p

l

y

v

o

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IO

H

(

p

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a

k

)

IOH (avg)

IO

L

(

p

e

a

k

)

IO

L

(

a

v

g

)



Table 1.19.3. Flash Memory Version Electrical Characteristics (Note 1)

Word program time (Vcc=3.3V, Topr=25°C)

Block erase time

75 600 µs

ParameterStandard

Min. Typ.(Note 2)

MaxUnitSymbol

––

0.4 9 s

0.7 9 s

9 s1.2

8Kbyte block

16Kbyte block

32Kbyte block

– Erase/Write cycle (Note 3) cycle

– Data retention time (Note 5) year20

tPS Flash Memory Circuit Stabilization Wait Time µs15

100 (Note 4)

Table 1.19.4. Flash Memory Version Program/Erase Voltage and Read Operation Voltage Characteristics

(at Topr = 0 to 60oC)

Flash program, erase voltage Flash read operation voltage

VCC = 3.3 V ± 0.3 V VCC = 3.0 to 3.6 V

Note 1: When not otherwise specified, Vcc = 3.0 to 3.6V; Topr = 0 to 60 °C.

Note 2: VCC = 3.3V; Topr = 25 °C.

Note 3: Program and Erase Endurance refers to the number of times a block erase can be performed. If the program and erase endurance is n (n=100),

each block can be erased n times. For example, if a 8Kbytes block 0 is erased after writing 1 word data 4096 times, each to a different address, this counts as

one program and erase endurance. Data cannot be written to the same address more than once without erasing the block. (Rewrite prohibited)

Note 4: Maximum number of E/W cycles for which opration is guaranteed.

Note 5: Topr = 55°C.

Note 6: Customers desiring E/W failure rate information should contact their Renesas technical support representative.



Interrupt for stop moderelease

CPU clock

td(R-S)

Table 1.19.5. Power Supply Circuit Timing Characteristics

S

y

m

b

o

l S

t

a

n

d

a

r

dT

y

p

. U

n

i

tM

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c

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M

i

n

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a

x

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a

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2

VC

C

=

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0

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6

V 1

5

0

5

0

t d

(

R

-

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) S

T

O

P

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l

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a

s

e

t

i

m

e

t d

(

M

-

L

) T

i

m

e

f

o

r

i

n

t

e

r

n

a

l

p

o

w

e

r

s

u

p

p

l

y

s

t

a

b

i

l

i

z

a

t

i

o

n

w

h

e

n

m

a

i

n

c

l

o

c

k

o

s

c

i

l

l

a

t

i

o

n

s

t

a

r

t

s

m

st d

(

P

-

R

) T

i

m

e

f

o

r

i

n

t

e

r

n

a

l

p

o

w

e

r

s

u

p

p

l

y

s

t

a

b

i

l

i

z

a

t

i

o

n

d

u

r

i

n

g

p

o

w

e

r

i

n

g

-

o

n

s

s



Table 1.19.6. Electrical Characteristics (Note)

Symbol Parameter Measuring conditionStandard

Min. Typ. Max.Unit

VOH

HIGH output voltageVOH

VOL

VOL

HIGH outputvoltage

LOW outputvoltage

V

VXOUT

LOW output voltage XOUT

V

V0.5

VCC-0.5 IOH= -1mA

IOH= -0.1mA

IOL=1mA

IOL=0.1mA

Hysteresis

Hysteresis

HIGH inputcurrent

LOW inputcurrent

Pull-upresistance

Feedback resistance

IIH

IIL

VT+-VT-

VT+-VT-

0.2 0.8 V

0.2 1.8 V

4.0

RESET

XIN, RESET, CNVssVI=3V

VI=0V -4.0

RfXIN XIN 3.0 M

RPULLUP

160 kVI=0V 66 500

CLK0 to CLK4, TA4OUT,

TA0IN, TA1IN, TA4IN,

CTS0 to CTS2, SCL, SDA,

INT1 to INT3,

RxD0 to RxD2, SIN3

XIN, RESET, CNVss

VCC

VCC

0.5

(0.7)

P60 to P67, P71, P73, P74, P76, P80 to P84, P90 to P92, TS

P60 to P67, P71, P73, P74, P76,



P60 to P67, P71, P73, P74, P76, P80 to P84, P90 to P92

P80 to P84, P90 to P92, TS

Note : Referenced to VCC = 3.0 to 3.6V, VSS = 0V at Topr = -20 to 85 °C/-40 to 85 °C/-40 to 105 °C, f(BCLK) = 15.36 MHz unless otherwise specified.

VCC-0.5

A

A



Table 1.19.7. Electrical Characteristics (2) (Note 1)

S

y

m

b

o

l S

t

a

n

d

a

r

dT

y

p

. U

n

i

tMeasuring condition

M

i

n

. M

a

x

.P

a

r

a

m

e

t

e

r

I n

s

i

n

g

l

e

-

c

h

i

p

m

o

d

e

,

t

h

e

o

u

t

p

u

t

p

i

n

s

a

r

e

o

p

e

n

a

n

d

o

t

h

e

r

p

i

n

s

a

r

e

VS

S

70

TBD

TBD

N

o

d

i

v

i

s

i

o

n m

Af (

B

C

L

K

)

=

1

5.36

M

H

z

,

F

l

a

s

h

m

e

m

o

r

y

IC

CP

o

w

e

r

s

u

p

p

l

y

c

u

r

r

e

n

t(

VC

C=

2

.

7

t

o

3

.

6

V

)V

c

c1=

3

.

0

V m

AF

l

a

s

h

m

e

m

o

r

y f (

B

C

L

K

)

=

10

M

H

z

,

P

r

o

g

r

a

m

V

c

c1=

3

.

0

Vm

AF

l

a

s

h

m

e

m

o

r

y f (

B

C

L

K

)

=

E

r

a

s

e10MHz,

Note : Referenced to VCC = 3.0 to 3.6V, VSS = 0V at Topr = -20 to 85 °C/-40 to 85 °C/-40 to 105 °C, f(BCLK) = 15.36 MHz unless otherwise specified.

95



Timing Requirements

(VCC = 3V, VSS = 0V, at Topr = – 20 to 85oC/– 40 to 85oC/– 40 to 105oC unless otherwise specified)

Table 1.19.8. External Clock Input

Max.

External clock rise time nstr

Min.External clock input cycle timeExternal clock input HIGH pulse widthExternal clock input LOW pulse width

External clock fall time

ns

ns

ns

ns

tc

tw(H)

tw(L)

tf

ParameterSymbol UnitStandard

195.3

80

80

1818



Timing Requirements


Table 1.19.10. Timer A Input (Gating Input in Timer Mode)

Table 1.19.11. Timer A Input (External Trigger Input in One-shot Timer Mode)

Table 1.19.12. Timer A Input (External Trigger Input in Pulse Width Modulation Mode)

Table 1.19.13. Timer A Input (Counter Increment/decrement Input in Event Counter Mode)

Table 1.19.9. Timer A Input (Counter Input in Event Counter Mode)

Table 1.19.14. Timer A Input (Two-phase Pulse Input in Event Counter Mode)

StandardMax.

nsTAiIN input LOW pulse widthtw(TAL)

Min.ns

ns

Unit

TAiIN input HIGH pulse widthtw(TAH)

ParameterSymbol

tc(TA) TAiIN input cycle time

60

150

60

Standard

Max.Min.

ns

ns

ns

Unit

TAiIN input cycle time

TAiIN input HIGH pulse widthTAiIN input LOW pulse width

tc(TA)

tw(TAH)

tw(TAL)

Symbol Parameter

600

300

300

Standard

Max.Min.ns

ns

ns

Unit


TAiIN input HIGH pulse widthTAiIN input LOW pulse width

tc(TA)

tw(TAH)

tw(TAL)

Symbol Parameter

300

150

150

StandardMax.Min.

ns

ns

Unit

tw(TAH)

tw(TAL)

Symbol Parameter

TAiIN input HIGH pulse width

TAiIN input LOW pulse width

150

150

StandardMax.Min.

ns

ns

ns

Unit

ns

ns

Symbol Parameter

TAiOUT input cycle time

TAiOUT input HIGH pulse width

TAiOUT input LOW pulse width

TAiOUT input setup timeTAiOUT input hold time

tc(UP)

tw(UPH)

tw(UPL)

tsu(UP-TIN)

th(TIN-UP)

3000

1500

1500

600

600

StandardMax.Min.

sns

ns

UnitSymbol Parameter


TAiOUT input setup time

TAiIN input setup time

tc(TA)

tsu(TAIN-TAOUT)

tsu(TAOUT-TAIN)

2

500

500



Table 1.19.15. Serial I/O

_______

Table 1.19.16. External Interrupt INTi Input

ns

ns

ns

ns

ns

ns

ns

Standard

Max.Min.ns

ns

tw(INH)

tw(INL)

Symbol Parameter Unit

INTi input LOW pulse width

INTi input HIGH pulse width

Standard

Max.Min.

CLKi input cycle time

CLKi input HIGH pulse width

CLKi input LOW pulse width

tc(CK)

tw(CKH)

tw(CKL)

ParameterSymbol Unit

td(C-Q)

tsu(D-C)

th(C-Q) TxDi hold time

RxDi input setup time

TxDi output delay time

th(C-D) RxDi input hold time

380

380

300

150

150

0

100

90

160

Timing Requirements




Figure 1.19.1. Timing Diagram (1)

TAiIN input

TAiOUT input

During event counter mode

tc(TA)

tw(TAH)

tw(TAL)

tc(UP)

tw(UPH)

tw(UPL)

th(TIN–UP) tsu(UP–TIN)TAiIN input(When count on falling edge is selected)

TAiIN input(When count on rising edge is selected)

TAiOUT input(Up/down input)

tc(TA)

tsu(TAIN-TAOUT)

tsu(TAOUT-TAIN)

tsu(TAOUT-TAIN)

Two-phase pulse input in event counter mode

TAiIN input

TAiOUT input

tsu(TAIN-TAOUT)



Figure 1.19.2. Timing Diagram (2)

tsu(D–C)

CLKi

TxDi

RxDi

tc(CK)

tw(CKH)

tw(CKL)

tw(INL)

tw(INH)

td(C–Q) th(C–D)

th(C–Q)

INTi input

M16C/6S Group Flash Memory Version


Table 1.20.1. Flash Memory Version Specifications

Flash Memory VersionFlash Memory Performance

The flash memory version has three modes—CPU rewrite, standard serial input/output, and parallel input/

output modes—in which its internal flash memory can be operated on.

Note: About the parallel programmer of exclusive use, there is no schedule of development at the present time.

Table 1.20.1 shows the outline performance of flash memory version (see Table 1.1.1 for the items not

listed in Table 1.20.1.).

Table 1.20.2. Flash Memory Rewrite Modes Overview

Flash memory CPU rewrite mode Standard serial I/O moderewrite mode

Function

Areas which User ROM area User ROM areacan be rewritten

Operation Single chip mode Boot modemode Memory expansion mode

(EW0 mode)Boot mode (EW0 mode)

ROM None Serial programmerprogrammer

The user ROM area is rewrit-ten by executing softwarecommands from the CPU.EW0 mode:

Can be rewritten in anyarea other than the flashmemory

EW1 mode:Can be rewritten in theflash memory

The user ROM area is rewrit-ten by using a dedicated se-rial programmer.Standard serial I/O mode 1:

Clock sync serial I/OStandard serial I/O mode 2:

UART

Item

Flash memory operating mode

Erase block

Program method

Erase method

Program, erase control method

Protect method

Number of commands

Program/EraseEndurance(Note)

ROM code protection

Specification

2 modes (CPU rewrite, standard serial I/O)

See Figure 1.20.1 Flash Memory Block Diagram

In units of word

Block erase

Program and erase controlled by software command

The block 0 and block 1 are write protected by bit FMR02.

5 commands

100 times

Standard serial I/O mode is supported.

Data Retention 20 years (Topr = 55°C)

Block 0 to 4 (program area)

Note: Program and erase endurance definitionProgram and erase endurance are the erase endurance of each block. If the program and erase endurance are n times (n=100), each block can be erased n times. For example, if a 8-Kbyte block 0 is erased after writing 1 word data 4096 times, each to different addresses, this is counted as one program and erasure. However, data cannot be written to the same address more than once without erasing the block. (Rewrite disabled)



1. Memory MapThe ROM in the flash memory version is separated between a user ROM area and a boot ROM area.

Figures 1.20.1 and 1.20.2 show the block diagram of flash memory.

The user ROM area is divided into several blocks, so that memory can be erased one block at a time. The

user ROM area can be rewritten in all of CPU rewrite, standard serial input/output, and parallel input/output

modes.

The boot ROM area is reserved. The rewrite control program for standard serial I/O mode is stored in this

area before shipment, so that the area cannot be rewritten.

Figure 1.20.1. Flash Memory Block Diagram (ROM Capacity 64K bytes)

4K bytes0FF000160FFFFF16

Boot ROM area (Reserved)

Note 1: To specify a block, use an even address in that block.Note 2: Blocks 0 and 1 can be rewritten if FMR02 of FMR0 register is set to "1" (only in case of CPU rewriting mode.)

0FFFFF16

Block 0 : 8K bytes

Block 1 : 8K bytes

0FE00016

0FC00016

0FDFFF16

Block 2 : 16K bytes

0FBFFF16

0F800016

Block 3 : 32K bytes

0F000016

0F7FFF16

User ROM area



Figure 1.20.2. Flash Memory Block Diagram (ROM Capacity 96K bytes)

4K bytes0FF000160FFFFF16

Boot ROM area (Reserved)

Note 1: To specify a block, use an even address in that block.Note 2: Blocks 0 and 1 can be rewritten if FMR02 of FMR0 register is set to "1" (only in case of CPU rewriting mode.)

0FFFFF16

Block 0 : 8K bytes

Block 1 : 8K bytes

0FE00016

0FC00016

0FDFFF16

Block 2 : 16K bytes

0FBFFF16

0F800016

Block 3 : 32K bytes

0F000016

0EFFFF16

Block 4 : 32K bytes

0E800016

0F7FFF16

User ROM area



Boot ModeAfter a hardware reset which is performed by applying a high-level signal to the CNVSS and P15 pins, the

microcomputer is placed in boot mode, thereby executing the program in the boot ROM area.

The boot ROM area contains a standard serial input/output mode based rewrite control program which was

stored in it when shipped from the factory.

Functions To Prevent Flash Memory from RewritingTo prevent the flash memory from being read or rewritten easily, parallel input/output mode has a ROM

code protect and standard serial input/output mode has an ID code check function.

• ROM Code Protect FunctionThe ROM code protect function inhibits the flash memory from being read or rewritten during parallel

input/output mode. Figure 1.20.3 shows the ROMCP register.

The ROMCP register is located in the user ROM area. The ROMCP1 bit consists of two bits. The ROM

code protect function is enabled by clearing one or both of two ROMCP1 bits to “0” when the ROMCR bits

are not ‘002,’ with the flash memory thereby protected against reading or rewriting. Conversely, when the

ROMCR bits are ‘002’ (ROM code protect removed), the flash memory can be read or rewritten. Once the

ROM code protect function is enabled, the ROMCR bits cannot be changed during parallel input/output

mode. Therefore, use standard serial input/output or other modes to rewrite the flash memory.

• ID Code Check Function

Use this function in standard serial input/output mode. Unless the flash memory is blank, the ID codes

sent from the programmer and the ID codes written in the flash memory are compared to see if they

match. If the ID codes do not match, the commands sent from the programmer are not accepted. The ID

code consists of 8-bit data, the areas of which, beginning with the first byte, are 0FFFDF16, 0FFFE316,

0FFFEB16, 0FFFEF16, 0FFFF316, 0FFFF716, and 0FFFFB16. Prepare a program in which the ID codes

are preset at these addresses and write it in the flash memory.



Figure 1.20.3. ROMCP Register

Figure 1.20.4. Address for ID Code Stored

Symbol Address Value when shipped ROMCP 0FFFFF16 FF16 (Note 4)

ROM code protect control address


b7 b6 b5 b4 b3 b2 b1 b0

00: Removes protect01: 10: 11:

00: 01: 10: 11: Protect disabled

ROM code protect reset bit (Note 2, Note 4)

ROM code protect level 1 set bit (Note 1, Note 3, Note 4)

ROMCR

ROMCP1

b5 b4

b7 b6

11

Reserved bit Set this bit to “1”




Enables ROOMCP1 bit

Protect enabled

Note 1: If the ROMCR bits are set to other than ‘002’ and the ROMCP1 bits are set to other than ‘112’ (ROM code protect enabled), the flash memory is disabled against reading and rewriting in parallel input/output mode.

Note 2: If the ROMCR bits are set to ‘002’ when the ROMCR bits are other than ‘002’ and the ROMCP1 bits are other than ‘112,’ ROM code protect level 1 is removed. However, because the ROMCR bits cannot be modified during parallel input/output mode, they need to be modified in standard serial input/output or other modes.

Note 3: The ROMCP1 bits are effective when the ROMCR bits are ‘012,’ ‘102,’ or ‘112.’Note 4: Once any of these bits is cleared to “0”, it cannot be set back to “1”. If a memory block that

contains the ROMCP register is erased, the ROMCP register is set to ‘FF16.’

11

RW

RW

RW

RW

RW

RW

RW

RW

RW

Reset vector

Watchdog timer vector

Single step vector

Address match vector

BRK instruction vector

Overflow vector

Undefined instruction vector

ID7

ID6

ID5

ID4

ID3

ID2

ID1

DBC vector

Reserved

0FFFFF16 to 0FFFFC16

0FFFFB16 to 0FFFF816

0FFFF716 to 0FFFF416

0FFFF316 to 0FFFF016

0FFFEF16 to 0FFFEC16

0FFFEB16 to 0FFFE816

0FFFE716 to 0FFFE416

0FFFE316 to 0FFFE016

0FFFDF16 to 0FFFDC16

4 bytes

Address

ROMCP



Table 1.21.1. EW0 Mode and EW1 Mode

Item EW0 mode EW1 modeOperation mode • Single chip mode Single chip modeAreas in which a • User ROM area User ROM arearewrite controlprogram can be locatedAreas in which a Must be transferred to any area other Can be executed directly in the userrewrite control than the flash memory (e.g., RAM) ROM areaprogram can be executed before being executedAreas which can be User ROM area User ROM arearewritten However, this does not include the area

in which a rewrite control programexists

Software command None • Program, Block Erase commandlimitations Cannot be executed on any block in

which a rewrite control program exists• Read Status Register commandCannot be executed

Modes after Program or Read Status Register mode Read Array modeEraseCPU status during Auto Operating Hold state (I/O ports retain the state inWrite and Auto Erase which they were before the command

was executed)(Note)

Flash memory status • Read the FMR0 register's FMR00, Read the FMR0 register's FMR00,detection FMR06, and FMR07 bits in a FMR06, and FMR07 bits in a program

program• Execute the Read Status Registercommand to read the statusregister's SR7, SR5, and SR4 flags.

_______

Note: Make sure no interrupts (except NMI and watchdog timer interrupts) and DMA transfers will occur.

CPU Rewrite ModeIn CPU rewrite mode, the user ROM area can be rewritten by executing software commands from the CPU.

Therefore, the user ROM area can be rewritten directly while the microcomputer is mounted on-board

without having to use a ROM programmer, etc.

Make sure the Program and the Block Erase commands are executed only on each block in the user ROM

area.

During CPU rewrite mode, the user ROM area be operated on in either Erase Write 0 (EW0) mode or Erase

Write 1 (EW1) mode. Table 1.21.1 lists the differences between Erase Write 0 (EW0) and Erase Write 1

(EW1) modes.



• EW0 ModeThe microcomputer is placed in CPU rewrite mode by setting the FMR0 register’s FMR01 bit to “1” (CPU

rewrite mode enabled), ready to accept commands. In this case, because the FMR1 register’s FMR11 bit

= 0, EW0 mode is selected. The FMR01 bit can be set to “1” by writing “0” and then “1” in succession.

Use software commands to control program and erase operations. Read the FMR0 register or status

register to check the status of program or erase operation at completion.

• EW1 Mode

EW1 mode is selected by setting FMR11 bit to “1” (by writing “0” and then “1” in succession) after setting

the FMR01 bit to “1” (by writing “0” and then “1” in succession).

Read the FMR0 register to check the status of program or erase operation at completion. The status

register cannot be read during EW1 mode.

When an erase/program operation is initiated the CPU halts all program execution until the operation is

completed.



Figure 1.21.1 shows the FMR0 and FMR1 registers.

FMR00 Bit

This bit indicates the operating status of the flash memory. The bit is “0” when the Program or Erase is

running; otherwise, the bit is “1”.

FMR01 BitThe microcomputer is made ready to accept commands by setting the FMR01 bit to “1” (CPU rewrite

mode).

FMR02 BitWhen FMR02 bit is “0” (rewriting is disable), block 0 and block 1 do not receive the command of a

program and block erase.

FMSTP BitThis bit is provided for initializing the flash memory control circuits, as well as for reducing the amount of

current consumed in the flash memory. The internal flash memory is disabled against access by setting

the FMSTP bit to “1”. Therefore, the FMSTP bit must be written to by a program in other than the flash

memory.

In the following cases, set the FMSTP bit to “1”:

• When flash memory access resulted in an error while erasing or programming in EW0 mode (FMR00

bit not reset to “1” (ready))

FMR06 Bit

This is a read-only bit indicating the status of auto program operation. The bit is set to “1” when a program

error occurs; otherwise, it is cleared to “0”. For details, refer to the description of the full status check.

FMR07 BitThis is a read-only bit indicating the status of auto erase operation. The bit is set to “1” when an erase

error occurs; otherwise, it is cleared to “0”. For details, refer to the description of the full status check.

Figure 1.21.2 and 1.21.3 show the setting and resetting of EW0 mode and EW1 mode, respectively.

FMR11 BitSetting this bit to “1” places the microcomputer in EW1 mode.



Flash memory control register 0 Symbol Address After reset FMR0 01B716 XX0000012

b7 b6 b5 b4 b3 b2 b1 b0

FMR00

Bit symbol Bit name Function RW

0: Busy (being written or erased)1: Ready

CPU rewrite mode select bit (Note 1)

0: Disables CPU rewrite mode 1: Enables CPU rewrite mode

FMR01

Lock bit disable select bit (Note 2)

0: Enables lock bit1: Disables lock bit

Flash memory stop bit (Note 3, Note 5)

FMR02

FMSTP

00

RY/BY status flag

Reserved bit Must always be set to “0”

0: Terminated normally1: Terminated in error

Program status flag (Note 4)FMR06

0: Terminated normally1: Terminated in error

Erase status flag (Note 4)FMR07

Flash memory control register 1 Symbol Address After reset FMR1 01B516 0X00XX0X2

b7 b6 b5 b4 b3 b2 b1 b0

Bit symbol Bit name Function

EW1 mode select bit (Note)

0: EW0 mode 1: EW1 mode

FMR11

0


Reserved bit The value in this bit when read is indeterminate.


000

RW

RW

RW

RW

RO

RO

RO

RW

RO

RW

RW

RW

(b0)

(b5-b4)

(b7)

(b5-b4)

0: Enables flash memory operation1: Stops flash memory operation (placed in low power mode, flash memory initialized)

Note 1: To set this bit to “1”, write “0” and then “1” in succession. Make sure no interrupts or DMA transfers will occur before writing “1” after writing “0”.

Also, while in EW0 mode, write to this bit from

a program in other than the flash memory. Note 2: To set this bit to “1”, write “0” and then “1” in succession when the FMR01 bit = 1. Make sure no

interrupts or no DMA transfers will occur before writing “1” after writing “0”.Note 3: Write to this bit from a program in other than the flash memory. Note 4: This flag is cleared to “0” by executing the Clear Status command.Note 5: Effective when the FMR01 bit = 1 (CPU rewrite mode). If the FMR01 bit = 0, although the FMR03 bit

can be set to “1” by writing “1” in a program, the flash memory is neither placed in low power mode nor initialized.

Reserved bit The value in this bit when read is indeterminate.(b3-b2) RO

Note : To set this bit to “1”, write “0” and then “1” in succession when the FMR01 bit = 1. Make sure no interrupts or no DMA transfers will occur before writing “1” after writing “0”.

The FMR01 and FMR11 bits both are cleared to “0” by setting the FMR01 bit to “0”.

Nothing is assigned.When write, set to “0”. When read, their contents are indeterminate.(b6)

Figure 1.21.1. FIDR Register and FMR0 and FMR1 Registers



Execute the Read Array command

Single-chip mode

Set CM0, CM1, and PM1 registers (Note1) Execute software commands

Jump to the rewrite control program which has been transferred to any area other than the flash memory (The subsequent processing is executed by the rewrite control program in any area other than the flash memory)

Transfer a CPU rewrite mode based rewrite control program to any area other than the flash memory

Write “0” to the FMR01 bit(CPU rewrite mode disabled)

Set the FMR01 bit by writing “0” and then “1” (CPU rewrite mode enabled) (Note 2)

EW0 mode operation procedure

Rewrite control program

Jump to a specified address in the flash memory

Note 1: Select 10 MHz or less for CPU clock using the CM0 register’s CM06 bit and CM1 register’s CM17 to 6 bits. Also, set the PM1 register’s PM17 bit to “1” (with wait state).

Note 2: To set the FMR01 bit to “1”, write “0” and then “1” in succession. Make sure no interrupts or no DMA transfers will occur before writing “1” after writing “0”.

Write to the FMR01 bit from a program in other than the flash memory. Note 3: Disables the CPU rewrite mode after executing the Read Array command.

Figure 1.21.2. Setting and Resetting of EW0 Mode



Figure 1.21.3. Setting and Resetting of EW1 Mode

Single-chip mode

Set CM0, CM1, and PM1 registers (Note 1)

Set the FMR01 bit by writing “0” and then “1” (CPU rewrite mode enabled) Set the FMR11 bit by writing “0” and then “1” (EW1 mode) (Note 2)

Program in ROM

EW1 mode operation procedure

Execute software commands

Write “0” to the FMR01 bit(CPU rewrite mode disabled)

Note 1: Select 10 MHz or less for CPU clock using the CM0 register’s CM06 bit and CM1 register’s CM17 to 6 bits. Also, set the PM1 register’s PM17 bit to “1” (with wait state).

Note 2: To set the FMR01 bit to “1”, write “0” and then “1” in succession. Make sure no interrupts or no DMA transfers will occur before writing “1” after writing “0”.

Write to the FMR01 bit from a program in other than the flash memory. Also write only when the NMI pin is “H” level.



Precautions on CPU Rewrite ModeDescribed below are the precautions to be observed when rewriting the flash memory in CPU rewrite mode.

(1) Operation Speed

Before entering CPU rewrite mode (EW0 or EW1 mode), select 10 MHz or less for BCLK using the

CM06 bit in the CM0 register and the CM17 to CM16 bits in the CM1 register. Also, set the PM17 bit in

the PM1 register to “1” (with wait state).

(2) Instructions to Prevent from Using

The following instructions cannot be used in EW0 mode because the flash memory’s internal data is

referenced: UND instruction, INTO instruction, JMPS instruction, JSRS instruction, and BRK instruc-

tion

(3) Interrupts

EW0 Mode

• Any interrupt which has a vector in the variable vector table can be used providing that its vector is

transferred into the RAM area._______

• The NMI and watchdog timer interrupts can be used because the FMR0 register and FMR1 regis-

ter are initialized when one of those interrupts occurs. The jump addresses for those interrupt

service routines should be set in the fixed vector table._______

Because the rewrite operation is halted when a NMI or watchdog timer interrupt occurs, the rewrite

program must be executed again after exiting the interrupt service routine.

• The address match interrupt cannot be used because the flash memory’s internal data is refer-

enced.

EW1 Mode

• Make sure that any interrupt which has a vector in the variable vector table or address match

interrupt will not be accepted during the auto program or auto erase period.

• Avoid using watchdog timer interrupts.

• The WDT interrupt can be used because the FMR0 register and FMR1 register are initialized when

this interrupt occurs. The jump address for the interrupt service routine should be set in the fixed

vector table.

Because the rewrite operation is halted when a WDT interrupt occurs, the rewrite program must be

executed again after exiting the interrupt service routine.

(4) How to Access

To set the FMR01, FMR02, or FMR11 bit to “1”, write “0” and then “1” in succession. This is necessary

to ensure that no interrupts or DMA transfers will occur before writing “1” after writing “0”.

(5) Writing in the User ROM Space

EW0 Mode

• If the power supply voltage drops while rewriting any block in which the rewrite control program is

stored, a problem may occur that the rewrite control program is not correctly rewritten and, conse-

quently, the flash memory becomes unable to be rewritten thereafter. In this case, standard serial

I/O or parallel I/O mode should be used.

EW1 Mode

• Avoid rewriting any block in which the rewrite control program is stored.



(6) DMA Transfer

In EW1 mode, make sure that no DMA transfers will occur while the FMR0 register’s FMR00 bit = 0

(during the auto program or auto erase period).

(7) Writing Command and Data

Write the command code and data at even addresses.

(8) Wait Mode

When shifting to wait mode, set the FMR01 bit to “0” (CPU rewrite mode disabled) before executing

the WAIT instruction.

(9) Stop Mode

When shifting to stop mode, the following settings are required:

• Set the FMR01 bit to “0” (CPU rewrite mode disabled) and disable DMA transfers before setting the

CM10 bit to “1” (stop mode).

• Execute the JMP.B instruction subsequent to the instruction which sets the CM10 bit to “1” (stop

mode)

Example program BSET 0, CM1 ; Stop mode

JMP.B L1

L1:

Program after returning from stop mode



Software CommandsSoftware commands are described below. The command code and data must be read and written in 16-

bit units, to and from even addresses in the user ROM area. When writing command code, the 8 high-

order bits (D1t–D8) are ignored.

Table 1.21.2. Software Commands

Read Array Command (FF16)This command reads the flash memory.

Writing ‘xxFF16’ in the first bus cycle places the microcomputer in read array mode. Enter the read

address in the next or subsequent bus cycles, and the content of the specified address can be read in

16-bit units.

Because the microcomputer remains in read array mode until another command is written, the con-

tents of multiple addresses can be read in succession.

However, when you use Read array command immediately after a program command, please read

data in the following procedure.

(1) FF16, FF16, FF16, and FF16 are written to 4 arbitrary continuous addresses.

(2) The head address of (1) is specified in Read array mode.

(3) (2) is repeated until the read value and FFFF16 are in agreement.

(4) The head address +2 of (1) is specified.

(5) (4) is repeated until the read value and FFFF16 are in agreement.

(6) Arbitrary addresses are specified.

Read Status Register Command (7016)This command reads the status register.

Write ‘xx7016’ in the first bus cycle, and the status register can be read in the second bus cycle. (Refer

to “Status Register.”) When reading the status register too, specify an even address in the user ROM

area.

Do not execute this command in EW1 mode.

Command

Program

Clear status register

Read array

Read status register

First bus cycle Second bus cycle

Block erase

Write

Write

Write

Write

Write

Mode

Read

Write

Write

Mode

X

WA

BA

Address

SRD

WD

xxD016

Data(D0 to D7)

xxFF16

xx7016

xx5016

xx4016

xx2016

Data(D0 to D7)

X

X

X

WA

X

Address

SRD: Status register data (D7 to D0)WA: Write address (Make sure the address value specified in the first bus cycle is the same even address as the write address specified in the second bus cycle.)WD: Write data (16 bits)BA: Uppermost block address (even address, however)X: Any even address in the user ROM areax: High-order 8 bits of command code (ignored)



Start

Program completed

YES

NO

Note: Write the command code and data at even number.

Write the command code ‘xx4016’ to the write address

Write data to the write address

FMR00=1?

Full status check

Figure 1.21.4. Program Command

Clear Status Register Command (5016)This command clears the status register to “0”.

Write ‘xx5016’ in the first bus cycle, and the FMR06 to FMR07 bits in the FMR0 register and SR4 to

SR5 in the status register will be cleared to “0”.

Program Command (4016)

This command writes data to the flash memory in 1 word (2 byte) units.

Write ‘xx4016’ in the first bus cycle and write data to the write address in the second bus cycle, and an

auto program operation (data program and verify) will start. Make sure the address value specified in

the first bus cycle is the same even address as the write address specified in the second bus cycle.

Check the FMR00 bit in the FMR0 register to see if auto programming has finished. The FMR00 bit is

“0” during auto programming and set to “1” when auto programming is completed.

Check the FMR06 bit in the FMR0 register after auto programming has finished, and the result of auto

programming can be known. (Refer to “Full Status Check.”)

Writing over already programmed addresses is inhibited.

Moreover, when FMR02 bit of FMR0 register is “0” (rewriting is disable), the program command to

block 0 and block 1 is not received. Just behind a program command, when you execute commands

other than a program command, please make it the address value which was specified by the 2nd bus

cycle of a program command and which writes in and specifies the same address as an address by

the 1st bus cycle of the following command.

In EW1 mode, do not execute this command on any address at which the rewrite control program is

located.

In EW0 mode, the microcomputer goes to read status register mode at the same time auto program-

ming starts, making it possible to read the status register. The status register bit 7 (SR7) is cleared to

“0” at the same time auto programming starts, and set back to “1” when auto programming finishes. In

this case, the microcomputer remains in read status register mode until a read command is written

next. The result of auto programming can be known by reading the status register after auto program-

ming has finished.



Write ‘xxD016’ to the uppermost block address

Start

Block erase completed

YES

NO

Note: Write the command code and data at even number.

Write the command code ‘xx2016’

FMR00=1?

Full status check

Figure 1.21.5. Block Erase Command

Block Erase

Write ‘xx2016’ in the first bus cycle and write ‘xxD016’ to the uppermost address of a block (even

address, however) in the second bus cycle, and an auto erase operation (erase and verify) will start.

Check the FMR0 register’s FMR00 bit to see if auto erasing has finished.

The FMR00 bit is “0” during auto erasing and set to “1” when auto erasing is completed.

Check the FMR0 register’s FMR07 bit after auto erasing has finished, and the result of auto erasing

can be known. (Refer to “Full Status Check.”)

Moreover, when FMR02 bit of FMR0 register is “0” (rewriting is disable), the block erase command to

block 0 and block 1 is not received.

Figure 1.21.5 shows an example of a block erase flowchart.

Each block can be protected against erasing by a lock bit. (Refer to “Data Protect Function.”)

Writing over already programmed addresses is inhibited.

In EW1 mode, do not execute this command on any address at which the rewrite control program is

located.

In EW0 mode, the microcomputer goes to read status register mode at the same time auto erasing

starts, making it possible to read the status register. The status register bit 7 (SR7) is cleared to “0” at

the same time auto erasing starts, and set back to “1” when auto erasing finishes. In this case, the

microcomputer remains in read status register mode until the Read Array or Read Lock Bit Status

command is written next.



Status RegisterThe status register indicates the operating status of the flash memory and whether an erase or program-

ming operation terminated normally or in error. The status of the status register can be known by reading

the FMR0 register’s FMR00, FMR06, and FMR07 bits.

Table 1.21.3 shows the status register.

In EW0 mode, the status register can be read in the following cases:

(1) When a given even address in the user ROM area is read after writing the Read Status Register

command

(2) When a given even address in the user ROM area is read after executing the Program, Block Erase,

Erase All Unlocked Block, or Lock Bit Program command but before executing the Read Array

command.

Sequencer Status (SR7 and FMR00 Bits )

The sequence status indicates the operating status of the flash memory. SR7 = 0 (busy) during auto

programming and auto erase is set to “1” (ready) at the same time the operation finishes.

Erase Status (SR5 and FMR07 Bits)

Refer to “Full Status Check.”

Program Status (SR4 and FMR06 Bits)

Refer to “Full Status Check.”

Table 1.21.3. Status Register

• D0 to D7: Indicates the data bus which is read out when the Read Status Register command is executed.Status register

bit

SR4 (D4)

SR5 (D5)

SR7 (D7)

SR6 (D6)

Status nameContents

SR1 (D1)

SR2 (D2)

SR3 (D3)

SR0 (D0)

Program status

Erase status

Sequencer status

Reserved

Reserved

Reserved

Reserved

"1"

Ready

Terminated in error

Terminated in error

-

-

-

-

-

"0"

Busy

Terminated normally

Terminated normally

-

-

-

-

-Reserved

FMR0register

bitFMR00

FMR07

FMR06

Value afterreset

1

0

0

• The FMR07 bit (SR5) and FMR06 bit (SR4) are cleared to “0” by executing the Clear Status Register

command.

• When the FMR07 bit (SR5) or FMR06 bit (SR4) = 1, the Program and Block Erase are not accepted.



Full Status CheckWhen an error occurs, the FMR0 register’s FMR06 to FMR07 bits are set to “1”, indicating occurrence

of each specific error. Therefore, execution results can be verified by checking these status bits (full

status check). Table 1.21.4 lists errors and FMR0 register status. Figure 1.21.6 shows a full status

check flowchart and the action to be taken when each error occurs.

Table 1.21.4. Errors and FMR0 Register Status

FMR00 register

(SRD register)

status Error Error occurrence condition

FMR07 FMR06

(SR5) (SR4)

1 1 Command • When any commands are not written correctly

sequence error • A value other than ‘xxD016’ or ‘xxFF16’ is written in the second

bus cycle of the block erase command (Note 1)

• When the block erase command is executed on protected blocks

• When the program command is executed on protected blocks1 0 Erase error • When the block erase command is executed on unprotected

blocks but the blocks are not automatically erased correctly0 1 Program error • When the program command is executed on unprotected blocks

but the blocks are not automatically programmed correctly.

Note 1: The flash memory enters read array mode by writing command code ‘xxFF16’ in the second bus

cycle of these commands. The command code written in the first bus cycle becomes invalid.



Full status check

FMR06 =1and

FMR07=1?

NO

Command sequence error

YES

FMR07=0?

YES

Erase errorNO

(1) Execute the Clear Status Register command to clear these status flags to “0”.

(2) Reexecute the command after checking that it is entered correctly.

(1) Execute the Clear Status Register command to clear the erase status flag to “0”.

(2) Reexecute the Block Erase command.

Note 3: If FMR06 or FMR07 = 1, neither the Program nor Block Erase command is accepted. Execute the Clear Status Register command before executing those commands.

FMR06=0?

YES

Program errorNO

Full status check completed

Note 1: If the error still occurs, the block in error cannot be used.

(1) Execute the Clear Status Register command to clear the erase status flag to “0”.

(2) Reexecute the Program command.Note 2: If the error still occurs, the block in error

cannot be used.

[During programming]

Figure 1.21.6. Full Status Check and Handling Procedure for Each Error



Standard Serial I/O ModeThe standard serial I/O mode inputs and outputs the software commands, addresses and data needed to

operate (read, program, erase, etc.) the internal flash memory using the serial I/O port UART1. The serial

I/O mode transfers the data serially in 8-bit units.

In the standard serial I/O mode the CPU executes a control program for flash memory rewrite (using the

CPU's rewrite mode), rewrite data input and so forth. It is started when both the P15 (CE) pin and the

CNVss pin are in “H” level after the reset is released. (In normal operation mode, set CNVss pin to “L”

level.) The main clock f1 is 5.12 MHz in this mode.

This control program is written in the boot ROM area when the product is shipped.

There are actually two standard serial I/O modes: mode 1, which is clock synchronized, and mode 2, which

is asynchronized. Standard serial I/O switches between mode 1 (clock synchronous) and mode 2 (clock

asynchronous) depending on the level of CLK1 pin when the reset is released.

To use standard serial I/O mode 1 (clock synchronous), set the CLK1 pin to “H” level and release the reset.

The operation uses the four UART1 pins CLK1, RxD1, TxD1 and RTS1 (BUSY). The CLK1 pin is the

transfer clock input pin through which an external transfer clock is input. The TxD1 pin is for CMOS output.

The RTS1 (BUSY) pin outputs an “L” level when ready for reception and an “H” level when reception starts.

In mode 1, be sure the TxD1 (P67) pin is at high before reset being deasserted.

To use standard serial I/O mode 2 (clock asynchronous), set the CLK1 pin to “L” level and release the

reset. The operation uses the two UART1 pins RxD1 and TxD1.

In standard serial input/output mode, the user ROM area can be rewritten while the microcomputer is

mounted on-board by using a serial programmer suitable for the M16C/62P group. For more information

about serial programmers, contact the manufacturer of your serial programmer. For details on how to use,

refer to the user’s manual included with your serial programmer.

Table 1.22.3 lists pin functions (flash memory standard serial input/output mode). Figures 1.22.1 to 1.22.2

show pin connections for serial input/output mode.

ID Code Check FunctionThis function determines whether the ID codes sent from the serial programmer and those written in the

flash memory match. (Refer to the description of the functions to inhibit rewriting flash memory version.)



ID Code Check Function (D-version only, see Table 1.1.4 for D-version)The ID code of “ALeRASE” in ASCII code is used for forced erase function. The ID code of “Protect” in

ASCII code is used for standard serial I/O mode disable function. Table 1.22.1 lists Reserved Word of ID

Code. All ID code storage addresses and data must match the combinations listed in Table 1.22.1. When

the forced erase function or standard serial I/O mode disable function is not used, use another combination

of ID codes.

Table 1.22.1. Reserved Word of ID Code

FFFDFh

FFFE3h

FFFEBh

FFFEFh

FFFF3h

FFFF7h

FFFFBh

41h (upper-case A)

4Ch (upper-case L)

65h (lower-case e)

52h (upper-case R)

41h (upper-case A)

53h (upper-case S)

45h (upper-case E)

50h (upper-case P)

72h (lower-case r)

6Fh (lower-case o)

74h (lower-case t)

65h (lower-case e)

63h (lower-case c)

74h (lower-case t)

ALeRASE Protect

ID1

ID2

ID3

ID4

ID5

ID6

ID7

ID Code Storage AddressReserved word of ID Code (ASCII)

All ID code storage addresses and data must match the combinations listed in Table 1.22.1.



Standard Serial I/O Mode Disable Function (D-version only, see Table 1.1.4 for D-

version)Use the standard serial I/O mode disable function in standard serial I/O mode. When the ID codes in the ID

code stored addresses are set to “Protect” in ASCII code (see Table 1.22.1 “Reserved Word of ID Code”),

the MCU does not communicate with the serial programmer. Therefore, the flash memory cannot be read,

written or erased by the serial programmer.

When the ID codes are set to “Protect”, and the ROMCP1 bits in the ROMCP register are set to other than

“11” (ROM code protect enabled), ROM code protection cannot be disabled by the serial programmer.

Therefore, the flash memory cannot be read, written or erased by the serial or parallel programmer.

Forced Erase Function (D-version only, see Table 1.1.4 for D-version)Use the forced erase function in standard serial I/O mode. When the reserved word, “ALeRASE” in ASCII

code, are sent from the serial programmer as ID codes, the contents of the user ROM area will be erased

at once. However, if the ID codes stored in the ID code storage addresses are set to a reserved word other

than “ALeRASE” (other than the combination table listed in Table 1.22.1), and the ROMCP1 bits in the

ROMCP register are other than “11” (ROM code protect enabled), the forced erase function is ignored and

ID code check is executed by the ID code check function. Table 1.22.2 lists conditions and functions for

forced erase function.

When both the ID codes sent from the serial programmer and the ID codes stored in the ID code storage

addresses correspond to the reserved word “ALeRASE”, the user ROM area will be erased. However,

when the serial programmer sends other than “ALeRASE”, even if the ID codes stored in the ID code

storage addresses are “ALeRASE”, there is no ID match and any command is ignored. The flash memory

cannot be operated.

Table 1.22.2. Forced Erase Function

The user ROM area all erase(forced erase function)

ID code check (ID code check function. No ID match)

ID code check (ID code check function)

ID code check (ID code check function)

ConditionFunctionID code from serial

function programmer

Other than ALeRASE

ALeRASE

Other than ALeRASE (1)

Other than ALeRASE (1)

ALeRASE

ALeRASE

Code in ID code storage address

ROMCP1 bits in the ROMCP register

“11” (ROM code protect disabled)

Other than “11” (ROM code protect enabled)

—

—

—

Note 1: For the combination of the stored addresses is “Protect”, refer to “Standard Serial I/O Mode Disable Function”.



Pin Description

VCC,VSSApply the voltage guaranteed for Program and Erase to Vcc pin. Apply 0 V to Vss pin.

CNVSS Connect to Vcc pin.

RESET

XIN Connect a ceramic resonator or crystal oscillator between XIN and XOUT pins. To input an externally generated clock, input it to XIN pin and open XOUT pin.XOUT

VDCCN Input "H" level signal.

VCCA, VSSA

VREF

Please connect AVcc to Vcc and connect AVss to Vss.

Input the standard voltage of a preamplifier and an operational amplifier.

Input "H" or "L" level signal or open.

Standard serial I/O mode 1: BUSY signal output pinStandard serial I/O mode 2: Monitors the boot program operation check signal output pin.

Standard serial I/O mode 1: Serial clock input pin Standard serial I/O mode 2: Input "L."

Serial data input pin.

Serial data output pin. (Note 1)


P60 to P63

P90 to P92


P64/RTS1

P65/CLK1

P66/RXD1


P67/TXD1

P15

P70, P71, P73, P74, P76

P80, P81, P83, P84, P85

Signal name

Power supply input

CNVSS

Reset input

Clock input

Clock output

Analog power supply input

Standard voltage input

Input port P6

BUSY output

SCLK input

RxD input

TxD output

CE input

Input port P7

Input port P8

Input port P11

I/O

I

I

I

I

O

O

O

I

I

I

I

I

I

I

I

Input "H" level signal.

Reset input pin. While RESET pin is "L" level, input a 20 cycle or longer clock to XIN pin.

Note 1: When using standard serial input/output mode 1, the TxD pin must be held high while the RESET pin is pulled low. Therefore, connect this pin to Vcc1 via a resistor. Because this pin is directed for data output after reset, adjust the pull-up resistance value in the system so that data transfers will not be affected.

Table 1.22.3. Functional explanation of pin (flash memory standard serial I/O mode)



Example of Circuit Application in the Standard Serial I/O ModeFigure 1.22.1 and 1.22.2 show example of circuit application in standard serial I/O mode 1 and mode 2,

respectively. Refer to the user's manual for serial programmer to handle pins controlled by a serial

programmer.

Figure 1.22.1. Circuit Application in Standard Serial I/O Mode 1

Clock input

BUSY output

Data input

Data output

BUSY

SCLK

TXD

CNVss

P15(CE)

RESET

RxD

Reset input

User reset signal

Microcomputer

(1) Control pins and external circuitry will vary according to programmer. For more information, see the programmer manual.(2) In this example, modes are switched between single-chip mode and standard serial

input/output mode by controlling the CNVss input with a switch.(3) If in standard serial input/output mode 1 there is a possibility that the user reset

signal will go low during serial input/output mode, break the connection between the user reset signal and RESET pin by using, for example, a jumper switch.



Figure 1.22.2. Circuit Application in Standard Serial I/o Mode 2

Monitor output

Data input

Data output

BUSY

SCLK

TxD

CNVss

P15(CE)

RxD

Microcomputer

(1) In this example, modes are switched between single-chip mode and standard serial input/output mode by controlling the CNVss input with a switch.



ROM Code Protect FunctionThe ROM code protect function inhibits the flash memory from being read or rewritten. (Refer to the

description of the functions to inhibit rewriting flash memory version.)

M16C/6S Group IT800AFE (Analog Front End)


IT800AFE (Analog Front End)

1. The block diagram of analog front endAnalog front end (AFE) part is the circuit located between M16C/6S and a power line, and M16C/6S

build in DAC, preamplifier, and ADC. There are the following two signal circuits in AFE.

(1)Transmitting circuit:It drives with the signal from the logic of M16C/6S inside, and this is consists of

DAC with a differential output, Output filter for spectrum adjustment, Differential line driver amplifier and

line coupling circuit which drive power line.

(2)Receiving circuit:This is consists of Line coupling circuit, Differential preamplifier, Input filter group

and ADC. Line coupling circuit is common to both transmission and reception.

(1)Transmitting path

The characteristics required for transmitting path are as follows.

(a)A suitable output signal level is obtained on specific load.

(b)Frequency characteristic is flat in signal bandwidth.

(c)The signal level outside a zone: It is less than each regulation.

This system assumes operation in the following three fundamental signal zones.

(a)The U.S., Japan: 120k to 400kHz

(b)Europe in door: 95k to 125kHz(CENELEC B Band)

(c)Europe out door: 20k to 80kHz(CENELEC A Band)

It is necessary to perform the change of a signal zone by change of adjustment of change of the

configuration of IT800, the analog filter to a signal zone, or output electric power, and the output imped-

ance of the line driver stage (notes).

Note. Please refer to the following standard and style about the conditions outside a signal level or a

zone.

(a)The U.S.:FCC standard, part 15

(b)Europe:CENELEC standard, EN 50065-1

(c)Japan:ARIB STD-T84

M16C/6S

OutputFilter

Input FilterPreAmp

ChannelFilters

LineDriver Power line

LineDriver

DAC

ADC

Figure 1.23.1 Analog Front End circuit block diagram



About DAC (Digital to Analog Converter)DAC of built-in in M16C/6S is current output type 10 bit DAC. The standard level of output current can

be set up by the external resistance linked to a built-in standard power supply. A DAC circuit and a load

circuit are shown in Figure 1.23.2. The typical characteristic is shown in Table 1.23.1.

Figure 1.23.2 DAC (Digital to Analog Converter)

10 bit DAC

D9-D0DATA

10

Rext

LSI internal connection

External pin (pin number) IFULL(mA)=2131/Rext(

At Rext=2.1k=Iout+Ioutc

Iout

Ioutc

Vref +

-

Cout33pF

Rout2.1k(1%)

Rext2.1k(1%)

Routc2.1k(1%)

Coutc33pF

8

7

6

MatrixCurrent

Cell LineDriverAmp

)

, IFULL=1mA

Table 1.23.1 DAC Electrical Characteristics (Vdd=3.3±0.3V, Ta = -20 to 85°C/-40 to 85°C/-40 to 105°C

unless otherwise specified)

Rext=2.1k

Rext=2.1k

Rext=2.1k

Rext=2.1k

Rout/Routc=2.1k

Vref

Iref

Rext

Rout/Routc

IFULL

Voutmax

Standard voltage

Maximum output voltage

Standard current

External standard register

DAC output register

Full-scale current

ConditionSymbolElectrical Characteristics

MaxTypMinUnitParameter

0.3

0.14

2.1

2.0

1.1

Vdd-1

0.9 1

V

V

mA

mA

k

k



In the circumference of a DAC circuit, it is cautious of the following point and a constant is set up.

(a)Full-scale output current of DAC

Although the current by which DAC is outputted to a pin (Iout/Ioutc) according to the change width of an

internal bit changes, total is fixed and serves as full-scale output current (IFULL). This IFULL can be set

up by the following formula.

IFULL=2131/Rext(mA)

The unit of Rext is Ω

Since about 1mA of an IFULL value is the optimal value, Rext is 2.1kΩ.

DAC is total and Iout/Ioutc changes between 0 to IFULL at 1024 steps by the full range for a change

width of 10 bits.

The value of Iout/Ioutc is expressed with the following formula if the step value which converted the 10-

bit binary input into decimal is set to d. (d=0 to 1023)

Iout=IFULL/1023*d

Ioutc=IFULL/1023*(1023-d)

(b)About DAC load resistance

Resistance (Rout/Routc) is connected to a DAC output pin.In this resistance, signal voltage occurs by

the current (Iout/Ioutc) which flows, respectively. In order to maintain the linearity of Iout/Ioutc, it is neces-

sary to set up Rout/Routc so that this potential may not exceed maximum 2V. Since Iout/Ioutc is mostly

set to one half of IFULL(s) at the time of a non-signal (balanced state), the signal voltage (Vout/Voutc) of

a DAC output pin is set to below:

Vout=Rout X Iout

Voutc=Routc X Ioutc

Since the recommendation value of Vout/Voutc at the time of a non-signal is about 1V, in Rext=2.1kΩ,

Rout/Routc serves as 2.1kΩ.

The capacitor (Cout/Coutc) for output filters cuts the high frequency ingredient of DAC, and sets it up

on balance with necessary zone frequency.



Figure 1.23.3 Consists of Preamp circuit

0.1 F

3.3V

10k

Vref

M16C/6S

Pre_BOut

10k

Pre-InP

Pre-InN

Input filter Amplifier

Buffer

GVO=0dB

No-load

DC to 1MHz

DC to 1MHz

DC to 1MHz

Vdd

Vof

GVO

BW

CMIR

CMRR

PSRR

Standard voltage

Common mode rejection ratio

Power supply rejection ratio

Input off-set voltage

Open loop gain

Gain band width

Common mode input range

MaxTypMin

3.3 3.6

15

70

4030

5

3.0

0.7 Vdd-0.7

V

dB

dB

mV

V

dB

MHz

ConditionSymbolElectrical Characteristics

UnitParameter

(2)Receiving circuit(a)Preamplifier

A preamplifier circuit consists of two CMOS operational amplifiers as shown in Figure 1.23.3, the first

opamp is connected as gain stage with gain of 20dB and the second opamp is connected as a voltage

follower for driving of external filter.

Table 1.23.2 Preamp Electrical Characteristics (Ta = 25°C unless otherwise specified)



(b)ADC (Analog to Digital Converter)

The output of the channel filter (maximum of three) connected outside is connected to 1 bit ADC which

consists of an operational amplifier and a comparator.

M16C/6S build in ADC of three equivalent performances. The circuit of one ADC has composition

shown in the following figure.

Three ADC use all three by the signal zone to be used. The constant of a filter is set up as shown in the

following table.

Figure 1.23.4 ADC block diagram

Table 1.23.3 The example of an ADC part constant setting

C1

R1

33

33

10

R2 R3

10 12

10

C2 C3 Unit

Unit

Parts

Parts

Register

Capacitor

Application characteristic

Application characteristic

FCC/ARIB

CECLEC-B

FCC/ARIB

CECLEC-B

10 pF

pF

22

AMP1_IN/

AMP1_Out/AMP2_Out/ CH1_InP/CH2_InP/CH3_InPAMP3_Out

AMP2_IN/AMP3_IN/

Vref

CH1_InN/CH2_InN/ FB1/FB2/FB3CH3_InN

3.3V

10k

10k

1k

R1/R2/R3

C1/C2/C3

ChannelFilter

Amplifier

Comparator+

+-

-

0.22 F

0.1 F

0.1 F

M16C/6S Group Usage Notes


Usage NotesRegister Setting

Immediate values should be set in the registers containing write-only bits. When establishing a new value

by modifying a previous value, write the previous value into RAM as well as the register. Change the

contents of the RAM and then transfer the new value to the register.



Power ControlWhen entering wait mode, insert a JMP.B instruction before a WAIT instruction. Do not excute any instruc-

tions which can generate a write to RAM between the JMP.B and WAIT instructions. Disable the DMA

transfers, if a DMA transfer may occur between the JMP.B and WAIT instructions. After the WAIT instruc-

tion, insert at least 4 NOP instructions. When entering wait mode, the instruction queue reads ahead the

instructions following WAIT, and depending on timing, some of these may execute before the MCU enters

wait mode.

Program example when entering wait mode

Program Example: JMP.B L1 ; Insert JMP.B instruction before WAIT instruction

L1:

FSET I ;

WAIT ; Enter wait mode

NOP ; More than 4 NOP instructions

NOP

NOP

NOP

When entering stop mode, insert a JMP.B instruction immediately after executing an instruction which

sets the CM10 bit in the CM1 register to 1, and then insert at least 4 NOP instructions. When entering stop

mode, the instruction queue reads ahead the instructions following the instruction which sets the CM10

bit to 1 (all clock stops), and, some of these may execute before the MCU enters stop mode or before the

interrupt routine for returning from stop mode.

Program example when entering stop mode

Program Example: FSET I

BSET CM10 ; Enter stop mode

JMP.B L2 ; Insert JMP.B instruction

L2:

NOP ; More than 4 NOP instructions

NOP

NOP

NOP

Stop mode and wait mode is cancelled by a hardware reset or an interrupt. if an interrupt is to be used to

cancel stop mode and wait mode that interrupt must first have been enabled, and the priority level of the

interrupt which is not used to cancel must have been changed to 0.



Changing the Interrupt Generate FactorIf the interrupt generate factor is changed, the IR bit in the interrupt control register for the changed interrupt

may inadvertently be set to 1 (interrupt requested). If you changed the interrupt generate factor for an

interrupt that needs to be used, be sure to clear the IR bit for that interrupt to 0 (interrupt not requested).

“Changing the interrupt generate factor” referred to here means any act of changing the source, polarity or

timing of the interrupt assigned to each software interrupt number. Therefore, if a mode change of any

peripheral function involves changing the generate factor, polarity or timing of an interrupt, be sure to clear

the IR bit for that interrupt to 0 (interrupt not requested) after making such changes. Refer to the description

of each peripheral function for details about the interrupts from peripheral functions.

Figure 1.24.1 shows the procedure for changing the interrupt generate factor.

Figure 1.24.1 Procedure for Changing the Interrupt Generate Factor

Changing the interrupt source

Disable interrupts (2,3)

Change the interrupt generate factor (including a mode change of peripheral function)

Use the MOV instruction to clear the IR bit to 0 (interrupt not requested) (3)

Enable interrupts (2,3)

End of change

IR bit: A bit in the interrupt control register for the interrupt whose interrupt generate factor is to be changed.

1. The above settings must be executed individually. Do not execute two or more settings simultaneously (using one instruction).2. Use the I flag for the INTi interrupt (i = 0 to 5). For the interrupts from peripheral functions other than the INTi interrupt, turn off the peripheral function that is the source of the interrupt in order not to generate an interrupt request before changing the interrupt generate factor. In this case, if the maskable interrupts can all be disabled without causing a problem, use the I flag. Otherwise, use the corresponding bits ILVL2 to ILVL0 for the interrupt whose interrupt generate factor is to be changed.3. Refer to Rewrite the Interrupt Control Register for details about the instructions to use and the notes to be taken for instruction execution.

NOTES:



Watchdog Timer InterruptInitialize the watchdog timer after the watchdog timer interrupt occurs.

DMAC

Write to DMAE Bit in DMiCON Register (i = 0 to 1)When both of the conditions below are met, follow the steps below.

(a) Conditions

• The DMAE bit is set to 1 again while it remains set (DMAi is in an active state).

• A DMA request may occur simultaneously when the DMAE bit is being written.

(b) Procedure

(1) Write 1 to the DMAE bit and DMAS bit in DMiCON register simultaneously (1).

(2) Make sure that the DMAi is in an initial state (2) in a program.

If the DMAi is not in an initial state, the above steps should be repeated.

NOTES:

1. The DMAS bit remains unchanged even if 1 is written. However, if 0 is written to this bit, it is set to 0

(DMA not requested). In order to prevent the DMAS bit from being modified to 0, 1 should be written to

the DMAS bit when 1 is written to the DMAE bit. In this way the state of the DMAS bit immediately

before being written can be maintained.

Similarly, when writing to the DMAE bit with a read-modify-write instruction, 1 should be written to the

DMAS bit in order to maintain a DMA request which is generated during execution.

2. Read the TCRi register to verify whether the DMAi is in an initial state. If the read value is equal to a

value which was written to the TCRi register before DMA transfer start, the DMAi is in an initial state. (If

a DMA request occurs after writing to the DMAE bit, the value written to the TCRi register is 1.) If the

read value is a value in the middle of transfer, the DMAi is not in an initial state.



Timers

Timer A

Timer A (Timer Mode)The timer remains idle after reset. Set the mode, count source, counter value, etc. using the TAiMR (i = 0

to 4) register and the TAi register before setting the TAiS bit in the TABSR register to 1 (count starts).

Always make sure the TAiMR register is modified while the TAiS bit remains 0 (count stops) regardless

whether after reset or not.

While counting is in progress, the counter value can be read out at any time by reading the TAi register.

However, if the TAi register is read at the same time the counter is reloaded, the read value is always

FFFF16. If the TAi register is read after setting a value in it, but before the counter starts counting, the read

value is the one that has been set in the register.

Timer A (Event Counter Mode)The timer remains idle after reset. Set the mode, count source, counter value, etc. using the TAiMR (i = 0

to 4) register, the TAi register, the UDF register, bits TAZIE, TA0TGL, and TA0TGH in the ONSF register

and the TRGSR register before setting the TAiS bit in the TABSR register to 1 (count starts).

Always make sure bits TAZIE, TA0TGL, and TA0TGH in the TAiMR register, the UDF register, the ONSF

register, and the TRGSR register are modified while the TAiS bit remains 0 (count stops) regardless

whether after reset or not.

While counting is in progress, the counter value can be read out at any time by reading the TAi register.

However, if the TAi register is read at the same time the counter is reloaded, the read value is always

FFFF16 when the timer counter underflows and 000016 when the timer counter overflows. If the TAi

register is read after setting a value in it, but before the counter starts counting, the read value is the one

that has been set in the register.



Timer A (One-shot Timer Mode)The timer remains idle after reset. Set the mode, count source, counter value, etc. using the TAiMR (i = 0

to 4) register, the TAi register, bits TA0TGL and TA0TGH in the ONSF register and the TRGSR register

before setting the TAiS bit in the TABSR register to 1 (count starts).

Always make sure bits TA0TGL and TA0TGH in the TAiMR register, the ONSF register, and the TRGSR

register are modified while the TAiS bit remains 0 (count stops) regardless whether after reset or not.

When setting TAiS bit to 0 (count stop), the followings occur:

• A counter stops counting and a content of reload register is reloaded.

• TAiOUT pin outputs “L”.

• After one cycle of the CPU clock, the IR bit in TAiIC register is set to 1 (interrupt request).

Output in one-shot timer mode synchronizes with a count source internally generated. When the external

trigger has been selected, a maximun delay of one cycle of the count source occurs between the trigger

input to TAiIN pin and output in one-shot timer mode.

The IR bit is set to 1 when timer operation mode is set with any of the following procedures:

• Select one-shot timer mode after reset.

• Change an operation mode from timer mode to one-shot timer mode.

• Change an operation mode from event counter mode to one-shot timer mode.

To use the timer Ai interrupt (the IR bit), set the IR bit to 0 after the changes listed above have been made.

When a trigger occurs while the timer is counting, the counter reloads the reload register value, and

continues counting after a second trigger is generated and the counter is decremented once. To generate

a trigger while counting, space more than one cycle of the timer count source from the first trigger and

generate again.

When selecting the external trigger for the count start conditions in timer A one-shot timer mode, do

generate an external trigger 300ns before the count value of timer A is set to 000016. The one-shot

timer does not continue counting and may stop.



Timer A (Pulse Width Modulation Mode)The timer remains idle after reset. Set the mode, count source, counter value, etc. using bits TA0TGL and

TA0TGH in the TAiMR (i = 0 to 4) register, the TAi register, the ONSF register and the TRGSR register

before setting the TAiS bit in the TABSR register to 1 (count starts).

Always make sure bits TA0TGL and TA0TGH in the TAiMR register, the ONSF register and the TRGSR

register are modified while the TAiS bit remains 0 (count stops) regardless whether after reset or not.

The IR bit is set to 1 when setting a timer operation mode with any of the following procedures:

• Select the PWM mode after reset.

• Change an operation mode from timer mode to PWM mode.

• Change an operation mode from event counter mode to PWM mode.

To use the timer Ai interrupt (interrupt request bit), set the IR bit to 0 by program after the above listed

changes have been made.

When setting TAiS register to 0 (count stop) during PWM pulse output, the following action occurs:

• Stop counting.

• When TAiOUT pin is output “H”, output level is set to “L” and the IR bit is set to 1.

• When TAiOUT pin is output “L”, both output level and the IR bit remains unchanged.



Serial I/O

Clock-Synchronous Serial I/O

Transmission/receptionWith an external clock selected, and choosing the RTS function, the output level of the RTSi pin goes to

“L” when the data-receivable status becomes ready, which informs the transmission side that the recep-

tion has become ready. The output level of the RTSi pin goes to “H” when reception starts. So if the RTSi

pin is connected to the CTSi pin on the transmission side, the circuit can transmission and reception data

with consistent timing. With the internal clock, the RTS function has no effect.

TransmissionWhen an external clock is selected, the conditions must be met while if the CKPOL bit in the UiC0 register

is set to 0 (transmit data output at the falling edge and the receive data taken in at the rising edge of the

transfer clock), the external clock is in the high state; if the CKPOL bit in the UiC0 register is set to 1

(transmit data output at the rising edge and the receive data taken in at the falling edge of the transfer

clock), the external clock is in the low state.

• The TE bit in UiC1 register is set to 1 (transmission enabled)

• The TI bit in UiC1 register is set to 0 (data present in UiTB register)

• If CTS function is selected, input on the CTSi pin is set to “L”

Reception

In operating the clock-synchronous serial I/O, operating a transmitter generates a shift clock. Fix settings

for transmission even when using the device only for reception. Dummy data is output to the outside from

the TxDi pin when receiving data.

When an internal clock is selected, set the TE bit in the UiC1 register (i = 0 to 2) to 1 (transmission

enabled) and write dummy data to the UiTB register, and the shift clock will thereby be generated. When

an external clock is selected, set the TE bit in the UiC1 register (i = 0 to 2) to 1 and write dummy data to

the UiTB register, and the shift clock will be generated when the external clock is fed to the CLKi input pin.

When successively receiving data, if all bits of the next receive data are prepared in the UARTi receive

register while the RE bit in the UiC1 register (i = 0 to 2) is set to 1 (data present in the UiRB register), an

overrun error occurs and the UiRB register OER bit is set to 1 (overrun error occurred). In this case,

because the content of the UiRB register is undefined, a corrective measure must be taken by programs

on the transmit and receive sides so that the valid data before the overrun error occurred will be retrans-

mitted. Note that when an overrun error occurred, the SiRIC register IR bit does not change state.

To receive data in succession, set dummy data in the lower-order byte of the UiTB register every time

reception is made.

When an external clock is selected, make sure the external clock is in high state if the CKPOL bit is set to

0, and in low state if the CKPOL bit is set to 1 before the following conditions are met:

• The RE bit in the UiC1 register is set to 1 (reception enabled)

• The TE bit in the UiC1 register is set to 1 (transmission enabled)

• The TI bit in the UiC1 register= 0 (data present in the UiTB register)



UART Mode

Special Mode 1 (I2C bus Mode)When generating start, stop and restart conditions, set the STSPSEL bit in the U2SMR4 register to 0 and

wait for more than half cycle of the transfer clock before setting each condition generate bit (STAREQ,

RSTAREQ and STPREQ) from 0 to 1.

SI/O3, SI/O4The SOUTi default value which is set to the SOUTi pin by the SMi7 bit approximately 10ns may be output

when changing the SMi3 bit from 0 (I/O port) to 1 (SOUTi output and CLKfunction) while the SMi2 bit in

the SiC (i=3 and 4) to 0 (SOUTi output) and the SMi6 bit is set to 1 (internal clock). And then the SOUTi

pin is held high-impedance.

If the level which is output from the SOUTi pin is a problem when changing the SMi3 bit from 0 to 1, set the

default value of the SOUTi pin by the SMi7 bit.

Programmable I/O Ports

The input threshold voltage of pins differs between programmable input/output ports and peripheral func-

tions.

Therefore, if any pin is shared by a programmable input/output port and a peripheral function and the

input level at this pin is outside the range of recommended operating conditions VIH and VIL (neither

“high” nor “low”), the input level may be determined differently depending on which side—the program-

mable input/output port or the peripheral function—is currently selected.



Flash Memory Version

Functions to Inhibit Rewriting Flash Memory RewriteID codes are stored in addresses 0FFFDF16, 0FFFE316, 0FFFEB16, 0FFFEF16, 0FFFF316, 0FFFF716,

and 0FFFFB16. If wrong data are written to theses addresses, the flash memory cannot be read or written

in standard serial I/O mode.

The ROMCP register is mapped in address 0FFFFF16. If wrong data is written to this address, the flash

memory cannot be read or written in parallel I/O mode.

In the flash memory version of MCU, these addresses are allocated to the vector addresses (“H”) of fixed

vectors. The b3 to b0 in address 0FFFFF16 are reserved bits. Set these bits to 11112.

Regarding Programming/Erasure Times and Execution TimeAs the number of programming/erasure times increases, so does the execution time for software com-

mands (Program, and Block Erase).

The software commands are aborted by hardware reset 1, brown-out detection reset (hardware reset 2),

and watchdog timer interrupt. If a software command is aborted by such reset or interrupt, the affected

block must be erased before reexecuting the aborted command.

Definition of Programming/Erasure Times“Number of programs and erasure” refers to the number of erasure per block.

If the number of program and erasure is n (n=100) each block can be erased n times. For example, if a 8K

byte block A is erased after writing 1 word data 4096 times, each to a different address, this is counted as

one program and erasure. However, data cannot be written to the same address more than once without

erasing the block. (Rewrite prohibited)

Boot ModeAn undefined value is sometimes output in the I/O port until the internal power supply becomes stable

when “H” is applied to the CNVSS pin and “L” is applied to the RESET pin.

When setting the CNVSS pin to “H”, the following procedure is required:

(1) Apply an “L” signal to the RESET pin and the CNVSS pin.

(2) Bring VCC to more than 2.7V, and wait at least 2 msec. (Internal power supply stable waiting time)

(3) Apply an “H” signal to the CNVSS pin.


When the CNVSS pin is “H” and RESET pin is “L”, P67 pin is connected to the pull-up resister.

M16C/6S Group APPENDIX


APPENDIX

IT800DLL Explanatory Note

June 2, 2005

IT800 Data Link Layer – Functionality and Advantages

1. Scope

This document describes the functionality of the Data Link Layer (DLL) implemented in the products

based on Yitran's IT800 technology for narrowband networking using the power line wiring.

The purpose of this document is to emphasize the advantages of the embedded algorithms and mecha-

nisms of the DLL and to analyze the scenarios of using other implementations of a Data Link Layer.

2. Network Reference Module

The DLL is the 2nd layer of the 7 layers in the OSI network reference model illustrated in Figure 1(a).

According to this model, data is transported upstream and downstream between subsequent layers,

where the communication between layers of different communication nodes is basically carried out be-

tween the same layers [Figure 1(b)].

Figure 1: Network Reference Model

The Physical Layer (PHY) defines the electrical specifications for activating, the physical link between the

communicating network system nodes. The DLL algorithms are designed to establish and manage a

unique access channel between any two nodes as optimally and fairly as possible while minimizing the

probability of collisions.

The IT800 DLL was developed by Yitran especially for the IT800 PHY and using the DLL optimize the

utilization of the PHY and thus optimizes the overall performance.

The IT800 DLL implementation manages the time critical sessions of the interface with the PHY and uses

the knowledge of the PHY implementation for optimal interrupt decoding and efficient interface interac-

tions. The DLL takes advantage of various PHY features such as multiple transportation modes and the

ability to create special packets and signals, enabling optimal utilization of the media channel while pro-

viding the most reliable data transfer.

Application

Upper Layers

LayerCommunication

DataTransport

Physical Layers

(a) OSI 7 Layers Model (b) Data Transport and Layer Communication

Presentation

Session

Transport

Network

DLL

PHY

Layer 3

Layer 2

Layer 1

Layer 3

Layer 2

Layer 1

STOP

Copyright © 2005, YITRAN Communications Ltd.




June 2, 2005

3. IT800DLL Main functions

The DLL main functions and mechanisms are described in the following table:

As can be seen from the table above, the IT800 DLL implements enhanced functionality, provides best

performance in terms of channel access and throughput (based on Carrier Sense signaling, Adaptive

Back-off algorithm and packet prioritization), reliable data transfer (using acknowledgement and repeti-

tion mechanisms, multi-hop transmissions and packet filtering) and allows easy integration of IT800

based solution with different protocol stacks. Another important advantage of using IT800DLL is assuring

the co-existence between different IT800 based products operating in the same environment.

Function Description

Carrier sense Provides the carrier detection (CD) signal for triggering the mediaaccess algorithms as a function of the PHY correlator output, whichindicates the probability of a signal on the line.

Channel accessprioritization

Determines the sequence and time of packet transmissions for a PLCnode, where the highest priority packet nodes participate in the DLLcontention for the media access.

Adaptive back-off Spreads the time over which a PLC node contends for the channelusing a uniform distribution of the transmissions number over a givenperiod of time (Yitran patent pending). This mechanism provides highefficiency of the network functionality, optimal utiliziation of thechannel and sustains a viable network even in cases where many nodescontend for the channel simultaneously.

Acknowledgement Serves for informing the transmitting node about the success orfailure of a packet delivery to a target node by means of a traffic-freeacknowledgement window.

Repetitive un-acknowledgement

This mechanism is used for transmitting packets a pre-determinednumber of times without requiring a reception acknowledgement fromthe target node.

Multiple hop broadcast Retransmits single-network broadcast packets and CNC (ControlNetwork Channel) messages to all the nodes participating in the samelogical network.

Fragmentation andreassembly

Transfers packets longer than the maximal packet size allowed by thePHY by means of fragmentation in the transmitting node andreassembly in the receiving node

Packet filtering Filters received packets according to their type for transferring onlypre-defined types of messages to the upper layers and rejecting impostornode or other types of messages that are not required.





June 2, 2005

4. Other DLL implementationsIn case of using other implementations of the DLL or considering such implementations, please be ad-

vised to consider the following issues:

1. Co-existence: Implementing a different channel access scheme, prioritization levels, packet for-

mats and so forth, will not allow your product to co-exist with other IT800 based products that

may share the same medium. Using the IT800 will enable such co-existence regardless of the

product, the vendor, the application and the protocol used in top of the DLL.

2. Required Knowledge, Time to Market and Cost: Interfacing the DLL is much easier than inter-

facing the PHY. Physical layer interface includes handling of a several interrupts, critical timing

sections and so forth. To be able to do so you require very good understanding of the both the

power line medium and the PHY internal mechanisms and will significantly increase the develop-

ment resources and schedule and as a result the time to market and product cost. In addition

note that not all the PHY internal mechanism can be disclosed as some are in the status of

patent-pending.

3. Overall performance: IT800DLL has been tested and integrated into different Control and Auto-

mation products over many years. The implementation has showed the best performance for

Narrowband Power Line communication modem, when all the algorithms implemented in it were

verified using the networking simulations and in real systems.

5. SummaryAs a conclusion, we highly recommend to using IT800 DLL implementation in all type of products using

the IT800 PHY, rather than using the latter by itself.

In case you still wish to self implement the DLL layer, please be sure to consult RENESAS support

engineers.


A - 1

REVISION HISTORY M16C/6S Group

Rev. Date Description

Page Summary

1.00 Jun 25, 2003 - First edition issued

2.00 Aug 18, 2003 P1 L7 is changed.

P2 T1.1.1 is changed.

P3 F1.1.1 is changed.





P9 L5 and F1.2.1 are changed.

P12 Table of register is changed.







P27 L2 and F1.7.1 are changed.



P33 L4 to L5 and F1.7.6 are changed.

P36 L5 is changed.







P62 L2 is changed.



P85 L3 and T1.12.2 are changed.




P94 L13 is changed.



P107 F1.14.2 and F1.14.3 are changed.


A - 2


Page Summary

2.00 Aug 18, 2003 P121 PT1.16.4 is changed.



– Special Mode 3 is deleted.

P139 L10 to L11 and L17 to L19 and L21 and L30 to L32 and L38 to L40 are changed.












P158 L2 is changed.

P159 L2 is changed.

P162 L3 to L4 are deleted. T1.20.2 is changed.

P163 1.Memory Map is changed. F1.20.1 is changed.

P164 Boot Mode is changed.


P168 is changed.




P174 T1.21.2 is changed. Read Array Command is changed.

P175 Program Command is changed.

P176 Block Erase is changed.

P177 Sequencer Status and T1.21.3 are changed.






P184 Parallel I/O Mode and User ROM and Boot ROM Areas are deleted.

A - 3


Page Summary

2.01 Oct 27, 2003 P3 L1 to L2 are changed. F1.1.1 is changed.P7 T1.1.3 is changed.P22 L3 to L4 are changed.P23 (3) Setting PLC Mode is changed. T1.6.4 and F1.6.1 and F1.6.2 are changed.

P141 F1.18.4 is changed.P143 F1.18.6 is changed.P144 F1.18.7 is changed.P178 Standard Serial I/O Mode is changed.

3.00 Jul 22, 2004 P1 Table of Contents is changed.P2 T1.1.1 is changed.P4 T1.1.2 is changed.P5 F1.1.2 is changed.P6 F1.1.3 is changed.P7 T1.1.3 is changed.P9 F1.2.1 is changed.P22 Text is changed. T1.6.1 is deleted.P23 Text is changed. T1.6.4 and F1.6.2 are deleted. Table name of T1.6.3 is added.P26 T1.7.1 is changed.P27 F1.7.1 is changed.P32 Text is changed. F1.7.6 is changed.P33 Text is changed.P36 Text is changed.P37 T1.7.4 is changed.P38 Text is changed.P44 T1.7.7, F1.7.9 and text are deleted.P45 Text is changed.P46 F1.9.1 is changed.P48 Text is changed (NMI Interrupt is deleted.)P49 T1.9.1 is changed.P55 T1.9.5 is changed.P58 F.1.9.8 is changed.P59 F.1.9.9 is changed.

BetweenText is deleted (NMI Interrupt is deleted.)P60 to P61

P63 Text is deleted (NMI Interrupt is deleted.)P79 F.1.12.4 is changed.

P137 Text is changed.P140 F.1.18.3 is changed.P147 T.1.18.1 is changed.P148 F.1.18.10 is changed.P149 T.1.19.1 is changed.P150 T.1.19.2 is changed. Deletion of a voltage display of a header.P151 Deletion of a voltage display of a header.P152 Deletion of a voltage display of a header.

A - 4


Page Summary

3.00 Jul 22, 2004 P153 T.1.19.6 is changed. Deletion of a voltage display of a header.

P154 T.1.19.7 is changed. Deletion of a voltage display of a header.

155 Deletion of a voltage display of a header.

P156 Deletion of a voltage display of a header.

P157 T.1.19.15 is changed.





P170 Text is changed.

P180 IT800AFE (Analog Front End) is added.

P181 F.1.23.2 is changed.

P183 Text is changed. T.1.23.2 is changed.


3.01 Feb 17, 2005 - Words standardized (On-chip Oscillator).

P7 T.1.1.3 addition and changed.

P34 L11-L12 addition and changed.

P38 L2-L5 addition and deleted.

P42 T.1.7.6 part of deleted.

P157 L19 is deleted.

4.00 Aug 05, 2005 P1 Text is changed.

P5 F.1.1.2 is changed. T.1.1.3 and F.1.1.3 are added.




P61 Text is changed. F.1.9.11 is changed.

P66 Text is changed. F.1.10.1 is changed.





P86 P86 is added.





P105 L1-L13 are added.



Description

Page Summary

A - 5

Rev. Date

4.00 Aug 05, 2005 P110 T.1.15.2 is changed.







P130 Text is changed.

P137 L2, L5-L6 and L12 are changed.

P147 Note is added.





P188 to Appendix is added.

P190

5.00 Apr 24, 2009 1 Overview “AMR (Automatic Meter Reading)” → “smart metering”

2 Table 1.1.1 Operating Ambient Temperature “-40 to 105°C” is added.

3 Table 1.1.2 “Error Correction” → “Error Correction/Detection”

About Firmware “(Product name: D2DL)” is added.

5 Table 1.1.3 is revised.

Table 1.1.4 is added.

Figure 1.1.2 is revised.

6 Table 1.1.5 and 1.1.6 are added.

Figure 1.1.3 is revised.

8 Table 1.1.7 P85 is revised.

13 Address 000416 After reset “000000002” → “XXXX0X002”

Address 000516 After reset “000010002” → “00XX10102”

24 Table 1.6.3 title is added.

25 Figure 1.6.2 After reset “000000002” → “XXXX0X002”

“000000112 (CNVSS pin =“H”)” is deleted.

Figure 1.6.3 After reset “0X0010002” → “00XX10X02”

28 Figure 1.7.1 is revised.

33 (1) Main Clock “Xin” → “XIN”

41 “Figure 1.7.8...transition.” is deleted.

42 Figure 1.7.8 Note 1 to Note 4 are revised.

61 Figure 1.9.10 Note 1 “INT5IC” → “INT3IC”

66 Watchdog Timer “If a sub-clock is...no matter how the WDC7 bit is set.” is deleted.


Description

Page Summary

5.00 Apr 24, 2009 92 “UARTi (i=0 to 2)” is revised.

117 Table 1.16.1 “Error detection” is revised.

147 Table 1.18.1 title “(Excluding Analog Pins)” is added.

148 Figure 1.18.10 title “(Excluding Analog Pins)” is added.

149 Table 1.19.1 Topr is revised, Note 1 is revised.

150 Table 1.19.2 “VCC1” → “VCC” , Note 1 is revised.

152 Table 1.19.5 Note is deleted.

153 Table 1.19.6 Note is revised.

154 Table 1.19.7 Standard “95” is added. Note is revised.

155 to 157 Timing Requirements “-20 to 85°C” → “-20 to 85°C/-40 to 85°C/-40 to 105°C”

160 parallel writer → parallel programmer

Table 1.20.1 “Block 0 to 5” → “Block 0 to 4”

“See Figure 20.2.1 to 20.2.3” → “See Figure 1.20.1”

161 “The boot ROM area is located ... in parallel input/output mode.” → “The boot

ROM area is reserved. The rewrite control program ... the area cannot be rewritten.”

164 “In CPU mode, only the user ROM area ... the boot ROM area cannot be rewritten.” is deleted.

178 Standard Serial I/O Mode “The main clock f1 is 5.12 MHz in this mode.” is added.

180 serial writer → serial programmer

183 (1)Transmitting path is revised.

184 Table 1.23.1 title “-20 to 85°C” → “-20 to 85°C/-40 to 85°C/-40 to 105°C”

186 Table 1.23.2 title “-25°C” → “25°C”


188 to 197 “Usage Notes” is added.

200 4. Other DLL implementations “the last three years” → “many years”

5.01 Dec 10, 2009 2 Table 1.1.1 Memory Capacity; ROM is revised

5 Table 1.1.4 “M306S0F8DGP” is added,

Figure 1.1.2 ROM capacity “8: 64K bytes” is added

10 Figure 1.2.1 Internal ROM “64K bytes” is added, Note 1 is revised

26 Figure 1.6.4 Internal ROM “64K bytes” is added

161 Figure 1.20.1 is added

162 Figure 1.20.2 title “(ROM Capacity 96K bytes)” is added.

5.02 Dec 25, 2012 2 Table 1.1.1. Performance outline of M16C/6S group is revised, Note 2 is revised

5 Table 1.1.3. Product List (1) M16C/6S is revised

6 Table 1.1.5. Product Code (1) M16C/6S is revised

15 Note 2 is deleted

37 Table 1.7.2. Note is deleted

151 Table 1.19.3. Flash Memory Version Electrical Characteristics is revised

Note 3 is revised, Note 6 is deleted

160 Table 1.20.1 Flash Memory Version Specifications is revised, Note 1 is revised

A - 6

Rev. Date

Description

Page Summary

5.02 Dec 25, 2012 180, 181 ID Code Check Function, Forced Erase Function, Standard Serial I/O Mode

Disable Function are added

Rev. Date

A - 7

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General Precautions in the Handling of MPU/MCU Products

The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes on the products covered by this manual, refer to the relevant sections of the manual. If the descriptions under General Precautions in the Handling of MPU/MCU Products and in the body of the manual differ from each other, the description in the body of the manual takes precedence.

1. Handling of Unused Pins Handle unused pins in accord with the directions given under Handling of Unused Pins in the manual. The input pins of CMOS products are generally in the high-impedance state. In operation

with an unused pin in the open-circuit state, extra electromagnetic noise is induced in the vicinity of LSI, an associated shoot-through current flows internally, and malfunctions occur due to the false recognition of the pin state as an input signal become possible. Unused pins should be handled as described under Handling of Unused Pins in the manual.

2. Processing at Power-on The state of the product is undefined at the moment when power is supplied. The states of internal circuits in the LSI are indeterminate and the states of register

settings and pins are undefined at the moment when power is supplied. In a finished product where the reset signal is applied to the external reset pin, the states of pins are not guaranteed from the moment when power is supplied until the reset process is completed. In a similar way, the states of pins in a product that is reset by an on-chip power-on reset function are not guaranteed from the moment when power is supplied until the power reaches the level at which resetting has been specified.

3. Prohibition of Access to Reserved Addresses Access to reserved addresses is prohibited. The reserved addresses are provided for the possible future expansion of functions. Do

not access these addresses; the correct operation of LSI is not guaranteed if they are accessed.

4. Clock Signals After applying a reset, only release the reset line after the operating clock signal has become stable. When switching the clock signal during program execution, wait until the target clock signal has stabilized. When the clock signal is generated with an external resonator (or from an external

oscillator) during a reset, ensure that the reset line is only released after full stabilization of the clock signal. Moreover, when switching to a clock signal produced with an external resonator (or by an external oscillator) while program execution is in progress, wait until the target clock signal is stable.

5. Differences between Products Before changing from one product to another, i.e. to one with a different part number, confirm that the change will not lead to problems. The characteristics of MPU/MCU in the same group but having different part numbers may

differ because of the differences in internal memory capacity and layout pattern. When changing to products of different part numbers, implement a system-evaluation test for each of the products.

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