mixed signal chip design lab analog-to-digital converters jaehyun lim, kyusun choi department of...
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![Page 1: Mixed Signal Chip Design Lab Analog-to-Digital Converters Jaehyun Lim, Kyusun Choi Department of Computer Science and Engineering The Pennsylvania State](https://reader036.vdocument.in/reader036/viewer/2022062320/56649cff5503460f949d12e4/html5/thumbnails/1.jpg)
Mixed Signal Chip Design Lab
Analog-to-Digital Converters
Jaehyun Lim, Kyusun Choi
Department of Computer Science and Engineering
The Pennsylvania State University
CSE598A/EE597G Spring 2006
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Mixed Signal Chip Design Lab
ADC Glossary
DNL (differential nonlinearity)
- measure of the maximum deviation from the ideal step size of 1 LSB
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Mixed Signal Chip Design Lab
ADC Glossary
INL (integral nonlinearity)
- deviation of the entire transfer function from the ideal function
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Mixed Signal Chip Design Lab
ADC Glossary
Offset Error
- difference between the ideal LSB transition to the actual transition point
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Mixed Signal Chip Design Lab
ADC Glossary
Gain Error
- how well the slope of the actual transfer function matches the slope of the ideal transfer function
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Mixed Signal Chip Design Lab
ADC Glossary
Resolution- number of discrete values it can produce
Monotonic- digital output code always increases as the ADC a
nalog input increases Full scale
- voltage range ADC can accept Aliasing
- due to unwanted signals beyond the Nyquist limit- to prevent, all undesired signals must be filtered
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Mixed Signal Chip Design Lab
ADC Glossary
SINAD (signal-to-noise and distortion)- RMS value of the output signal to the RMS value o
f all of the other spectral components below half the clock frequency
ENOB (effective number of bits)- dynamic performance of an ADC at a specific inpu
t frequency and sampling rate
02.6
76.1SINAD
ENOB
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Mixed Signal Chip Design Lab
High Speed ADC Architecture
Flash ADC
- highest speed
- large # of comparators
- large size
- large power consumption
- 8-bit maximum resolution
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Mixed Signal Chip Design Lab
High Speed ADC Architecture
Two-Step Flash ADC
- SHA
- D/A converter
- subtractor
- coarse flash ADC (MSB)
- find flash ADC (LSB)
- reduce # of comparators
2N-1 2(2N/2-1)
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Mixed Signal Chip Design Lab
High Speed ADC Architecture
Pipelined ADC
- multi-stage conversion
- high speed
- acceptable power
- each stage has SHA, ADC, DAC, subtractor, Amp
- different conversion step concurrently
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Mixed Signal Chip Design Lab
High Speed ADC Architecture
Folding ADC
- no SHA (flash)
- reduce # of comparators
(two step flash)
- small area, high speed
- rounding problem
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Mixed Signal Chip Design Lab
Time-Interleaved ADC
- multiple ADCs in parallel high speed
- offset/gain mismatch
- phase skew
High Speed ADC Architecture
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Mixed Signal Chip Design Lab
And More ADC Architectures
Algorithmic ADC
- low power, small size, slow
Integrating-Type ADC
- high accuracy, simple architecture, very slow
Successive Approximation ADC
R&C / C&R Type ADC
Interpolating ADC
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Mixed Signal Chip Design Lab
Design Consideration – Flash ADC
Large Input Capacitance
• parallel structure of 2N-1 comparators
• limits speed performance
• large size buffer Bubble / Sparkle
• no SHA, comparator mismatch…
• error in thermometer code
• solution : 3-input NAND
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Mixed Signal Chip Design Lab
Design Consideration – Flash ADC
Metastability
• input to ADC ≈comparator reference
• indeterminate output error
• solution : latch pipelining (extra gain)
gray encoding (no signal split)
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Mixed Signal Chip Design Lab
Clock Distribution and Timing
• clock travels long distance on a large ADC chip
• different delay, different loading
Kickback Noise
• disturbs reference
Design Consideration – Flash ADC
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Mixed Signal Chip Design Lab
Design Consideration – Two-Step Flash ADC
Subtractor Gain
• without gain stage– output of subtractor = 1-LSB of coarse ADC– difficult comparator design
(offset < 1-LSB of fine ADC)
• with gain stage– delay– mismatch between subtractor output and fine
ADC input full scale
missing code / nonmonotonicity
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Mixed Signal Chip Design Lab
Design Consideration – Two-Step Flash ADC
Nonlinearity
SHA
Vin
residue
Vin
residue
including errors- gain mismatch- DNL, INL- offset- ...
analoginput
tlevel digitized by coarse ADC
level sensed by subtractor
t1 t2
ΔV
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Mixed Signal Chip Design Lab
Design Consideration – Pipelined Flash ADC
MDAC (Multiplying D/A Converter)
- performs subtractor, gain amplifier, S/H, and DAC
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Mixed Signal Chip Design Lab
Design Consideration – Pipelined Flash ADC
MDAC Operation removes offset
(2N-1)·C·Vin + C·VinQi =
= 2N·C·Vin
Vx
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Mixed Signal Chip Design Lab
Design Consideration – Pipelined Flash ADC
MDAC Operation
Qf = 2N·C·DVref + C·Vo
from Qin=Qf, Vo = 2N(Vin-DVref)
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Mixed Signal Chip Design Lab
Design Consideration – Folding ADC
Rounding Problem- only linear at zero-crossings
limits resolution to ~10 bits
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Mixed Signal Chip Design Lab
Design Consideration – Folding ADC
Multiple Folds
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Mixed Signal Chip Design Lab
Two-Step Flash ADC Implementation
SHA
4-bit Coarse ADC
3-bit Fine ADC
Resistor-String DAC
Voltage Subtractor
Amplifier
Registers
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Mixed Signal Chip Design Lab
Coarse ADC
Two-Step Flash ADC Implementation
Fat-Tree EncoderBubble Correction
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Mixed Signal Chip Design Lab
Coarse ADC
Two-Step Flash ADC Implementation
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Mixed Signal Chip Design Lab
Resistor-String DAC
• voltage scaling DAC
• simple
• fast
• small (under 8-bit)
• resistor mismatching
Two-Step Flash ADC Implementation
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Mixed Signal Chip Design Lab
Resistor-String DAC
Two-Step Flash ADC Implementation
00011111
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Mixed Signal Chip Design Lab
SHA
Two-Step Flash ADC Implementation
input
output
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Mixed Signal Chip Design Lab
Voltage Subtractor
Two-Step Flash ADC Implementation
V1
V2
8 x (V1-V2)
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Mixed Signal Chip Design Lab
Things To Be Done
• voltage subtractor and gain amplifier
- input voltage range for the subtractor
- output offset
- proper gain setting (input range of fine ADC)
• 3-bit fine ADC
- identical to the 4-bit coarse ADC
Two-Step Flash ADC Implementation