motivation for lecture cmos symboler cmos transistors. mos ... · pinch-off p v-n + n + v ds gs...

Viktor Öwall, Inst. för Elektro- och Informations Teknologi, Lunds Universitet, www.eit.lth.se!

Digital Integrated Circuits

Viktor Öwall


Motivation for Lecture

•  To see how standard gates are implemented with transistors?

•  How does technology affect the performance, e.g. speed and power consumption?

•  What has happened with technology scaling?


For digital design we use CMOS transistors.

p- N-Channel

Gate Drain Source

n+ n+

Solid State Physics V DS [V]

I D

V GS

I d

Electrical Characteristics

gmVgs goVgs Vds

drain

source

gate Small Signal Model (amplifier design)

GND

VDD

Digital – transistor as a switch


CMOS symboler

gate

drain

source

NMOS PMOS

Most common when digital design

The Bulk/Substrate is assumed to be connected to GND/VDD if nothing else specified.


p -

n + n +

Gate Drain Source

substrat

Courtesy of Intel


N-channel A channel when a positive gate-source voltage, VGS, larger than the threshold voltage is applied, VT, is applied appliceras.

MOS transistor N-channel

0 ( 2 2 )T T F SB FV V Vγ φ φ= + − + − −

p -

n + n +

Gate Drain Source

Gate-oxid (isolerande)

substrat

F Fermi Potentialφ =


Depletion

p - Depletion

Region

n + n +

V GS >0

VGS > 0; e- charge is attracted

Source Drain Gate


A channel is created

p - Depletion

Region

n + n +

V GS >V T

N-kanal

VGS > 0; e- laddningar attraheras

VGS > VT, Strong inversion a channel

Source Drain Gate


Linjära Regionen 0 < VDS < VGS-VT

e- (elektroner) from Source to Drain

p -

n + n +

V GS >V T

V DS <V GS -V T

I D

x

Source Drain Gate


ID as a function of VDS

V DS [V]

I D

V GS

V GS

V GS

Linear Region

Increasing VGS


Pinch-off

p -

n + n +

V GS >V T

V DS =V GS -V T

I D

When VDS = VGS-VT No new charge to the channel

The current saturates

TGS VxVV >− )(Channel voltage

Source Drain Gate


Slope due to velocity saturation in short channel devices

V DS [V]

I D V GS

V GS

V GS

Linear

Saturation

Pinch-off TGSDS VVV −=

ID as a function of VDS


ID as a function of VGS Linear Saturation

What is ID when VGS=0? Viktor Öwall, Inst. för Elektro- och Informations Teknologi, Lunds Universitet, www.eit.lth.se!

DrainSource Gate

CDB

n+n+

CG

CGDCGS

CSB

Xd

tox

Kapacitanser

Bulk Cap. Junction Cap. Overlap Cap.


NMOS transistor as a switch

V DS [V]

I D

V GS

V GS

V GS vin

vin=“low” a “open”

vin=“high” a “short”

Increasing VGS

G S

D


PMOS transistor as a switch

V DS [V]

I D

V GS

V GS

V GS

vin

VDD

G D

S

vin=“high” a “open”

vin=“low” a “short”


The CMOS Inverter

GND

VDD


GND

V DD

“high” in a NMOS “short” PMOS “open”

Out connected to GND a “low”

CMOS Inverter with transistorn as a switch


GND

V DD

I D


“high” in a NMOS “short” PMOS “open”


GND

V DD

“low” in a NMOS “open” PMOS “short”

Out connected to VDD a “high”



The CMOS Inverter

GND

VDD


CMOS Inverter

VOUT

VIN

Ideal ”Real”

”Vdd/2”

V OUT N Off P Lin

V IN

N Lin P Off

N Sat P Sat

N Sat P Lin

N Lin P Sat


P-Substrate

N-Well

N-Channel

P-Channel


V DD

A B

B

GND

A

A B OUT

0 1

1 1 1

0 0

0 OUT

Truth Table

Logic gates, NAND


Logic gates, NAND V

DD

A B

B

GND

A

A B OUT

0 1

1 1 1

0 0

0 1 1 1 0 OUT

Sanningstabell


V DD

B

GND

A B OUT

0 1

1 1 1

0 0

0 1 1 1 0 OUT

Sanningstabell A

A

B

Logic gates, NAND


V DD

B

GND

A B OUT

0 1

1 1 1

0 0

0 1 1 1 0 OUT

Sanningstabell A

A

B

Logic gates, NAND


V DD

B

GND

A B OUT

0 1

1 1 1

0 0

0 1 1 1 0 OUT

Sanningstabell A

A

B

Logic gates, NAND


V DD

B

GND

A B OUT

0 1

1 1 1

0 0

0 1 1 1 0 OUT

Sanningstabell A

A

B

Logic gates, NAND


Logic Gates, AND

A

GND

B

AND

VddVdd

NAND

PMOS

NMOS

GND

Vdd

&

US

A B NAND

0 1

1 1 1 0

0 0 1

1 1 0

NAND + Inverter a AND

Europe

V DD A B

B

NAND f

GND

AND f A

AND

0 0 0 1


Two Input NAND/ AND

0.8 m

CMOS

NAND

Inverter


Logic Function?

V DD

A

B

B

GND

A

A B OUT

OUT

Sanningstabell

0 1

1 1 1

0 0

0


Logic Function: NOR

V DD

A

B

B

GND

A

A B OUT

OUT

Sanningstabell

0 1

1 1 1

0 0

0 0

0 0

1

≥ 1

US Europe


This is called Complementary Logic

V DD

A B

B

GND

A OUT Properties:

+ rail to rail swing , i.e.out = VDD or GND + ”no” static power, i.e. either PUN or PDN off - Many transistors

Pull up network

Pull down network


Pseudo-NMOS Gates V

DD

B

GND

A OUT

Pull up network

Pull down network

Properties: + fewer transistors + in the eayrly years there was only NMOS - Static power consumption -  Low input ”not 0”


Pseudo-NMOS Gates V

DD

B

GND

A OUT

Pull up network

Pull down network

Properties: + fewer transistors - Static power consumption -  Low input ”not 0”


More complex functions: an adder

i+1 b i+1 a i b i a

i cin

i+1 cout

msb b msb a

msb cin

msb cout

Memory digit

lsb = least signifcant bit

msb = most signifcant bit

sumi sumi+1 summsb

What is the maximum delay?


More complex functions: a carry ripple adder

i+1 b i+1 a i b i a

i cin

i+1 cout

msb b msb a

msb cin

msb cout

Memory digit

lsb = least signifcant bit

msb = most signifcant bit

sumi sumi+1 summsb

What is the maximum delay?

Max delay?

Max delay


Full Adder in CMOS, 1 bit

C o

C B A B

A A

B B A

C

C C

C

C

A A

A A

B B

B

B

S

V DD

V DD V DD

V DD S C o

A and B: in C: memory in S: sum Co: memory out


14 bitars adderare


Some properties:

•  Speed •  Power consumption

L is what we refer to as the process/technology/… node e.g. 45nm, 32nm,…


Speed, simplified model

Reduced capacitance give faster circuits: smaller transistors a less capacitance

2L

)( TDD

DDpd VVk

VCT−⋅=

fkVCTDD

Lpd

1==

if TDD VV >>

Big approximation today!


The distance between VDD and VT has been reduced.

Shouri Chatterjee, Yannis Tsividis and Peter Kinget, Analog Circuit Design Techniques at 0.5V Viktor Öwall, Inst. för Elektro- och Informations Teknologi, Lunds Universitet, www.eit.lth.se!

Speed, a simplified model

Reduced capacitance give faster circuits: smaller transistors, i.e. new technologies a less capacitance

Clock frequency is proportional to VDD. Why not increase it? Why not decrease VT?

2L

)( TDD

DDpd VVk

VCT−⋅=

fkVCTDD

Lpd

1==

if TDD VV >>

Big approximation today!


Power consumption in CMOS

staticcircuit-shortdynamictotal PPPP ++=

Traditionally the most important!

Gaining more importance with

technology scaling


Dynamic Power Consumption

Charge"

V"DD"

Discharge"

2dynamic L DDP f C V=

The VDD2 does that we especially want to lower VDD

a Slower circuits


Short Circuit - Current Spikes

Current peak when both N- and PMOS are open

VDD-VT

VT

Ipeak


Static Power: What is the current when input

are stable to high or low? Linear Saturation

V"DD"


Static Power Consumption due to leakage current

Ileakage increases with decreasing VT Pstat =Ileakage VDD

Drain Leakage"I"leakage"

Subthreshold"Current"

V"DD"


VT Scaling: VT and IOFF Trade-off

As VT decreases, sub-threshold leakage increases

Performance vs Leakage:

VT a IOFF

High VT

VG VTH

ln(

I DS)

IOFFH

Low VT

VTL

IOFFL


Trends in energy consumption

From upcoming book OptimizationDSP Architecture Design Essentials By Dejan Markovic (UCLA) and Robert W. Brodersen (UC Berkeley)


Example from 65nm CMOS HVT SVT LVT Full Adder delay(ns) 0,26 0,15 0,11

leakage(mW) 1,30E-8 2,20E-7 1,88E-6

Nand2 delay(ns) 0,039 0,024 0,02

leakage(mW) 1,94E-9 3,30E-8 2,24E-7

HVT, SVT & LVT: High, standard and low VT Supply voltage 1V HVT around 450mV


So what do we do?

•  High VDD needed for high speed a High Power consumption!

One possibility: parallel processing!

•  Low VT needed for high speed a High leakage power!

Two possibilities: –  Multiple VT –  Find ways to reduce leakage, e.g. power gating


The end of ”some” scaling!


Going Multicore, e.g. Intel SandyBridge!

•  32 nm – 64 bit •  4 995 000 000 Transistors •  ~3.5 GHz •  216 mm2 (10x Pentium 4)


Going sub-threshold: long pursued in research. Now: Intel September 2011!


…and new technologies!


You can learn more in ETIN20 Digital IC-design.

Next week:

Storage (registers and memories) Computational platforms

Design Methodologies

motivation for lecture cmos symboler cmos transistors. mos ... · pinch-off p v-n + n + v ds gs...

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