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ELEC4614 Power Electronics Laboratory

Experiment 4 Three-phase inverter 1 F. Rahman/March 2009

The University of New South Wales School of Electrical Engineering & Telecommunications


Experiment 4: Three-Phase DC-AC Inverter

1.0 Objectives

This experiment introduces you to a three-phase bridge inverter circuit. The switching schemes

for producing six-step quasi-squarewave and sine-modulated SPWM AC output voltages from

such a circuit will be studied and tested. Effects of modulation frequency and third harmonic

injection into the modulating waveform will also be studied.

2.0 Introduction

Inverter circuits convert DC power from a DC source to AC of a desired voltage and frequency.

Three-phase inverters are widely used in AC motor drive applications, in three-phase grid

connetion to wind generators and other power system applications.

The DC source is usually in the form of a battery, solar cell, rectified wind generator output or a

rectified DC output from the fixed AC supply from the utility. The input may have

characteristics of a voltage source or a current source. This experiment concerns a three-phase

voltage source inverter in which the input to the inverter is from an ideal DC voltage source.

2.1 Voltage-source three-phase inverter

A three-phase voltage source inverter is indicated in figure 1. It consists of three inverter legs

consisting of two transistors and two diodes which are anti-parallel to their respective transistors.

These diodes act as energy return diodes when the load current is switched off by the transistors

and the load inductance forces the current to continue to flow through suitable diodes to return

the energy trapped in the load induactances back to the DC source.

Figure 1

D6 T2 T4

T3 T1 D3

D4

D1

Vd

R

D2

D5

T6

T5

R R

C A B

N

A

B C

ia ib ic

0V

+Vd/2

Vd/2

id

Phase A Phase B Phase C

P

N


Experiment 2 2 F. Rahman/March 2009

The switching signals for each inverter leg are displaced by 120 with respect to the adjacent legs.

The output line-line voltages are determined by the potential differences between the output

terminals of each leg. Symmetrical three phase voltages across a three-phase load can be

produced by switching the devices ON for either 180 of the output voltage waveform. With

180 conduction, the switching sequence is T1T2T3 – T2T3T4 – T3T4T5 – T4T5T6 – T5T6T1 –

T6T1T2 – T1T2T3 - .... for the positive A-B-C phase sequence and the other way round for the

negative (A-C-B) phase sequence.

Whenever an upper switch in an inverter leg connected with the positive DC rail is turned ON,

the output terminal of the leg goes to potential +Vd/2 with respect to the center-tap of the DC

supply. Whenever a lower switch in an inverter leg connected with the negative DC rail is turned

ON, the output terminal of that leg goes to potential Vd/2 with respect to the center-tap of the

DC supply. Note that a center-tap of the DC supply Vd has been created by connecting two equal

valued capacitors across it. The center-tap is assumed to be at zero or earth potential. However,

this contraption is artificial and really not essential; the center-tap may not exist in practice.

2.2. Six-step square-wave inverter

In this case, each switch is turned ON for 180 . Switches T1 and T4, which belong to the left-

most inverter leg, produces the output voltage for phase A. The switching signals for T1 and T4

are complementary, as are for T3 and T6 or T5 and T2.. The switching signals for switches T3

and T6, (which are for phase B, belonging to the middle leg), are delayed by 120 from those for

T1 and T4 respectively, for the ABC phase sequence. Similarly, for the same phase sequence, the

switching signals for switches T5 and T2 are delayed from the switching signals for T3 and T6

by 120 . The phase terminal voltages at A, B and C (sometimes called respective pole voltages)

are determined by the states of the switches connected at each pole. Note that with 180

conduction (i.e., complementary switching), each pole voltage can have only two values (or

discrete states), namely dV

2 or dV

2. Considering that there are three poles, the number

possible output voltage states from the inverter are 23 = 8.

Line-line voltage waveforms

The line-line voltages, vAB, vBC and vCA are determined from the switching states at the poles) and

the DC source voltage, (Vd). Thus, when switches T1 and T3 are ON, vAB = 0V, when T1 and T6

are ON, vAB = +Vd, and so on. The line-line voltages vAB, vBC and vCA (for the +ve or ABC phase

sequence) are therefore quasi-square waveforms of 120 of ON and 60 of OFF durations, as

shown in figure 2. Each is phase displaced from its adjacent ones by 120 .

Line-neutral voltage waveforms

Line-neutral voltages are determined from the switching states and the neutral point voltage of

the load which can be found by assuming that the load consists of a balanced three-phase resistor

bank. For instance, if T1, T3 and T2 are ON, the potential of the neutral point of the load is d

2V

3

and therefore VAN and VBN will each be at potentials d

1V

3 while vCN will be at d

2V

3. Similarly,

when T4, T2 and T3 are ON, the potential of the neutral point becomes d

1V

3, As a result, the

potential vBN will become d

2V

3 and vAN and vCN will each be at d

1V .

3



T2

T1

T3

T6

T5

T4

iA 13 dV

23 dV

13 dV

23 dV

vAN

vAN

vBN

vBN iB

vCN

vCN iC

Figure 2

vAB

vCA

vBC

+Vd

Vd

+Vd

+Vd

Vd

180 360 0



Line-line voltage

The line-line output voltages are obtained by subtracting two square-wave waveforms which are

120 displaced from each other. Each of these waveforms would consist of harmonics orders 1,

3, 5, 7, 9, … and so on. Because of the 120 phase shift between the waveforms, the triplen

harmonics (of order which are multiples of 3) of both will of the same phase and hence these

cancel in the process of subtraction. Consequently, the triplen order harmonic voltages are

eliminated from the line – line voltage. The remaining harmonics are at n = 6r ± 1 where r is any

positive integer, the nth

harmonic having an amplitude 1/n times the fundamental component.

Vd

Vd

= 120 = 120 60 60

Figure 3

The line-line quasi-square output voltage waveform of figure 22.4 has amplitude Vd and duration

= 120 . Fourier series representation of this waveform is given by

= d o o o o

2 3 1 1 1V cos t cos 5 t cos 7 t cos 11 t .........

5 7 11 (1)

The RMS values of the fundamental and higher order output voltages are,

d d d dl l ,1 l l ,5 l l ,7 l l ,11

6 V 6 V 6 V 6 VV ; V ; V ; V ;

5 7 11 …. (2)

Thus, l l ,1 dV 0.78V

and dl l ,h

0.78VV

h where h = 6n 1 and n = 1, 2, 3, ….. (3)

Line-neutral voltage

The line-neutral voltage waveform for this inverter is as shown in figure 5. Fourier series

representation of this waveform is given by

60 60 60

2d3

V 1

d3V

2d3

V

1d3

V

Figure 4

= 2

· d o o o o

1 1 1V cos t cos5 t cos7 t cos11 t

5 7 11 (4)



RMS values of the fundamental and higher order terms of the line-neutral voltage are:

d d d dl n,1 l n,5 l n,7 l n,11

2 V 2 V 2 V 2 VV ; V ; V ; V ;

5 7 11 …. (5)

2.3 Crossover-protection delay

The switching transistors at the top and bottom of any one leg of the inverter must not conduct

simultaneously to prevent short circuiting the DC source. Thus, there must be a dead-time, Td

which must elapse before top and bottom transistors can change state. The duration of the dead-

time is determined by the turn-off times of the switching devices used. Typically this is of the

order of a few microseconds. Your experimental circuit includes a module which accepts a TTL

level signal and produces two switching signals for an inverter leg with a variable dead-time in

microseconds at the transitions. The timing diagram of figure 5 describes the operation of this

circuit.

A

A

A

A_

+ T1 & T2 ON T1 & T2 OFF

T3 & T4 OFFT3 & T4 ON

T T Td d d

_

Figure 5

3. Output voltage control of three-phase inverters

The output voltage of the 6-step quasi-square inverter can be adjusted, other than by adjusting

the DC source voltage. There are a number of ways in which continuously variable 3-phase

output voltage can be obtained. Only the Sinusoidal PWM (SPWM) schemes will be considered

here.

Sinusoidal PWM (SPWM)

In this scheme, three reference sinusoidal signals representing the desired output waveform of

the inverter is compared with a high frequency triangular or a sawtooth carrier waveform as

indicated in figures 6 (a) and (b). The comparator output pulse becomes proportional to the level

of the sinusoid at the centre of the pulse. (Hence the term Pulse-Width Modulation: PWM).

These outputs are used to switch the transistor pairs T1-T4 and T3-T6 and T5-T2 in figure 1 to

produce the inverter (leg) terminal voltage waveform of figure 6(c). The resulting inverter output

now has much reduced harmonics, specially the lower order ones (which are more difficult to

filter out). Figure 7 also indicates the inverter output voltage waveform and its harmonic

spectrum.

Figure 7 shows the harmonic profile of a SPWM inverter where mf = fc/fo = 7, where fo is the

output frequency and fc is the carrier frequency. M, the depth of modulation, is the ratio of the

amplitudes of the reference and the carrier waveforms.



ec,A ec,B ec,C vcw

Figure 6(a)

T1

T2

T3

T4

T5

T6

Figure 6(b)

vBC

vAB

vCA

+Vd

Vd

+Vd

Vd

+Vd

Vd

0

0

Figure 6(c)



vAB

+Vd

Vd

0

Figure 7(a)

V1

mf

mf + 2

3mf

2mf + 2 3m

f + 2

2mf

Harmonics vl-l

Figure 7(b)

Analysis of output voltage waveform

Linear Modulation Range, m < 1

Considering that the positive DC bus voltage is +Vd/2 and the negative DC bus voltage is Vd/2

with respect to the center-tap of the DC supply, the output voltage waveform of a phase leg is a

pulsewidth modulated bipolar AC waveform of magnitude = dV

2. The RMS value of the

fundamental of this voltage varies linearly with the depth of modulation m. Thus,

dAn,1

VV m

2 2 0 354. m Vd (6)

where m is the depth of modulation. This has been indicated as the line-neutral voltage because,

with SPWM and balanced three-phase load, the potential of the load neutral point and that of the

DC supply center-tap should be the same. The RMS value of the fundamental line-line voltage is

d

AB,1 d

3VV m 0.612m V

2 2 (7)

Variation of the output voltage m is indicated in figure 8. Note that with m > 1, overmodulation

occurs, and that the RMS fundamental output voltage increases with m until the output voltage

waveforms becomes quasi-square for sufficiently high m. Note also that overmodulation drops

pulses from the output and causes lower order harmonics to appear in the output.



m

1.0

l l ,1

d

V

V

0.612

3.24

0.78

Figure 8

The fundamental output voltage can be increased without dropping pulses by adding a third

harmonic to the modulating waveform as indicated in the figure below, for m > 1. It can be

shown that the fundamental line-line output voltage can be increased by 15.5% of what is by

linear modulation. Although some third harmonic voltage is added to the modulating waveform,

the third harmonic phase currents in a star connected load must always cancel. For this

c,A o o

1e m sin t m sin 3 t

6 and so on for other phases. (8)

Figure 9 shows the waveforms of the modulating and output waveforms for this scheme.

+Vd

Vd

0

Figure 9



5. Equipment

3 IGBT inverter legs with feedback diodes

1 3 phase diode rectifier module

1 LC filter comprising of one 22mH/5 A inductor and 1 capacitor bank with

four 200VDC/4600 MFD capacitors connected in two groups of two

in parallel and then in series giving a centre tap.

1 three-phase load resistor bank

3 22mH/5A inductor for load inductances

1 three-phase PWM module

1 three-channel cross-over protection module

3 isolated current transducers; 1V/1A

1 isolated voltage transducer; 1V/50V

1 four-channel oscilloscope

1 DC voltmeter and ammeter module

1 AC voltmeter and ammeter module

1 PC with digital signal processor and its interface.

1 Loadbank with switches

6. Experiment

A three-phase transistor consists of three inverter legs as shown in figure 10. The two transistors

in each leg of the inverter must be switched in a complementary manner taking into account their

dead-time requirements.

Idc

dcV C

I ac

acV

T T T

T TT

D

D

D D

D D

1

1

6 2

2

3 5

3 3

4

4

LOAD

X-OVER

PROTECTION

DELAY

Td = 10

T

TT

TT

T

1

4

3

5

6

2

.. . .. .

IBM PC

TMS320C31 DSP

BASED

CONTROLLER

COCKPIT

CONTROL

PANEL

DS

P B

OA

RD

INT

ER

FA

CE

R

R

R

L

L

L

I

IIR Y

B

To CRO To CROTo CRO

To CRO

RY

PU

LS

E W

IDT

H

MO

DU

LA

TO

R

3 P

HA

SE

41

5V

50

Hz

Filter

SW

3

SW

1

SW

2

DAC1

DAC2

DAC3

A+

A

B+

C+

B

C_

_

_

NUETRAL

sec

Figure 10



Six-step, quasi-square-wave inverter

Familiarise yourselves with the 3-phase inverter hardware comprising of the rectified DC source,

its adjustment via the autotransformer (variac), the DSP board with the digital and PWM I/O and

the three-phase load.

5.1 Close all the three load switches S1-S3 to obtain a three-phase load. Check that the same

number load resistors are selected in each phase for a balanced load. Also add three

balance inductances in series with the load resistance of each phase. Connect the BNC

leads for the switching signals, T5 and T6, for the third leg of the inverter as shown in

figure 10. Connect DAC1, DAC2 and DAC3 directly to the input of the three crossover

protection circuits to bypass the modulators. Set the dead-time in the cross-over protection

module to 10sec.

5.2 Turn the DC supply to the inverter to zero by adjusting the variac. Run Three-phase

Square-wave Inverter using the icon in the directory “Elec4614_labs_3phinverter” on the

desktop. This DSP program produces three 180 square-wave TTL logic signals at 50Hz,

which are at 120 phase displacement with each other.

Observe and sketch the inverter switching signals for each phase on the CRO, making the

time-base used on the CRO such that one full cycle of the output frequency is displayed

over full screen of the CRO.

5.3 Raise the DC link voltage to 200V slowly and record waveforms of the line-line voltage, a

line-neutral load voltage and a load current on the CRO and sketch these on your logbook.

Record the RMS values in dBv of a few harmonics, including the fundamental, of the line-

line, line-neutral voltage and of the line current using the CRO based FFT. Do not allow

the load current in any phase to exceed 4A.

Adjust the DC link supply to the inverter to zero.

3-Phase SPWM Inverter

For producing three-phase sinusoidal output voltage from an inverter, three symmetrical

sinusoidal modulating signals with 120 phase displacement with each other are each compared

with a high frequency carrier to produce switching signals for the three legs of the inverter. The

amplitudes of the modulating signals control the amplitudes of the fundamental output voltages

of the inverter directly.

5.4 Run the DSP program “Three-phase Sinewave Inverter 1 kHz” in the same directory

above. Run the DSpace Control Desk and under file menu open experiment Three-phase

Sinewave Inverter 1 kHz (D:\dSpace\work\inverter\3PHsin1kHz). Under menu

instrument, select Animation Mode.

Connect the PWM1, PWM3, PWM5 outputs of the interface box to the Crossover protector

inputs R, Y, B respectively. The rest of the inverter connections remain unchanged. Adjust

the amplitude of the modulating waveforms to about 5V peak-peak (modulating index, m

= 0.5). Observe a modulating signal and the relevant PWM switching signals for the same

phase on the CRO, after synchronising their triggering. Sketch the waveforms.

5.5 Increase the DC-link voltage to 200V slowly and observe a line-line and a line-neutral

output voltage and a phase current waveforms of the load. Tabulate the RMS values of the



fundamental and a few higher order harmonics of these waveforms in dBV using the FFT

facility of the CRO.

Vn in dBV = 20 log10 (Vnrms )

5.6. Repeat 5.5 for m in the range from 0 – 1, in steps of 0.2.

Adjust the DC link voltage to the inverter to zero.

5.7 Repeat 5.5 and 5.6 with switching frequency fs = 5kHz and 10kHz.

For fs = 5 kHz, run the DSP program Three-phase Sinewave Inverter 5 kHz using the icon

on the desktop. Under Control Desk filemenu, open experiment Three-phase Sinewave

Inverter 5 kHz (D:\dSpace\work\inverter\3PHsin5kHz). Under menu instrument,

select Animation Mode.

For fs = 10 kHz, run the DSP program Three-phase Sinewave Inverter 10 kHz using the

icon on the desktop. Under Control Desk filemenu, open experiment Three-phase

Sinewave Inverter 10 kHz (D:\dSpace\work\inverter\3PHsin10kHz). Under menu

instrument, select Animation Mode.

Adjust the DC link voltage to the inverter to zero.

5.8. Run the DSP program “Inverter with 3rd

harmonic injection 1 kHz”. Under Control Desk

filemenu open experiment Inverter with third harmonic injection 1 kHz

(D:\dSpace\work\inverter\3PHsinovm1kHz). Under menu instrument, select

Animation Mode This program adds 15.5% of 3rd

harmonic component to the modulating

signals for each phase. Slowly increase the DC link voltage to 200V.

5.9 Repeat 5.5 for m = 1, 2, 3 and 4, and record the RMS values in dBV of the fundamental

and few higher order harmonics of the line-line, and line-neutral voltage and line current of

the load.


5.10 Run the DSP program “Inverter with 3rd

harmonic injection 5 kHz”. Under filemenu

select experiment Inverter with third harmonic injection 5 kHz

(D:\dSpace\work\inverter\3PHsinovm5kHz). Under menu instrument, select

Animation Mode. Slowly increase the DC link voltage to 200V Repeat 5.9 for fs = 5 kHz


6.0 Report

6.1 Using data from section 5.3, compare the measured RMS values of the fundamental and

the the recorded harmonics of the line-line and line-neural voltages of the three-phase

quasi-square-wave inverter with their predicted values from equations 2 and 5.

6.2 Plot the measured RMS values of the fundamental and the harmonics of the line-line and

line-neutral voltages and line currents of the three-phase quasi-square-wave inverter



6.3 Comment on the observed effects of switching frequency on the SPWM inverter output

current waveform at low and high switching frequencies. Use the CRO FFT data to clarify

this.

6.4 For 0 < m < 1, plot the variation of the RMS value of the fundamental output voltage with

the depth of modulation m and discuss.

6.5 For 1 < m < 4, plot the variation of the the fundamental line-line and line-neutral voltages

with and without 3rd

harmonic injection and discuss.

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