ti ldo presentation

7/25/2019 Ti Ldo Presentation

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Design of Lowdropout voltage

Regulator- Presented By Debalina Ghosh


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Contents

Brief discussion on different component of LDO Low Dropoutvoltage Regulator!

Principle of operation of LDO

Pro"ect specification

Designed bloc# diagram and discussion

Designed schematics and discussion on design challenges

$est Bench and simulation to meet performance metrics

References


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Brief Description of components of LDO %&'

a very stable voltage withrespect to temperature

change and input voltage

variations, usually of thebandgap type.

a very high (dc) gain opamp to achievea close to zero error signal V err =V+ -V-.

eedbac! "etwor!# $% and $&define the feedbac! factor and

generate V fb to be compared withVref to get the designed output

voltage Vo

'eries ass ower *ransistor

power transistor configuration topass high current from the sourceto output. s it handles largecurrent, the size of pass transistordominates the area of the wholeseries regulator.


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Principle of operation of LDO %&'

()

*egative feedbac# loop consists of feedbac# resistorsRf+ , Rf !. error amplifier and /+

0or e1ample2 when (o 3o as load current is initially drawn from the output

capacitor 3fb as 3fb 4 Rf+5 Rf+6Rf !!3o 3a 4 7 3ref-3fb! 3o *egative feedbac# causes 3o to maintain its

original value!

8hen 3in 3gs.9L 9L is the output

transistor in the error amplifier! 3a 3o as 3o 4 3a-3B:./+ 3fb as 3fb 4 Rf+5 Rf+6Rf !!3o 3a 4 7 3ref-3fb! 3o *egative feedbac# causes 3o to

maintain its original value!


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Pro"ect ;pecification

Parameter Specification

Minimum supply voltage < 3

Maximum output current = +>) m7

Dropout voltage < )? 3

Quiescent current < &) @7 e1cluding voltage reference circuit!Output capacitor < @0

Equivalent series resistor (ESR) < A

Minimum loop-gain magnitu e = ) dB

Maximum un ers!oots an overs!oots < +)) m3

"ransient recovery time (un er # $ % m'

loa step it! % m' %# ns sle rate)< @s

Process )? @m C9O;


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Designed Bloc# diagram

Both Pictures ta#en fromhttp255www?analog-eetimes?com5en5ldo-design-techni ues-for-small-spaces-part-


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why to choose buffer stage in between :rror amplifier andPass Device E

$he ability to source high load current while achieving low drop out voltagere uires the use of Large siFe P9O; transistor as pass device?

One low fre uency dominant pole output capacitor of LDO

7nother low fre uency non dominant pole within G0 Large gatecapacitance of large P9O; pass device?

$he idea of low output resistance voltage buffer is to isolate the largecapacitor associated with the gate of pmos from the large resistance of theoutput of the gain stage?


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'maller re uired $ e can be achieved by inserting a lowoutput-resistance (% g mb ) voltage buffer

ne more pole (p ) is created but is located at high fre uencydue to small output resistance of the voltage buffer

p& (with voltage buffer) locates at a higher fre uency than theone without voltage buffer (/ b 00 / g)


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8hole LDO ;chematic


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Buffer stage design

. Source-follower implementation of theintermediate buffer stage [1].

. (a) Source-follower with shunt feedback and(b) proposed buffer with dynamically-biased

shunt feedback for output resistance reductionunder different load currents [1]


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$est Bench and simulation to

meet performance metrics8e performed types of simulations to verify theperformance of the LDO?

*oop gain simulation (ac simulation)+ 0or loop stabilityand loop gain

"ransient simulation+ 0or undershoot. overshoot.transient recovery. and dropout voltage

D, simulation+ 0or uiescent current. ma1imum outputcurrent and dropout voltage


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*oop-gain transfer function simulation

Loop gain simulation results:

No load (PM = 88.88, DC gain > 50 dB

!ull load (PM = "5.#$, DC gain > 50 dB


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"ransient simulation


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Hoomed $ransient response

LDO step load output voltage response ) I +>) m7 in +) ns! Hoomed in from the precedingplot!

$ransient recovery time 4 J ?K I J)?)+ 4 ?K @s

ndershoot worst case! 4 +?KK+& I +? K&> 4 J ? m3

Overshoot worst case! 4 +?> K I +?K J 4 J ?K m3


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D, simulation

%est &en' )or ma*imum output 'urrent and dropout +oltage at'onstant input +oltage (load regulation


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;imulation plots for load sweep red plot 4 output current.blue plot 4 dropout voltage. load 4 rload!9a1imum output current 4 )J?> m7. dropout voltage 4+>+?J m3 at constant input voltage!


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$est bench for minimum supply voltageat constant load line regulation!


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;imulation plots for supply sweep red plot 4 outputcurrent. blue plot 4 output voltage. load 4 >? A!9inimum supply voltage 4 +?J& 3


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$otal uiescent current no load! 4 ? J 6?+ 4 &.&/ 0'


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;ummary

8e summariFe the simulation results obtained in the table below and compare withthe target specifications

Parameter Specification "!is esign

Minimum supply voltage < 3 +?J& 3

Maximum output current = +>) m7 )J?> m7

Dropout voltage < )? 3 )?+> 3

Quiescent current < &) @7 e1cluding voltage reference circuit! >?> @7

Output capacitor < @0 @0

Equivalent series resistor (ESR) < A )?& A

Minimum loop-gain magnitu e = ) dB )?KK dB

Maximum un ers!oots an overs!oots < +)) m3 J ?K m3

"ransient recovery time (un er # $ % m' loa step it!

% m' %# ns sle rate)< @s ?K @7

Process )? @m C9O; )? @m C9O;


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RE1ERE2,E

+ ? 9? 7l-;hyou#h. M? Lee. and R? 7? PereF. N7 transient-enhanced low-

uiescent current low-dropout regulator with buffer impedanceattenuation. IEEE J. Solid-State Circuits . vol? & . no? >. pp? +K I+K& .'ug. 3##4.

3. http255www?analog-eetimes?com5en5ldo-design-techni ues-for-small-spaces-part-

. G? Palmisano and G? Palumbo. N7 Compensation ;trategy for $wo-;tage C9O; Opamps Based on Current Buffer 5 (::: $R7*;7C$(O*; O*C(RC ($; 7*D ; ;$:9;Q(2 0 *D79:*$7L $M:OR 7*D 7PPL(C7$(O*;.3OL? &&. *O? . 97RCM +JJK?

&? Class note of Prof? Moi Lee?


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